-/* jit/i386/codegen.h - code generation macros and definitions for i386
+/* src/vm/jit/i386/codegen.h - code generation macros and definitions for i386
- Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
- R. Grafl, A. Krall, C. Kruegel, C. Oates, R. Obermaisser,
- M. Probst, S. Ring, E. Steiner, C. Thalinger, D. Thuernbeck,
- P. Tomsich, J. Wenninger
+ Copyright (C) 1996-2005, 2006, 2007, 2008
+ CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
This file is part of CACAO.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA.
-
- Contact: cacao@complang.tuwien.ac.at
-
- Authors: Andreas Krall
- Christian Thalinger
-
- $Id: codegen.h 1041 2004-04-26 17:11:08Z twisti $
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
*/
#ifndef _CODEGEN_H
#define _CODEGEN_H
-#include "global.h"
-#include "jit.h"
+#include "config.h"
+#include "vm/types.h"
+#include "vm/jit/i386/emit.h"
-/* define x86 register numbers */
-#define EAX 0
-#define ECX 1
-#define EDX 2
-#define EBX 3
-#define ESP 4
-#define EBP 5
-#define ESI 6
-#define EDI 7
+#include "vm/jit/jit.hpp"
-/* preallocated registers *****************************************************/
+#if defined(ENABLE_LSRA)
+/* let LSRA allocate reserved registers (REG_ITMP[1|2|3]) */
+# define LSRA_USES_REG_RES
+#endif
-/* integer registers */
-
-#define REG_RESULT EAX /* to deliver method results */
-#define REG_RESULT2 EDX /* to deliver long method results */
-#define REG_ITMP1 EAX /* temporary register */
-#define REG_ITMP2 ECX /* temporary register */
-#define REG_ITMP3 EDX /* temporary register */
+/* additional functions and macros to generate code ***************************/
-#define REG_NULL -1 /* used for reg_of_var where d is not needed */
+#define CALCOFFSETBYTES(var, reg, val) \
+ if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
+ else if ((s4) (val) != 0) (var) += 1; \
+ else if ((reg) == EBP) (var) += 1;
-#define REG_ITMP1_XPTR EAX /* exception pointer = temporary register 1 */
-#define REG_ITMP2_XPC ECX /* exception pc = temporary register 2 */
-#define REG_SP ESP /* stack pointer */
+#define CALCIMMEDIATEBYTES(var, val) \
+ if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
+ else (var) += 1;
-/* floating point registers */
-#define REG_FRESULT 0 /* to deliver floating point method results */
-#define REG_FTMP1 6 /* temporary floating point register */
-#define REG_FTMP2 7 /* temporary floating point register */
-#define REG_FTMP3 7 /* temporary floating point register */
+#define ALIGNCODENOP \
+ do { \
+ for (s1 = 0; s1 < (s4) (((ptrint) cd->mcodeptr) & 7); s1++) \
+ M_NOP; \
+ } while (0)
-/* macros to create code ******************************************************/
+/* MCODECHECK(icnt) */
-typedef enum {
- I386_AL = 0,
- I386_CL = 1,
- I386_DL = 2,
- I386_BL = 3,
- I386_AH = 4,
- I386_CH = 5,
- I386_DH = 6,
- I386_BH = 7,
- I386_NREGB
-} I386_RegB_No;
-
-
-/* opcodes for alu instructions */
-
-typedef enum {
- I386_ADD = 0,
- I386_OR = 1,
- I386_ADC = 2,
- I386_SBB = 3,
- I386_AND = 4,
- I386_SUB = 5,
- I386_XOR = 6,
- I386_CMP = 7,
- I386_NALU
-} I386_ALU_Opcode;
-
-typedef enum {
- I386_ROL = 0,
- I386_ROR = 1,
- I386_RCL = 2,
- I386_RCR = 3,
- I386_SHL = 4,
- I386_SHR = 5,
- I386_SAR = 7,
- I386_NSHIFT = 8
-} I386_Shift_Opcode;
-
-typedef enum {
- I386_CC_O = 0,
- I386_CC_NO = 1,
- I386_CC_B = 2, I386_CC_C = 2, I386_CC_NAE = 2,
- I386_CC_BE = 6, I386_CC_NA = 6,
- I386_CC_AE = 3, I386_CC_NB = 3, I386_CC_NC = 3,
- I386_CC_E = 4, I386_CC_Z = 4,
- I386_CC_NE = 5, I386_CC_NZ = 5,
- I386_CC_A = 7, I386_CC_NBE = 7,
- I386_CC_S = 8, I386_CC_LZ = 8,
- I386_CC_NS = 9, I386_CC_GEZ = 9,
- I386_CC_P = 0x0a, I386_CC_PE = 0x0a,
- I386_CC_NP = 0x0b, I386_CC_PO = 0x0b,
- I386_CC_L = 0x0c, I386_CC_NGE = 0x0c,
- I386_CC_GE = 0x0d, I386_CC_NL = 0x0d,
- I386_CC_LE = 0x0e, I386_CC_NG = 0x0e,
- I386_CC_G = 0x0f, I386_CC_NLE = 0x0f,
- I386_NCC
-} I386_CC;
-
-
-/* modrm and stuff */
-
-#define i386_address_byte(mod, reg, rm) \
- *(mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | (((rm) & 0x07)));
-
-
-#define i386_emit_reg(reg,rm) \
- i386_address_byte(3,(reg),(rm));
-
-
-#define i386_is_imm8(imm) \
- (((int)(imm) >= -128 && (int)(imm) <= 127))
-
-
-#define i386_emit_imm8(imm) \
- *(mcodeptr++) = (u1) ((imm) & 0xff);
-
-
-#define i386_emit_imm16(imm) \
+#define MCODECHECK(icnt) \
do { \
- imm_union imb; \
- imb.i = (int) (imm); \
- *(mcodeptr++) = imb.b[0]; \
- *(mcodeptr++) = imb.b[1]; \
+ if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
+ codegen_increase(cd); \
} while (0)
-#define i386_emit_imm32(imm) \
+/* M_INTMOVE:
+ generates an integer-move from register a to b.
+ if a and b are the same int-register, no code will be generated.
+*/
+
+#define M_INTMOVE(a,b) \
do { \
- imm_union imb; \
- imb.i = (int) (imm); \
- *(mcodeptr++) = imb.b[0]; \
- *(mcodeptr++) = imb.b[1]; \
- *(mcodeptr++) = imb.b[2]; \
- *(mcodeptr++) = imb.b[3]; \
+ if ((a) != (b)) \
+ M_MOV(a, b); \
+ } while (0)
+
+#define M_LNGMOVE(a,b) \
+ do { \
+ if (GET_HIGH_REG(a) == GET_LOW_REG(b)) { \
+ assert((GET_LOW_REG(a) != GET_HIGH_REG(b))); \
+ M_INTMOVE(GET_HIGH_REG(a), GET_HIGH_REG(b)); \
+ M_INTMOVE(GET_LOW_REG(a), GET_LOW_REG(b)); \
+ } else { \
+ M_INTMOVE(GET_LOW_REG(a), GET_LOW_REG(b)); \
+ M_INTMOVE(GET_HIGH_REG(a), GET_HIGH_REG(b)); \
+ } \
+ } while (0)
+
+
+/* M_FLTMOVE:
+ generates a floating-point-move from register a to b.
+ if a and b are the same float-register, no code will be generated
+*/
+
+#define M_FLTMOVE(reg,dreg) \
+ do { \
+ if ((reg) != (dreg)) { \
+ log_text("M_FLTMOVE"); \
+ assert(0); \
+ } \
} while (0)
-#define i386_emit_mem(r,mem) \
+#define ICONST(d,c) \
do { \
- i386_address_byte(0,(r),5); \
- i386_emit_imm32((mem)); \
+ if ((c) == 0) \
+ M_CLR(d); \
+ else \
+ M_MOV_IMM((c), d); \
} while (0)
-#define i386_emit_membase(basereg,disp,dreg) \
+#define LCONST(d,c) \
do { \
- if ((basereg) == ESP) { \
- if ((disp) == 0) { \
- i386_address_byte(0, (dreg), ESP); \
- i386_address_byte(0, ESP, ESP); \
- } else if (i386_is_imm8((disp))) { \
- i386_address_byte(1, (dreg), ESP); \
- i386_address_byte(0, ESP, ESP); \
- i386_emit_imm8((disp)); \
- } else { \
- i386_address_byte(2, (dreg), ESP); \
- i386_address_byte(0, ESP, ESP); \
- i386_emit_imm32((disp)); \
- } \
- break; \
- } \
- \
- if ((disp) == 0 && (basereg) != EBP) { \
- i386_address_byte(0, (dreg), (basereg)); \
- break; \
- } \
- \
- if (i386_is_imm8((disp))) { \
- i386_address_byte(1, (dreg), (basereg)); \
- i386_emit_imm8((disp)); \
+ if ((c) == 0) { \
+ M_CLR(GET_LOW_REG(d)); \
+ M_CLR(GET_HIGH_REG(d)); \
} else { \
- i386_address_byte(2, (dreg), (basereg)); \
- i386_emit_imm32((disp)); \
+ M_MOV_IMM((c), GET_LOW_REG(d)); \
+ M_MOV_IMM((c) >> 32, GET_HIGH_REG(d)); \
} \
} while (0)
-#define i386_emit_memindex(reg,disp,basereg,indexreg,scale) \
+/* branch defines *************************************************************/
+
+#define BRANCH_UNCONDITIONAL_SIZE 5 /* size in bytes of a branch */
+#define BRANCH_CONDITIONAL_SIZE 6 /* size in bytes of a branch */
+
+#define BRANCH_NOPS \
do { \
- if ((basereg) == -1) { \
- i386_address_byte(0, (reg), 4); \
- i386_address_byte((scale), (indexreg), 5); \
- i386_emit_imm32((disp)); \
- \
- } else if ((disp) == 0 && (basereg) != EBP) { \
- i386_address_byte(0, (reg), 4); \
- i386_address_byte((scale), (indexreg), (basereg)); \
- \
- } else if (i386_is_imm8((disp))) { \
- i386_address_byte(1, (reg), 4); \
- i386_address_byte((scale), (indexreg), (basereg)); \
- i386_emit_imm8 ((disp)); \
- \
- } else { \
- i386_address_byte(2, (reg), 4); \
- i386_address_byte((scale), (indexreg), (basereg)); \
- i386_emit_imm32((disp)); \
- } \
- } while (0)
-
-
-/* code generation prototypes */
-
-void i386_emit_ialu(s4 alu_op, stackptr src, instruction *iptr);
-void i386_emit_ialuconst(s4 alu_op, stackptr src, instruction *iptr);
-void i386_emit_lalu(s4 alu_op, stackptr src, instruction *iptr);
-void i386_emit_laluconst(s4 alu_op, stackptr src, instruction *iptr);
-void i386_emit_ishift(s4 shift_op, stackptr src, instruction *iptr);
-void i386_emit_ishiftconst(s4 shift_op, stackptr src, instruction *iptr);
-void i386_emit_ifcc_iconst(s4 if_op, stackptr src, instruction *iptr);
-
-
-/* integer instructions */
-
-void i386_mov_reg_reg(s4 reg, s4 dreg);
-void i386_mov_imm_reg(s4 imm, s4 dreg);
-void i386_movb_imm_reg(s4 imm, s4 dreg);
-void i386_mov_membase_reg(s4 basereg, s4 disp, s4 reg);
-void i386_mov_membase32_reg(s4 basereg, s4 disp, s4 reg);
-void i386_mov_reg_membase(s4 reg, s4 basereg, s4 disp);
-void i386_mov_memindex_reg(s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg);
-void i386_mov_reg_memindex(s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_mov_mem_reg(s4 mem, s4 dreg);
-void i386_movw_reg_memindex(s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_movb_reg_memindex(s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_mov_imm_membase(s4 imm, s4 basereg, s4 disp);
-void i386_movsbl_memindex_reg(s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg);
-void i386_movswl_memindex_reg(s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg);
-void i386_movzwl_memindex_reg(s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg);
-void i386_alu_reg_reg(s4 opc, s4 reg, s4 dreg);
-void i386_alu_reg_membase(s4 opc, s4 reg, s4 basereg, s4 disp);
-void i386_alu_membase_reg(s4 opc, s4 basereg, s4 disp, s4 reg);
-void i386_alu_imm_reg(s4 opc, s4 imm, s4 reg);
-void i386_alu_imm_membase(s4 opc, s4 imm, s4 basereg, s4 disp);
-void i386_test_reg_reg(s4 reg, s4 dreg);
-void i386_test_imm_reg(s4 imm, s4 dreg);
-void i386_inc_reg(s4 reg);
-void i386_inc_membase(s4 basereg, s4 disp);
-void i386_dec_reg(s4 reg);
-void i386_dec_membase(s4 basereg, s4 disp);
-void i386_dec_mem(s4 mem);
-void i386_cltd();
-void i386_imul_reg_reg(s4 reg, s4 dreg);
-void i386_imul_membase_reg(s4 basereg, s4 disp, s4 dreg);
-void i386_imul_imm_reg(s4 imm, s4 reg);
-void i386_imul_imm_reg_reg(s4 imm, s4 reg, s4 dreg);
-void i386_imul_imm_membase_reg(s4 imm, s4 basereg, s4 disp, s4 dreg);
-void i386_mul_membase(s4 basereg, s4 disp);
-void i386_idiv_reg(s4 reg);
-void i386_ret();
-void i386_shift_reg(s4 opc, s4 reg);
-void i386_shift_membase(s4 opc, s4 basereg, s4 disp);
-void i386_shift_imm_reg(s4 opc, s4 imm, s4 reg);
-void i386_shift_imm_membase(s4 opc, s4 imm, s4 basereg, s4 disp);
-void i386_shld_reg_reg(s4 reg, s4 dreg);
-void i386_shld_imm_reg_reg(s4 imm, s4 reg, s4 dreg);
-void i386_shld_reg_membase(s4 reg, s4 basereg, s4 disp);
-void i386_shrd_reg_reg(s4 reg, s4 dreg);
-void i386_shrd_imm_reg_reg(s4 imm, s4 reg, s4 dreg);
-void i386_shrd_reg_membase(s4 reg, s4 basereg, s4 disp);
-void i386_jmp_imm(s4 imm);
-void i386_jmp_reg(s4 reg);
-void i386_jcc(s4 opc, s4 imm);
-void i386_setcc_reg(s4 opc, s4 reg);
-void i386_setcc_membase(s4 opc, s4 basereg, s4 disp);
-void i386_xadd_reg_mem(s4 reg, s4 mem);
-void i386_neg_reg(s4 reg);
-void i386_neg_membase(s4 basereg, s4 disp);
-void i386_push_imm(s4 imm);
-void i386_pop_reg(s4 reg);
-void i386_push_reg(s4 reg);
-void i386_nop();
-void i386_lock();
-void i386_call_reg(s4 reg);
-void i386_call_imm(s4 imm);
-void i386_call_mem(s4 mem);
-
-
-/* floating point instructions */
-
-void i386_fld1();
-void i386_fldz();
-void i386_fld_reg(s4 reg);
-void i386_flds_membase(s4 basereg, s4 disp);
-void i386_fldl_membase(s4 basereg, s4 disp);
-void i386_fldt_membase(s4 basereg, s4 disp);
-void i386_flds_memindex(s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_fldl_memindex(s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_fildl_membase(s4 basereg, s4 disp);
-void i386_fildll_membase(s4 basereg, s4 disp);
-void i386_fst_reg(s4 reg);
-void i386_fsts_membase(s4 basereg, s4 disp);
-void i386_fstl_membase(s4 basereg, s4 disp);
-void i386_fsts_memindex(s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_fstl_memindex(s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_fstp_reg(s4 reg);
-void i386_fstps_membase(s4 basereg, s4 disp);
-void i386_fstpl_membase(s4 basereg, s4 disp);
-void i386_fstpt_membase(s4 basereg, s4 disp);
-void i386_fstps_memindex(s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_fstpl_memindex(s4 disp, s4 basereg, s4 indexreg, s4 scale);
-void i386_fistl_membase(s4 basereg, s4 disp);
-void i386_fistpl_membase(s4 basereg, s4 disp);
-void i386_fistpll_membase(s4 basereg, s4 disp);
-void i386_fchs();
-void i386_faddp();
-void i386_fadd_reg_st(s4 reg);
-void i386_fadd_st_reg(s4 reg);
-void i386_faddp_st_reg(s4 reg);
-void i386_fadds_membase(s4 basereg, s4 disp);
-void i386_faddl_membase(s4 basereg, s4 disp);
-void i386_fsub_reg_st(s4 reg);
-void i386_fsub_st_reg(s4 reg);
-void i386_fsubp_st_reg(s4 reg);
-void i386_fsubp();
-void i386_fsubs_membase(s4 basereg, s4 disp);
-void i386_fsubl_membase(s4 basereg, s4 disp);
-void i386_fmul_reg_st(s4 reg);
-void i386_fmul_st_reg(s4 reg);
-void i386_fmulp();
-void i386_fmulp_st_reg(s4 reg);
-void i386_fmuls_membase(s4 basereg, s4 disp);
-void i386_fmull_membase(s4 basereg, s4 disp);
-void i386_fdiv_reg_st(s4 reg);
-void i386_fdiv_st_reg(s4 reg);
-void i386_fdivp();
-void i386_fdivp_st_reg(s4 reg);
-void i386_fxch();
-void i386_fxch_reg(s4 reg);
-void i386_fprem();
-void i386_fprem1();
-void i386_fucom();
-void i386_fucom_reg(s4 reg);
-void i386_fucomp_reg(s4 reg);
-void i386_fucompp();
-void i386_fnstsw();
-void i386_sahf();
-void i386_finit();
-void i386_fldcw_mem(s4 mem);
-void i386_fldcw_membase(s4 basereg, s4 disp);
-void i386_wait();
-void i386_ffree_reg(s4 reg);
-void i386_fdecstp();
-void i386_fincstp();
-
-
-/* function gen_resolvebranch **************************************************
-
- backpatches a branch instruction
-
- parameters: ip ... pointer to instruction after branch (void*)
- so ... offset of instruction after branch (s4)
- to ... offset of branch target (s4)
-
-*******************************************************************************/
-
-#define gen_resolvebranch(ip,so,to) \
- *((void **) ((ip) - 4)) = (void **) ((to) - (so));
-
-
-/* function prototypes */
-
-void codegen_init();
-void init_exceptions();
-void codegen();
-void codegen_close();
-void dseg_display(s4 *s4ptr);
+ M_NOP; \
+ M_NOP; \
+ M_NOP; \
+ M_NOP; \
+ M_NOP; \
+ M_NOP; \
+ } while (0)
+
+
+/* patcher defines ************************************************************/
+
+#define PATCHER_CALL_SIZE 2 /* size in bytes of a patcher call */
+
+#define PATCHER_NOPS \
+ do { \
+ M_NOP; \
+ M_NOP; \
+ } while (0)
+
+
+/* macros to create code ******************************************************/
+
+#define M_BYTE1(a) \
+ do { \
+ *(cd->mcodeptr) = (a); \
+ cd->mcodeptr++; \
+ } while (0)
+
+
+#define M_BYTE2(a, b) \
+ do { \
+ M_BYTE1(a); \
+ M_BYTE1(b); \
+ } while (0)
+
+
+#define M_ILD(a,b,disp) emit_mov_membase_reg(cd, (b), (disp), (a))
+#define M_ILD32(a,b,disp) emit_mov_membase32_reg(cd, (b), (disp), (a))
+
+#define M_ALD(a,b,disp) M_ILD(a,b,disp)
+#define M_ALD32(a,b,disp) M_ILD32(a,b,disp)
+
+#define M_ALD_MEM(a,disp) emit_mov_mem_reg(cd, (disp), (a))
+
+#define M_ALD_MEM_GET_OPC(p) (*(p))
+#define M_ALD_MEM_GET_MOD(p) (((*(p + 1)) >> 6) & 0x03)
+#define M_ALD_MEM_GET_REG(p) (((*(p + 1)) >> 3) & 0x07)
+#define M_ALD_MEM_GET_RM(p) (((*(p + 1)) ) & 0x07)
+#define M_ALD_MEM_GET_DISP(p) (*((u4 *) (p + 2)))
+
+#define M_LLD(a,b,disp) \
+ do { \
+ M_ILD(GET_LOW_REG(a),b,disp); \
+ M_ILD(GET_HIGH_REG(a),b,disp + 4); \
+ } while (0)
+
+#define M_LLD32(a,b,disp) \
+ do { \
+ M_ILD32(GET_LOW_REG(a),b,disp); \
+ M_ILD32(GET_HIGH_REG(a),b,disp + 4); \
+ } while (0)
+
+#define M_IST(a,b,disp) emit_mov_reg_membase(cd, (a), (b), (disp))
+#define M_IST_IMM(a,b,disp) emit_mov_imm_membase(cd, (u4) (a), (b), (disp))
+#define M_AST(a,b,disp) M_IST(a,b,disp)
+#define M_AST_IMM(a,b,disp) M_IST_IMM(a,b,disp)
+
+#define M_IST32(a,b,disp) emit_mov_reg_membase32(cd, (a), (b), (disp))
+#define M_IST32_IMM(a,b,disp) emit_mov_imm_membase32(cd, (u4) (a), (b), (disp))
+
+#define M_LST(a,b,disp) \
+ do { \
+ M_IST(GET_LOW_REG(a),b,disp); \
+ M_IST(GET_HIGH_REG(a),b,disp + 4); \
+ } while (0)
+
+#define M_LST32(a,b,disp) \
+ do { \
+ M_IST32(GET_LOW_REG(a),b,disp); \
+ M_IST32(GET_HIGH_REG(a),b,disp + 4); \
+ } while (0)
+
+#define M_LST_IMM(a,b,disp) \
+ do { \
+ M_IST_IMM(a,b,disp); \
+ M_IST_IMM(a >> 32,b,disp + 4); \
+ } while (0)
+
+#define M_LST32_IMM(a,b,disp) \
+ do { \
+ M_IST32_IMM(a,b,disp); \
+ M_IST32_IMM(a >> 32,b,disp + 4); \
+ } while (0)
+
+#define M_IADD(a,b) emit_alu_reg_reg(cd, ALU_ADD, (a), (b))
+#define M_ISUB(a,b) emit_alu_reg_reg(cd, ALU_SUB, (a), (b))
+#define M_IMUL(a,b) emit_imul_reg_reg(cd, (a), (b))
+#define M_IDIV(a) emit_idiv_reg(cd, (a))
+
+#define M_MUL(a) emit_mul_reg(cd, (a))
+
+#define M_IADD_IMM(a,b) emit_alu_imm_reg(cd, ALU_ADD, (a), (b))
+#define M_ISUB_IMM(a,b) emit_alu_imm_reg(cd, ALU_SUB, (a), (b))
+#define M_IMUL_IMM(a,b,c) emit_imul_imm_reg_reg(cd, (b), (a), (c))
+
+#define M_IADD_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_ADD, (a), (b))
+#define M_ISUB_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_SUB, (a), (b))
+
+#define M_IADD_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_ADD, (a), (b), (c))
+
+#define M_ISUB_IMM_MEMABS(a,b) emit_alu_imm_memabs(cd, ALU_SUB, (a), (b))
+
+#define M_IINC(a) emit_inc_reg(cd, (a))
+
+#define M_IADDC(a,b) emit_alu_reg_reg(cd, ALU_ADC, (a), (b))
+#define M_ISUBB(a,b) emit_alu_reg_reg(cd, ALU_SBB, (a), (b))
+
+#define M_IADDC_IMM(a,b) emit_alu_imm_reg(cd, ALU_ADC, (a), (b))
+#define M_ISUBB_IMM(a,b) emit_alu_imm_reg(cd, ALU_SBB, (a), (b))
+
+#define M_AADD_IMM(a,b) M_IADD_IMM(a,b)
+#define M_AADD_IMM32(a,b) M_IADD_IMM32(a,b)
+#define M_ASUB_IMM(a,b) M_ISUB_IMM(a,b)
+
+#define M_NEG(a) emit_neg_reg(cd, (a))
+
+#define M_AND(a,b) emit_alu_reg_reg(cd, ALU_AND, (a), (b))
+#define M_OR(a,b) emit_alu_reg_reg(cd, ALU_OR, (a), (b))
+#define M_XOR(a,b) emit_alu_reg_reg(cd, ALU_XOR, (a), (b))
+
+#define M_AND_IMM(a,b) emit_alu_imm_reg(cd, ALU_AND, (a), (b))
+#define M_OR_IMM(a,b) emit_alu_imm_reg(cd, ALU_OR, (a), (b))
+#define M_XOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_XOR, (a), (b))
+
+#define M_AND_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_AND, (a), (b))
+
+#define M_CLR(a) M_XOR(a,a)
+
+#define M_PUSH(a) emit_push_reg(cd, (a))
+#define M_PUSH_IMM(a) emit_push_imm(cd, (s4) (a))
+#define M_POP(a) emit_pop_reg(cd, (a))
+
+#define M_MOV(a,b) emit_mov_reg_reg(cd, (a), (b))
+#define M_MOV_IMM(a,b) emit_mov_imm_reg(cd, (u4) (a), (b))
+
+#define M_TEST(a) emit_test_reg_reg(cd, (a), (a))
+#define M_TEST_IMM(a,b) emit_test_imm_reg(cd, (a), (b))
+
+#define M_CMP(a,b) emit_alu_reg_reg(cd, ALU_CMP, (a), (b))
+#define M_CMP_MEMBASE(a,b,c) emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c))
+#define M_CMP_MEMINDEX(a,b,c,d,e) emit_alu_memindex_reg(cd, ALU_CMP, (b), (a), (c), (d), (e))
+
+#define M_CMP_IMM(a,b) emit_alu_imm_reg(cd, ALU_CMP, (a), (b))
+#define M_CMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c))
+
+#define M_CMP_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_CMP, (a), (b))
+
+#define M_BSEXT(a,b) emit_movsbl_reg_reg(cd, (a), (b))
+#define M_SSEXT(a,b) emit_movswl_reg_reg(cd, (a), (b))
+
+#define M_BZEXT(a,b) emit_movzbl_reg_reg(cd, (a), (b))
+#define M_CZEXT(a,b) emit_movzwl_reg_reg(cd, (a), (b))
+
+#define M_CLTD M_BYTE1(0x99)
+
+#define M_SLL(a) emit_shift_reg(cd, SHIFT_SHL, (a))
+#define M_SRA(a) emit_shift_reg(cd, SHIFT_SAR, (a))
+#define M_SRL(a) emit_shift_reg(cd, SHIFT_SHR, (a))
+
+#define M_SLL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHL, (a), (b))
+#define M_SRA_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SAR, (a), (b))
+#define M_SRL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHR, (a), (b))
+
+#define M_SLLD(a,b) emit_shld_reg_reg(cd, (a), (b))
+#define M_SRLD(a,b) emit_shrd_reg_reg(cd, (a), (b))
+
+#define M_SLLD_IMM(a,b,c) emit_shld_imm_reg_reg(cd, (a), (b), (c))
+#define M_SRLD_IMM(a,b,c) emit_shrd_imm_reg_reg(cd, (a), (b), (c))
+
+#define M_CALL(a) emit_call_reg(cd, (a))
+#define M_CALL_IMM(a) emit_call_imm(cd, (a))
+#define M_RET M_BYTE1(0xc3)
+
+#define M_ICMP_IMM(a,b) emit_alu_imm_reg(cd, ALU_CMP, (a), (b))
+
+#define M_BEQ(a) emit_jcc(cd, CC_E, (a))
+#define M_BNE(a) emit_jcc(cd, CC_NE, (a))
+#define M_BLT(a) emit_jcc(cd, CC_L, (a))
+#define M_BLE(a) emit_jcc(cd, CC_LE, (a))
+#define M_BGE(a) emit_jcc(cd, CC_GE, (a))
+#define M_BGT(a) emit_jcc(cd, CC_G, (a))
+
+#define M_BB(a) emit_jcc(cd, CC_B, (a))
+#define M_BBE(a) emit_jcc(cd, CC_BE, (a))
+#define M_BAE(a) emit_jcc(cd, CC_AE, (a))
+#define M_BA(a) emit_jcc(cd, CC_A, (a))
+#define M_BNS(a) emit_jcc(cd, CC_NS, (a))
+#define M_BS(a) emit_jcc(cd, CC_S, (a))
+
+#define M_SETE(a) emit_setcc_reg(cd, CC_E, (a))
+
+#define M_JMP(a) emit_jmp_reg(cd, (a))
+#define M_JMP_IMM(a) emit_jmp_imm(cd, (a))
+
+#define M_NOP M_BYTE1(0x90)
+#define M_UD2 M_BYTE2(0x0f, 0x0b)
+
+
+#define M_FLD(a,b,disp) emit_flds_membase(cd, (b), (disp))
+#define M_DLD(a,b,disp) emit_fldl_membase(cd, (b), (disp))
+
+#define M_FLD32(a,b,disp) emit_flds_membase32(cd, (b), (disp))
+#define M_DLD32(a,b,disp) emit_fldl_membase32(cd, (b), (disp))
+
+#define M_FST(a,b,disp) emit_fstps_membase(cd, (b), (disp))
+#define M_DST(a,b,disp) emit_fstpl_membase(cd, (b), (disp))
+
+#define M_FSTNP(a,b,disp) emit_fsts_membase(cd, (b), (disp))
+#define M_DSTNP(a,b,disp) emit_fstl_membase(cd, (b), (disp))
#endif /* _CODEGEN_H */
projects / cacao.git / blobdiff