Authors: Andreas Krall
Christian Thalinger
-
- Changes: Joseph Wenninger
+ Joseph Wenninger
Christian Ullrich
- Edwin Steiner
+ Edwin Steiner
- $Id: codegen.c 4606 2006-03-15 04:43:25Z edwin $
+ $Id: codegen.c 6264 2007-01-02 19:40:18Z edwin $
*/
#include "vm/jit/i386/md-abi.h"
#include "vm/jit/i386/codegen.h"
-#include "vm/jit/i386/emitfuncs.h"
+#include "vm/jit/i386/emit.h"
#include "mm/memory.h"
#include "native/jni.h"
#include "native/native.h"
+
+#if defined(ENABLE_THREADS)
+# include "threads/native/lock.h"
+#endif
+
#include "vm/builtin.h"
#include "vm/exceptions.h"
#include "vm/global.h"
#include "vm/jit/asmpart.h"
#include "vm/jit/codegen-common.h"
#include "vm/jit/dseg.h"
+#include "vm/jit/emit-common.h"
#include "vm/jit/jit.h"
#include "vm/jit/parse.h"
#include "vm/jit/patcher.h"
#include "vm/jit/reg.h"
#include "vm/jit/replace.h"
-#if defined(ENABLE_LSRA)
-# ifdef LSRA_USES_REG_RES
-# include "vm/jit/i386/icmd_uses_reg_res.inc"
-# endif
+#if defined(ENABLE_SSA)
+# include "vm/jit/optimizing/lsra.h"
+# include "vm/jit/optimizing/ssa.h"
+#elif defined(ENABLE_LSRA)
# include "vm/jit/allocator/lsra.h"
#endif
*******************************************************************************/
-bool codegen(methodinfo *m, codegendata *cd, registerdata *rd)
+#if defined(ENABLE_SSA)
+void cg_move(codegendata *cd, s4 type, s4 src_regoff, s4 src_flags,
+ s4 dst_regoff, s4 dst_flags);
+void codegen_insert_phi_moves(jitdata *jd, basicblock *bptr);
+#endif
+
+bool codegen(jitdata *jd)
{
- s4 len, s1, s2, s3, d, off, disp;
- s4 parentargs_base;
- stackptr src;
- varinfo *var;
+ methodinfo *m;
+ codeinfo *code;
+ codegendata *cd;
+ registerdata *rd;
+ s4 len, s1, s2, s3, d, disp;
+ varinfo *var, *var1;
basicblock *bptr;
instruction *iptr;
- exceptiontable *ex;
+ exception_entry *ex;
u2 currentline;
methodinfo *lm; /* local methodinfo for ICMD_INVOKE* */
builtintable_entry *bte;
methoddesc *md;
- s4 fpu_st_offset = 0;
- rplpoint *replacementpoint;
+ s4 fieldtype;
+ s4 varindex;
+#if defined(ENABLE_SSA)
+ lsradata *ls;
+ bool last_cmd_was_goto;
+
+ last_cmd_was_goto = false;
+ ls = jd->ls;
+#endif
+
+ /* get required compiler data */
+
+ m = jd->m;
+ code = jd->code;
+ cd = jd->cd;
+ rd = jd->rd;
/* prevent compiler warnings */
/* float register are saved on 2 4-byte stackslots */
savedregs_num += (FLT_SAV_CNT - rd->savfltreguse) * 2;
- parentargs_base = rd->memuse + savedregs_num;
+ cd->stackframesize = rd->memuse + savedregs_num;
-#if defined(USE_THREADS)
+#if defined(ENABLE_THREADS)
/* space to save argument of monitor_enter */
if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
/* reserve 2 slots for long/double return values for monitorexit */
if (IS_2_WORD_TYPE(m->parseddesc->returntype.type))
- parentargs_base += 2;
+ cd->stackframesize += 2;
else
- parentargs_base++;
+ cd->stackframesize++;
}
#endif
-/* create method header */
+ /* create method header */
+
+ /* Keep stack of non-leaf functions 16-byte aligned. */
+
+ if (!jd->isleafmethod)
+ cd->stackframesize |= 0x3;
- (void) dseg_addaddress(cd, m); /* MethodPointer */
- (void) dseg_adds4(cd, parentargs_base * 4); /* FrameSize */
+ (void) dseg_add_unique_address(cd, code); /* CodeinfoPointer */
+ (void) dseg_add_unique_s4(cd, cd->stackframesize * 4); /* FrameSize */
-#if defined(USE_THREADS)
+#if defined(ENABLE_THREADS)
/* IsSync contains the offset relative to the stack pointer for the
argument of monitor_exit used in the exception handler. Since the
offset could be zero and give a wrong meaning of the flag it is
*/
if (checksync && (m->flags & ACC_SYNCHRONIZED))
- (void) dseg_adds4(cd, (rd->memuse + 1) * 4); /* IsSync */
+ (void) dseg_add_unique_s4(cd, (rd->memuse + 1) * 4); /* IsSync */
else
#endif
- (void) dseg_adds4(cd, 0); /* IsSync */
+ (void) dseg_add_unique_s4(cd, 0); /* IsSync */
- (void) dseg_adds4(cd, m->isleafmethod); /* IsLeaf */
- (void) dseg_adds4(cd, INT_SAV_CNT - rd->savintreguse); /* IntSave */
- (void) dseg_adds4(cd, FLT_SAV_CNT - rd->savfltreguse); /* FltSave */
+ (void) dseg_add_unique_s4(cd, jd->isleafmethod); /* IsLeaf */
+ (void) dseg_add_unique_s4(cd, INT_SAV_CNT - rd->savintreguse); /* IntSave */
+ (void) dseg_add_unique_s4(cd, FLT_SAV_CNT - rd->savfltreguse); /* FltSave */
/* adds a reference for the length of the line number counter. We don't
know the size yet, since we evaluate the information during code
to the information gotten from the class file */
(void) dseg_addlinenumbertablesize(cd);
- (void) dseg_adds4(cd, cd->exceptiontablelength); /* ExTableSize */
+ (void) dseg_add_unique_s4(cd, jd->exceptiontablelength); /* ExTableSize */
/* create exception table */
- for (ex = cd->exceptiontable; ex != NULL; ex = ex->down) {
- dseg_addtarget(cd, ex->start);
- dseg_addtarget(cd, ex->end);
- dseg_addtarget(cd, ex->handler);
- (void) dseg_addaddress(cd, ex->catchtype.cls);
+ for (ex = jd->exceptiontable; ex != NULL; ex = ex->down) {
+ dseg_add_target(cd, ex->start);
+ dseg_add_target(cd, ex->end);
+ dseg_add_target(cd, ex->handler);
+ (void) dseg_add_unique_address(cd, ex->catchtype.any);
}
- /* initialize mcode variables */
-
- cd->mcodeptr = cd->mcodebase;
- cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize);
-
- /* initialize the last patcher pointer */
-
- cd->lastmcodeptr = cd->mcodeptr;
-
/* generate method profiling code */
- if (opt_prof) {
+ if (JITDATA_HAS_FLAG_INSTRUMENT(jd)) {
/* count frequency */
- M_MOV_IMM((ptrint) m, REG_ITMP1);
- M_IADD_IMM_MEMBASE(1, REG_ITMP1, OFFSET(methodinfo, frequency));
+ M_MOV_IMM(code, REG_ITMP3);
+ M_IADD_IMM_MEMBASE(1, REG_ITMP3, OFFSET(codeinfo, frequency));
}
/* create stack frame (if necessary) */
- if (parentargs_base)
- M_ASUB_IMM(parentargs_base * 4, REG_SP);
+ if (cd->stackframesize)
+ M_ASUB_IMM(cd->stackframesize * 4, REG_SP);
/* save return address and used callee saved registers */
- p = parentargs_base;
+ p = cd->stackframesize;
for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
p--; M_AST(rd->savintregs[i], REG_SP, p * 4);
}
for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
- p-=2; i386_fld_reg(cd, rd->savfltregs[i]); i386_fstpl_membase(cd, REG_SP, p * 4);
+ p-=2; emit_fld_reg(cd, rd->savfltregs[i]); emit_fstpl_membase(cd, REG_SP, p * 4);
}
/* take arguments out of register or stack frame */
stack_off = 0;
for (p = 0, l = 0; p < md->paramcount; p++) {
t = md->paramtypes[p].type;
- var = &(rd->locals[l][t]);
+
+#if defined(ENABLE_SSA)
+ if ( ls != NULL ) {
+ l = ls->local_0[p];
+ }
+#endif
+ varindex = jd->local_map[l * 5 + t];
l++;
if (IS_2_WORD_TYPE(t)) /* increment local counter for 2 word types */
l++;
- if (var->type < 0)
+
+ if (varindex == UNUSED)
continue;
+
+ var = VAR(varindex);
+
s1 = md->params[p].regoff;
+
if (IS_INT_LNG_TYPE(t)) { /* integer args */
if (!md->params[p].inmemory) { /* register arguments */
log_text("integer register argument");
assert(0);
if (!(var->flags & INMEMORY)) { /* reg arg -> register */
- /* rd->argintregs[md->params[p].regoff -> var->regoff */
- } else { /* reg arg -> spilled */
- /* rd->argintregs[md->params[p].regoff -> var->regoff * 4 */
+ /* rd->argintregs[md->params[p].regoff -> var->vv.regoff */
+ }
+ else { /* reg arg -> spilled */
+ /* rd->argintregs[md->params[p].regoff -> var->vv.regoff * 4 */
}
- } else { /* stack arguments */
+ }
+ else { /* stack arguments */
if (!(var->flags & INMEMORY)) { /* stack arg -> register */
- i386_mov_membase_reg( /* + 4 for return address */
- cd, REG_SP, (parentargs_base + s1) * 4 + 4, var->regoff);
+ emit_mov_membase_reg( /* + 4 for return address */
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4, var->vv.regoff);
/* + 4 for return address */
- } else { /* stack arg -> spilled */
+ }
+ else { /* stack arg -> spilled */
if (!IS_2_WORD_TYPE(t)) {
-#if 0
- i386_mov_membase_reg( /* + 4 for return address */
- cd, REG_SP, (parentargs_base + s1) * 4 + 4,
- REG_ITMP1);
- i386_mov_reg_membase(
- cd, REG_ITMP1, REG_SP, var->regoff * 4);
-#else
+#if defined(ENABLE_SSA)
+ /* no copy avoiding by now possible with SSA */
+ if (ls != NULL) {
+ emit_mov_membase_reg( /* + 4 for return address */
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4,
+ REG_ITMP1);
+ emit_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP, var->vv.regoff * 4);
+ }
+ else
+#endif /*defined(ENABLE_SSA)*/
/* reuse Stackslotand avoid copying */
- var->regoff = parentargs_base + s1 + 1;
-#endif
-
- } else {
-#if 0
- i386_mov_membase_reg( /* + 4 for return address */
- cd, REG_SP, (parentargs_base + s1) * 4 + 4,
- REG_ITMP1);
- i386_mov_reg_membase(
- cd, REG_ITMP1, REG_SP, var->regoff * 4);
- i386_mov_membase_reg( /* + 4 for return address */
- cd, REG_SP, (parentargs_base + s1) * 4 + 4 + 4,
- REG_ITMP1);
- i386_mov_reg_membase(
- cd, REG_ITMP1, REG_SP, var->regoff * 4 + 4);
-#else
+ var->vv.regoff = cd->stackframesize + s1 + 1;
+
+ }
+ else {
+#if defined(ENABLE_SSA)
+ /* no copy avoiding by now possible with SSA */
+ if (ls != NULL) {
+ emit_mov_membase_reg( /* + 4 for return address */
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4,
+ REG_ITMP1);
+ emit_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP, var->vv.regoff * 4);
+ emit_mov_membase_reg( /* + 4 for return address */
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4 + 4,
+ REG_ITMP1);
+ emit_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP, var->vv.regoff * 4 + 4);
+ }
+ else
+#endif /*defined(ENABLE_SSA)*/
/* reuse Stackslotand avoid copying */
- var->regoff = parentargs_base + s1 + 1;
-#endif
+ var->vv.regoff = cd->stackframesize + s1 + 1;
}
}
}
-
- } else { /* floating args */
+ }
+ else { /* floating args */
if (!md->params[p].inmemory) { /* register arguments */
log_text("There are no float argument registers!");
assert(0);
if (!(var->flags & INMEMORY)) { /* reg arg -> register */
- /* rd->argfltregs[md->params[p].regoff -> var->regoff */
+ /* rd->argfltregs[md->params[p].regoff -> var->vv.regoff */
} else { /* reg arg -> spilled */
- /* rd->argfltregs[md->params[p].regoff -> var->regoff * 4 */
+ /* rd->argfltregs[md->params[p].regoff -> var->vv.regoff * 4 */
}
- } else { /* stack arguments */
+ }
+ else { /* stack arguments */
if (!(var->flags & INMEMORY)) { /* stack-arg -> register */
if (t == TYPE_FLT) {
- i386_flds_membase(
- cd, REG_SP, (parentargs_base + s1) * 4 + 4);
- fpu_st_offset++;
- i386_fstp_reg(cd, var->regoff + fpu_st_offset);
- fpu_st_offset--;
+ emit_flds_membase(
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4);
+ assert(0);
+/* emit_fstp_reg(cd, var->vv.regoff + fpu_st_offset); */
- } else {
- i386_fldl_membase(
- cd, REG_SP, (parentargs_base + s1) * 4 + 4);
- fpu_st_offset++;
- i386_fstp_reg(cd, var->regoff + fpu_st_offset);
- fpu_st_offset--;
+ }
+ else {
+ emit_fldl_membase(
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4);
+ assert(0);
+/* emit_fstp_reg(cd, var->vv.regoff + fpu_st_offset); */
}
} else { /* stack-arg -> spilled */
-#if 0
- i386_mov_membase_reg(
- cd, REG_SP, (parentargs_base + s1) * 4 + 4, REG_ITMP1);
- i386_mov_reg_membase(
- cd, REG_ITMP1, REG_SP, var->regoff * 4);
- if (t == TYPE_FLT) {
- i386_flds_membase(
- cd, REG_SP, (parentargs_base + s1) * 4 + 4);
- i386_fstps_membase(cd, REG_SP, var->regoff * 4);
- } else {
- i386_fldl_membase(
- cd, REG_SP, (parentargs_base + s1) * 4 + 4);
- i386_fstpl_membase(cd, REG_SP, var->regoff * 4);
+#if defined(ENABLE_SSA)
+ /* no copy avoiding by now possible with SSA */
+ if (ls != NULL) {
+ emit_mov_membase_reg(
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4, REG_ITMP1);
+ emit_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP, var->vv.regoff * 4);
+ if (t == TYPE_FLT) {
+ emit_flds_membase(
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4);
+ emit_fstps_membase(cd, REG_SP, var->vv.regoff * 4);
+ }
+ else {
+ emit_fldl_membase(
+ cd, REG_SP, (cd->stackframesize + s1) * 4 + 4);
+ emit_fstpl_membase(cd, REG_SP, var->vv.regoff * 4);
+ }
}
-#else
+ else
+#endif /*defined(ENABLE_SSA)*/
/* reuse Stackslotand avoid copying */
- var->regoff = parentargs_base + s1 + 1;
-#endif
+ var->vv.regoff = cd->stackframesize + s1 + 1;
}
}
}
/* call monitorenter function */
-#if defined(USE_THREADS)
+#if defined(ENABLE_THREADS)
if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
s1 = rd->memuse;
if (m->flags & ACC_STATIC) {
- i386_mov_imm_reg(cd, (ptrint) m->class, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, s1 * 4);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 0);
- i386_mov_imm_reg(cd, (ptrint) BUILTIN_staticmonitorenter, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, parentargs_base * 4 + 4, REG_ITMP1);
- i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
- i386_jcc(cd, I386_CC_Z, 0);
- codegen_addxnullrefs(cd, cd->mcodeptr);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, s1 * 4);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 0);
- i386_mov_imm_reg(cd, (ptrint) BUILTIN_monitorenter, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
+ M_MOV_IMM(&m->class->object.header, REG_ITMP1);
}
- }
-#endif
-
- /* copy argument registers to stack and call trace function with pointer
- to arguments on stack.
- */
-
- if (opt_verbosecall) {
- stack_off = 0;
- s1 = INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4 + 4 + parentargs_base * 4;
-
- M_ISUB_IMM(INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4, REG_SP);
-
- /* save temporary registers for leaf methods */
-
- for (p = 0; p < INT_TMP_CNT; p++)
- M_IST(rd->tmpintregs[p], REG_SP, TRACE_ARGS_NUM * 8 + 4 + p * 4);
-
- for (p = 0, l = 0; p < md->paramcount && p < TRACE_ARGS_NUM; p++) {
- t = md->paramtypes[p].type;
-
- if (IS_INT_LNG_TYPE(t)) {
- if (IS_2_WORD_TYPE(t)) {
- i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
- i386_mov_membase_reg(cd, REG_SP, s1 + stack_off + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
-
- } else if (t == TYPE_ADR) {
-/* } else { */
- i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
- i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, EAX);
- i386_cltd(cd);
- i386_mov_reg_membase(cd, EAX, REG_SP, p * 8);
- i386_mov_reg_membase(cd, EDX, REG_SP, p * 8 + 4);
- }
-
- } else {
- if (!IS_2_WORD_TYPE(t)) {
- i386_flds_membase(cd, REG_SP, s1 + stack_off);
- i386_fstps_membase(cd, REG_SP, p * 8);
- i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
-
- } else {
- i386_fldl_membase(cd, REG_SP, s1 + stack_off);
- i386_fstpl_membase(cd, REG_SP, p * 8);
- }
- }
- stack_off += (IS_2_WORD_TYPE(t)) ? 8 : 4;
- }
-
- /* fill up the remaining arguments */
- i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
- for (p = md->paramcount; p < TRACE_ARGS_NUM; p++) {
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
+ else {
+ M_ALD(REG_ITMP1, REG_SP, cd->stackframesize * 4 + 4);
+ M_TEST(REG_ITMP1);
+ M_BEQ(0);
+ codegen_add_nullpointerexception_ref(cd);
}
- i386_mov_imm_membase(cd, (ptrint) m, REG_SP, TRACE_ARGS_NUM * 8);
- i386_mov_imm_reg(cd, (ptrint) builtin_trace_args, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
-
- /* restore temporary registers for leaf methods */
+ M_AST(REG_ITMP1, REG_SP, s1 * 4);
+ M_AST(REG_ITMP1, REG_SP, 0 * 4);
+ M_MOV_IMM(LOCK_monitor_enter, REG_ITMP3);
+ M_CALL(REG_ITMP3);
+ }
+#endif
- for (p = 0; p < INT_TMP_CNT; p++)
- M_ILD(rd->tmpintregs[p], REG_SP, TRACE_ARGS_NUM * 8 + 4 + p * 4);
+#if !defined(NDEBUG)
+ emit_verbosecall_enter(jd);
+#endif
- M_IADD_IMM(INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4, REG_SP);
- }
+ }
- }
+#if defined(ENABLE_SSA)
+ /* with SSA Header is Basic Block 0 - insert phi Moves if necessary */
+ if ( ls != NULL)
+ codegen_insert_phi_moves(jd, ls->basicblocks[0]);
+#endif
/* end of header generation */
- replacementpoint = cd->code->rplpoints;
+ /* create replacement points */
+
+ REPLACEMENT_POINTS_INIT(cd, jd);
/* walk through all basic blocks */
- for (bptr = m->basicblocks; bptr != NULL; bptr = bptr->next) {
+
+ for (bptr = jd->basicblocks; bptr != NULL; bptr = bptr->next) {
bptr->mpc = (s4) (cd->mcodeptr - cd->mcodebase);
if (bptr->flags >= BBREACHED) {
-
/* branch resolving */
- branchref *brefs;
- for (brefs = bptr->branchrefs; brefs != NULL; brefs = brefs->next) {
- gen_resolvebranch(cd->mcodebase + brefs->branchpos,
- brefs->branchpos,
- bptr->mpc);
- }
+ codegen_resolve_branchrefs(cd, bptr);
/* handle replacement points */
- if (bptr->bitflags & BBFLAG_REPLACEMENT) {
- replacementpoint->pc = (u1*)bptr->mpc; /* will be resolved later */
-
- replacementpoint++;
- }
+ REPLACEMENT_POINT_BLOCK_START(cd, bptr);
/* copy interface registers to their destination */
- src = bptr->instack;
len = bptr->indepth;
MCODECHECK(512);
+#if 0
/* generate basic block profiling code */
- if (opt_prof) {
+ if (JITDATA_HAS_FLAG_INSTRUMENT(jd)) {
/* count frequency */
- M_MOV_IMM((ptrint) m->bbfrequency, REG_ITMP1);
- M_IADD_IMM_MEMBASE(1, REG_ITMP1, bptr->debug_nr * 4);
+ M_MOV_IMM(code->bbfrequency, REG_ITMP3);
+ M_IADD_IMM_MEMBASE(1, REG_ITMP3, bptr->nr * 4);
}
+#endif
-
-#if defined(ENABLE_LSRA)
+#if defined(ENABLE_LSRA) || defined(ENABLE_SSA)
+# if defined(ENABLE_LSRA) && !defined(ENABLE_SSA)
if (opt_lsra) {
- while (src != NULL) {
+# endif
+# if defined(ENABLE_SSA)
+ if (ls != NULL) {
+ last_cmd_was_goto = false;
+# endif
+ if (len > 0) {
len--;
- if ((len == 0) && (bptr->type != BBTYPE_STD)) {
- if (!IS_2_WORD_TYPE(src->type)) {
- if (bptr->type == BBTYPE_SBR) {
- /* d = reg_of_var(m, src, REG_ITMP1); */
- if (!(src->flags & INMEMORY))
- d = src->regoff;
- else
- d = REG_ITMP1;
-
- i386_pop_reg(cd, d);
- store_reg_to_var_int(src, d);
-
- } else if (bptr->type == BBTYPE_EXH) {
- /* d = reg_of_var(m, src, REG_ITMP1); */
- if (!(src->flags & INMEMORY))
- d = src->regoff;
- else
- d = REG_ITMP1;
+ var = VAR(bptr->invars[len]);
+ if (bptr->type != BBTYPE_STD) {
+ if (!IS_2_WORD_TYPE(var->type)) {
+ if (bptr->type == BBTYPE_EXH) {
+ d = codegen_reg_of_var(0, var, REG_ITMP1);
M_INTMOVE(REG_ITMP1, d);
- store_reg_to_var_int(src, d);
+ emit_store(jd, NULL, var, d);
}
-
- } else {
- log_text("copy interface registers(EXH, SBR): longs have to be in memory (begin 1)");
+ }
+ else {
+ log_text("copy interface registers(EXH, SBR): longs \
+ have to be in memory (begin 1)");
assert(0);
}
}
- src = src->prev;
}
- } else {
-#endif
- while (src != NULL) {
- len--;
- if ((len == bptr->indepth-1) && (bptr->type != BBTYPE_STD)) {
- if (!IS_2_WORD_TYPE(src->type)) {
- if (bptr->type == BBTYPE_SBR) {
- d = reg_of_var(rd, src, REG_ITMP1);
- i386_pop_reg(cd, d);
- store_reg_to_var_int(src, d);
- } else if (bptr->type == BBTYPE_EXH) {
- d = reg_of_var(rd, src, REG_ITMP1);
+ }
+ else
+#endif /* defined(ENABLE_LSRA) || defined(ENABLE_SSA) */
+ {
+ while (len) {
+ len--;
+ var = VAR(bptr->invars[len]);
+ if ((len == bptr->indepth-1) && (bptr->type != BBTYPE_STD)) {
+ if (!IS_2_WORD_TYPE(var->type)) {
+ if (bptr->type == BBTYPE_EXH) {
+ d = codegen_reg_of_var(0, var, REG_ITMP1);
M_INTMOVE(REG_ITMP1, d);
- store_reg_to_var_int(src, d);
+ emit_store(jd, NULL, var, d);
}
-
- } else {
- log_text("copy interface registers: longs have to be in memory (begin 1)");
+ }
+ else {
+ log_text("copy interface registers: longs have to be in \
+ memory (begin 1)");
assert(0);
}
- } else {
- d = reg_of_var(rd, src, REG_ITMP1);
- if ((src->varkind != STACKVAR)) {
- s2 = src->type;
- if (IS_FLT_DBL_TYPE(s2)) {
- s1 = rd->interfaces[len][s2].regoff;
- if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
- M_FLTMOVE(s1, d);
-
- } else {
- if (s2 == TYPE_FLT) {
- i386_flds_membase(cd, REG_SP, s1 * 4);
-
- } else {
- i386_fldl_membase(cd, REG_SP, s1 * 4);
- }
- }
- store_reg_to_var_flt(src, d);
-
- } else {
- s1 = rd->interfaces[len][s2].regoff;
- if (!IS_2_WORD_TYPE(rd->interfaces[len][s2].type)) {
- if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
- M_INTMOVE(s1, d);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, s1 * 4, d);
- }
- store_reg_to_var_int(src, d);
-
- } else {
- if (rd->interfaces[len][s2].flags & INMEMORY) {
- M_LNGMEMMOVE(s1, src->regoff);
-
- } else {
- log_text("copy interface registers: longs have to be in memory (begin 2)");
- assert(0);
- }
- }
- }
- }
+ }
+ else {
+ assert((var->flags & INOUT));
}
- src = src->prev;
- }
-#if defined(ENABLE_LSRA)
- }
-#endif
+ } /* while (len) */
+ } /* */
/* walk through all instructions */
- src = bptr->instack;
len = bptr->icount;
currentline = 0;
- for (iptr = bptr->iinstr; len > 0; src = iptr->dst, len--, iptr++) {
+
+ for (iptr = bptr->iinstr; len > 0; len--, iptr++) {
if (iptr->line != currentline) {
- dseg_addlinenumber(cd, iptr->line, cd->mcodeptr);
+ dseg_addlinenumber(cd, iptr->line);
currentline = iptr->line;
}
MCODECHECK(1024); /* 1kB should be enough */
switch (iptr->opc) {
+ case ICMD_NOP: /* ... ==> ... */
+ case ICMD_POP: /* ..., value ==> ... */
+ case ICMD_POP2: /* ..., value, value ==> ... */
+ break;
+
case ICMD_INLINE_START:
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: NO ECX: NO EDX: NO */
- dseg_addlinenumber_inline_start(cd, iptr, cd->mcodeptr);
+
+ REPLACEMENT_POINT_INLINE_START(cd, iptr);
break;
- case ICMD_INLINE_END:
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: NO ECX: NO EDX: NO */
- dseg_addlinenumber_inline_end(cd, iptr);
- dseg_addlinenumber(cd, iptr->line, cd->mcodeptr);
+ case ICMD_INLINE_BODY:
+
+ REPLACEMENT_POINT_INLINE_BODY(cd, iptr);
+ dseg_addlinenumber_inline_start(cd, iptr);
+ dseg_addlinenumber(cd, iptr->line);
break;
- case ICMD_NOP: /* ... ==> ... */
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: NO ECX: NO EDX: NO */
+ case ICMD_INLINE_END:
+
+ dseg_addlinenumber_inline_end(cd, iptr);
+ dseg_addlinenumber(cd, iptr->line);
break;
case ICMD_CHECKNULL: /* ..., objectref ==> ..., objectref */
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: NO ECX: NO EDX: NO */
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4);
- } else {
- i386_test_reg_reg(cd, src->regoff, src->regoff);
- }
- i386_jcc(cd, I386_CC_Z, 0);
- codegen_addxnullrefs(cd, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ emit_nullpointer_check(cd, iptr, s1);
break;
/* constant operations ************************************************/
case ICMD_ICONST: /* ... ==> ..., constant */
- /* op1 = 0, val.i = constant */
-
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: NO ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if (iptr->dst->flags & INMEMORY) {
- M_IST_IMM(iptr->val.i, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- if (iptr->val.i == 0) {
- M_CLR(d);
- } else {
- M_MOV_IMM(iptr->val.i, d);
- }
- }
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ ICONST(d, iptr->sx.val.i);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LCONST: /* ... ==> ..., constant */
- /* op1 = 0, val.l = constant */
-
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: NO ECX: NO EDX: NO */
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if (iptr->dst->flags & INMEMORY) {
- M_IST_IMM(iptr->val.l, REG_SP, iptr->dst->regoff * 4);
- M_IST_IMM(iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4);
-
- } else {
- log_text("LCONST: longs have to be in memory");
- assert(0);
- }
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ LCONST(d, iptr->sx.val.l);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_FCONST: /* ... ==> ..., constant */
- /* op1 = 0, val.f = constant */
-
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: YES ECX: NO EDX: NO */
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- if (iptr->val.f == 0.0) {
- i386_fldz(cd);
- fpu_st_offset++;
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ if (iptr->sx.val.f == 0.0) {
+ emit_fldz(cd);
/* -0.0 */
- if (iptr->val.i == 0x80000000) {
- i386_fchs(cd);
+ if (iptr->sx.val.i == 0x80000000) {
+ emit_fchs(cd);
}
- } else if (iptr->val.f == 1.0) {
- i386_fld1(cd);
- fpu_st_offset++;
+ } else if (iptr->sx.val.f == 1.0) {
+ emit_fld1(cd);
- } else if (iptr->val.f == 2.0) {
- i386_fld1(cd);
- i386_fld1(cd);
- i386_faddp(cd);
- fpu_st_offset++;
+ } else if (iptr->sx.val.f == 2.0) {
+ emit_fld1(cd);
+ emit_fld1(cd);
+ emit_faddp(cd);
} else {
- disp = dseg_addfloat(cd, iptr->val.f);
- i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(cd, cd->mcodeptr);
- i386_flds_membase(cd, REG_ITMP1, disp);
- fpu_st_offset++;
+ disp = dseg_add_float(cd, iptr->sx.val.f);
+ emit_mov_imm_reg(cd, 0, REG_ITMP1);
+ dseg_adddata(cd);
+ emit_flds_membase(cd, REG_ITMP1, disp);
}
- store_reg_to_var_flt(iptr->dst, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_DCONST: /* ... ==> ..., constant */
- /* op1 = 0, val.d = constant */
-
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: YES ECX: NO EDX: NO */
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- if (iptr->val.d == 0.0) {
- i386_fldz(cd);
- fpu_st_offset++;
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ if (iptr->sx.val.d == 0.0) {
+ emit_fldz(cd);
/* -0.0 */
- if (iptr->val.l == 0x8000000000000000LL) {
- i386_fchs(cd);
+ if (iptr->sx.val.l == 0x8000000000000000LL) {
+ emit_fchs(cd);
}
- } else if (iptr->val.d == 1.0) {
- i386_fld1(cd);
- fpu_st_offset++;
+ } else if (iptr->sx.val.d == 1.0) {
+ emit_fld1(cd);
- } else if (iptr->val.d == 2.0) {
- i386_fld1(cd);
- i386_fld1(cd);
- i386_faddp(cd);
- fpu_st_offset++;
+ } else if (iptr->sx.val.d == 2.0) {
+ emit_fld1(cd);
+ emit_fld1(cd);
+ emit_faddp(cd);
} else {
- disp = dseg_adddouble(cd, iptr->val.d);
- i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(cd, cd->mcodeptr);
- i386_fldl_membase(cd, REG_ITMP1, disp);
- fpu_st_offset++;
+ disp = dseg_add_double(cd, iptr->sx.val.d);
+ emit_mov_imm_reg(cd, 0, REG_ITMP1);
+ dseg_adddata(cd);
+ emit_fldl_membase(cd, REG_ITMP1, disp);
}
- store_reg_to_var_flt(iptr->dst, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_ACONST: /* ... ==> ..., constant */
- /* op1 = 0, val.a = constant */
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: YES ECX: NO EDX: NO */
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
-
- if ((iptr->target != NULL) && (iptr->val.a == NULL)) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_aconst,
- (unresolved_class *) iptr->target, 0);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ codegen_addpatchref(cd, PATCHER_aconst,
+ iptr->sx.val.c.ref, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
- M_MOV_IMM((ptrint) iptr->val.a, d);
- store_reg_to_var_int(iptr->dst, d);
-
- } else {
- if (iptr->dst->flags & INMEMORY) {
- M_AST_IMM((ptrint) iptr->val.a, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- if ((ptrint) iptr->val.a == 0) {
- M_CLR(d);
- } else {
- M_MOV_IMM((ptrint) iptr->val.a, d);
- }
- }
- }
- break;
-
-
- /* load/store operations **********************************************/
-
- case ICMD_ILOAD: /* ... ==> ..., content of local variable */
- case ICMD_ALOAD: /* op1 = local variable */
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if ((iptr->dst->varkind == LOCALVAR) &&
- (iptr->dst->varnum == iptr->op1)) {
- break;
- }
- var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
- if (iptr->dst->flags & INMEMORY) {
- if (var->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, var->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- i386_mov_reg_membase(cd, var->regoff, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- if (var->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, var->regoff * 4, iptr->dst->regoff);
-
- } else {
- M_INTMOVE(var->regoff, iptr->dst->regoff);
- }
- }
- break;
-
- case ICMD_LLOAD: /* ... ==> ..., content of local variable */
- /* op1 = local variable */
- /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
- /* EAX: NO ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if ((iptr->dst->varkind == LOCALVAR) &&
- (iptr->dst->varnum == iptr->op1)) {
- break;
- }
- var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
- if (iptr->dst->flags & INMEMORY) {
- if (var->flags & INMEMORY) {
- M_LNGMEMMOVE(var->regoff, iptr->dst->regoff);
-
- } else {
- log_text("LLOAD: longs have to be in memory");
- assert(0);
- }
-
- } else {
- log_text("LLOAD: longs have to be in memory");
- assert(0);
- }
- break;
-
- case ICMD_FLOAD: /* ... ==> ..., content of local variable */
- /* op1 = local variable */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- if ((iptr->dst->varkind == LOCALVAR) &&
- (iptr->dst->varnum == iptr->op1)) {
- break;
- }
- var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
- if (var->flags & INMEMORY) {
- i386_flds_membase(cd, REG_SP, var->regoff * 4);
- fpu_st_offset++;
- } else {
- i386_fld_reg(cd, var->regoff + fpu_st_offset);
- fpu_st_offset++;
- }
- store_reg_to_var_flt(iptr->dst, d);
- break;
-
- case ICMD_DLOAD: /* ... ==> ..., content of local variable */
- /* op1 = local variable */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
+ M_MOV_IMM(NULL, d);
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- if ((iptr->dst->varkind == LOCALVAR) &&
- (iptr->dst->varnum == iptr->op1)) {
- break;
- }
- var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
- if (var->flags & INMEMORY) {
- i386_fldl_membase(cd, REG_SP, var->regoff * 4);
- fpu_st_offset++;
} else {
- i386_fld_reg(cd, var->regoff + fpu_st_offset);
- fpu_st_offset++;
- }
- store_reg_to_var_flt(iptr->dst, d);
- break;
-
- case ICMD_ISTORE: /* ..., value ==> ... */
- case ICMD_ASTORE: /* op1 = local variable */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- if ((src->varkind == LOCALVAR) &&
- (src->varnum == iptr->op1)) {
- break;
- }
- var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
- if (var->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, var->regoff * 4);
-
- } else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, var->regoff * 4);
- }
-
- } else {
- var_to_reg_int(s1, src, var->regoff);
- M_INTMOVE(s1, var->regoff);
- }
- break;
-
- case ICMD_LSTORE: /* ..., value ==> ... */
- /* op1 = local variable */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
-
- if ((src->varkind == LOCALVAR) &&
- (src->varnum == iptr->op1)) {
- break;
- }
- var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
- if (var->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- M_LNGMEMMOVE(src->regoff, var->regoff);
-
- } else {
- log_text("LSTORE: longs have to be in memory");
- assert(0);
- }
-
- } else {
- log_text("LSTORE: longs have to be in memory");
- assert(0);
- }
- break;
-
- case ICMD_FSTORE: /* ..., value ==> ... */
- /* op1 = local variable */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
-
- if ((src->varkind == LOCALVAR) &&
- (src->varnum == iptr->op1)) {
- break;
- }
- var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
- if (var->flags & INMEMORY) {
- var_to_reg_flt(s1, src, REG_FTMP1);
- i386_fstps_membase(cd, REG_SP, var->regoff * 4);
- fpu_st_offset--;
- } else {
- var_to_reg_flt(s1, src, var->regoff);
-/* M_FLTMOVE(s1, var->regoff); */
- i386_fstp_reg(cd, var->regoff + fpu_st_offset);
- fpu_st_offset--;
- }
- break;
-
- case ICMD_DSTORE: /* ..., value ==> ... */
- /* op1 = local variable */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
-
- if ((src->varkind == LOCALVAR) &&
- (src->varnum == iptr->op1)) {
- break;
- }
- var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
- if (var->flags & INMEMORY) {
- var_to_reg_flt(s1, src, REG_FTMP1);
- i386_fstpl_membase(cd, REG_SP, var->regoff * 4);
- fpu_st_offset--;
- } else {
- var_to_reg_flt(s1, src, var->regoff);
-/* M_FLTMOVE(s1, var->regoff); */
- i386_fstp_reg(cd, var->regoff + fpu_st_offset);
- fpu_st_offset--;
+ if (iptr->sx.val.anyptr == NULL)
+ M_CLR(d);
+ else
+ M_MOV_IMM(iptr->sx.val.anyptr, d);
}
+ emit_store_dst(jd, iptr, d);
break;
- /* pop/dup/swap operations ********************************************/
+ /* load/store/copy/move operations ************************************/
- /* attention: double and longs are only one entry in CACAO ICMDs */
+ case ICMD_ILOAD:
+ case ICMD_ALOAD:
+ case ICMD_LLOAD:
+ case ICMD_FLOAD:
+ case ICMD_DLOAD:
+ case ICMD_ISTORE:
+ case ICMD_LSTORE:
+ case ICMD_FSTORE:
+ case ICMD_DSTORE:
+ case ICMD_COPY:
+ case ICMD_MOVE:
- case ICMD_POP: /* ..., value ==> ... */
- case ICMD_POP2: /* ..., value, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
- break;
-
- case ICMD_DUP: /* ..., a ==> ..., a, a */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
- M_COPY(src, iptr->dst);
+ emit_copy(jd, iptr, VAROP(iptr->s1), VAROP(iptr->dst));
break;
- case ICMD_DUP2: /* ..., a, b ==> ..., a, b, a, b */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- M_COPY(src, iptr->dst);
- M_COPY(src->prev, iptr->dst->prev);
- break;
-
- case ICMD_DUP_X1: /* ..., a, b ==> ..., b, a, b */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- M_COPY(src, iptr->dst);
- M_COPY(src->prev, iptr->dst->prev);
- M_COPY(iptr->dst, iptr->dst->prev->prev);
- break;
-
- case ICMD_DUP_X2: /* ..., a, b, c ==> ..., c, a, b, c */
-
- M_COPY(src, iptr->dst);
- M_COPY(src->prev, iptr->dst->prev);
- M_COPY(src->prev->prev, iptr->dst->prev->prev);
- M_COPY(iptr->dst, iptr->dst->prev->prev->prev);
- break;
-
- case ICMD_DUP2_X1: /* ..., a, b, c ==> ..., b, c, a, b, c */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- M_COPY(src, iptr->dst);
- M_COPY(src->prev, iptr->dst->prev);
- M_COPY(src->prev->prev, iptr->dst->prev->prev);
- M_COPY(iptr->dst, iptr->dst->prev->prev->prev);
- M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev);
- break;
-
- case ICMD_DUP2_X2: /* ..., a, b, c, d ==> ..., c, d, a, b, c, d */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- M_COPY(src, iptr->dst);
- M_COPY(src->prev, iptr->dst->prev);
- M_COPY(src->prev->prev, iptr->dst->prev->prev);
- M_COPY(src->prev->prev->prev, iptr->dst->prev->prev->prev);
- M_COPY(iptr->dst, iptr->dst->prev->prev->prev->prev);
- M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev->prev);
- break;
-
- case ICMD_SWAP: /* ..., a, b ==> ..., b, a */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- M_COPY(src, iptr->dst->prev);
- M_COPY(src->prev, iptr->dst);
+ case ICMD_ASTORE:
+ if (!(iptr->flags.bits & INS_FLAG_RETADDR))
+ emit_copy(jd, iptr, VAROP(iptr->s1), VAROP(iptr->dst));
break;
/* integer operations *************************************************/
case ICMD_INEG: /* ..., value ==> ..., - value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- if (src->regoff == iptr->dst->regoff) {
- i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_neg_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- }
- } else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4);
- i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
- i386_neg_reg(cd, iptr->dst->regoff);
-
- } else {
- M_INTMOVE(src->regoff, iptr->dst->regoff);
- i386_neg_reg(cd, iptr->dst->regoff);
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_NEG(d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LNEG: /* ..., value ==> ..., - value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- if (src->regoff == iptr->dst->regoff) {
- i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4);
- i386_alu_imm_membase(cd, ALU_ADC, 0, REG_SP, iptr->dst->regoff * 4 + 4);
- i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4 + 4);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_neg_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP1);
- i386_neg_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ M_NEG(GET_LOW_REG(d));
+ M_IADDC_IMM(0, GET_HIGH_REG(d));
+ M_NEG(GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_I2L: /* ..., value ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: YES */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, EAX);
- i386_cltd(cd);
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4);
- } else {
- M_INTMOVE(src->regoff, EAX);
- i386_cltd(cd);
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
+ s1 = emit_load_s1(jd, iptr, EAX);
+ d = codegen_reg_of_dst(jd, iptr, EAX_EDX_PACKED);
+ M_INTMOVE(s1, EAX);
+ M_CLTD;
+ M_LNGMOVE(EAX_EDX_PACKED, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_L2I: /* ..., value ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- }
- } else {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
- }
- }
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ M_INTMOVE(s1, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_INT2BYTE: /* ..., value ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SHL, 24, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SAR, 24, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- } else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4);
- i386_shift_imm_membase(cd, I386_SHL, 24, REG_SP, iptr->dst->regoff * 4);
- i386_shift_imm_membase(cd, I386_SAR, 24, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
- i386_shift_imm_reg(cd, I386_SHL, 24, iptr->dst->regoff);
- i386_shift_imm_reg(cd, I386_SAR, 24, iptr->dst->regoff);
-
- } else {
- M_INTMOVE(src->regoff, iptr->dst->regoff);
- i386_shift_imm_reg(cd, I386_SHL, 24, iptr->dst->regoff);
- i386_shift_imm_reg(cd, I386_SAR, 24, iptr->dst->regoff);
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_SLL_IMM(24, d);
+ M_SRA_IMM(24, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_INT2CHAR: /* ..., value ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- if (src->regoff == iptr->dst->regoff) {
- i386_alu_imm_membase(cd, ALU_AND, 0x0000ffff, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4);
- i386_alu_imm_membase(cd, ALU_AND, 0x0000ffff, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
- i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, iptr->dst->regoff);
- } else {
- M_INTMOVE(src->regoff, iptr->dst->regoff);
- i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, iptr->dst->regoff);
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ M_CZEXT(s1, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_INT2SHORT: /* ..., value ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SHL, 16, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SAR, 16, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4);
- i386_shift_imm_membase(cd, I386_SHL, 16, REG_SP, iptr->dst->regoff * 4);
- i386_shift_imm_membase(cd, I386_SAR, 16, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
- i386_shift_imm_reg(cd, I386_SHL, 16, iptr->dst->regoff);
- i386_shift_imm_reg(cd, I386_SAR, 16, iptr->dst->regoff);
- } else {
- M_INTMOVE(src->regoff, iptr->dst->regoff);
- i386_shift_imm_reg(cd, I386_SHL, 16, iptr->dst->regoff);
- i386_shift_imm_reg(cd, I386_SAR, 16, iptr->dst->regoff);
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ M_SSEXT(s1, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IADD: /* ..., val1, val2 ==> ..., val1 + val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialu(cd, ALU_ADD, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ if (s2 == d)
+ M_IADD(s1, d);
+ else {
+ M_INTMOVE(s1, d);
+ M_IADD(s2, d);
+ }
+ emit_store_dst(jd, iptr, d);
break;
+ case ICMD_IINC:
case ICMD_IADDCONST: /* ..., value ==> ..., value + constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
+ /* sx.val.i = constant */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+
+ /* `inc reg' is slower on p4's (regarding to ia32
+ optimization reference manual and benchmarks) and as
+ fast on athlon's. */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, ALU_ADD, src, iptr);
+ M_INTMOVE(s1, d);
+ M_IADD_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LADD: /* ..., val1, val2 ==> ..., val1 + val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- if (src->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_ADD, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_ADC, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
-
- } else if (src->prev->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_ADD, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_ADC, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_ADD, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_ADC, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
- }
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_INTMOVE(s1, GET_LOW_REG(d));
+ M_IADD(s2, GET_LOW_REG(d));
+ /* don't use REG_ITMP1 */
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP3);
+ M_INTMOVE(s1, GET_HIGH_REG(d));
+ M_IADDC(s2, GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LADDCONST: /* ..., value ==> ..., value + constant */
- /* val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
- /* else path can never happen? longs stay in memory! */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- if (src->regoff == iptr->dst->regoff) {
- i386_alu_imm_membase(cd, ALU_ADD, iptr->val.l, REG_SP, iptr->dst->regoff * 4);
- i386_alu_imm_membase(cd, ALU_ADC, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4);
+ /* sx.val.l = constant */
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_ADD, iptr->val.l, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_ADC, iptr->val.l >> 32, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ M_IADD_IMM(iptr->sx.val.l, GET_LOW_REG(d));
+ M_IADDC_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_ISUB: /* ..., val1, val2 ==> ..., val1 - val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- if (src->prev->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- M_INTMOVE(src->prev->regoff, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- if (src->prev->regoff == iptr->dst->regoff) {
- i386_alu_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- i386_mov_reg_membase(cd, src->prev->regoff, REG_SP, iptr->dst->regoff * 4);
- i386_alu_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, d);
- i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, d);
-
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- M_INTMOVE(src->prev->regoff, d);
- i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, d);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- /* workaround for reg alloc */
- if (src->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
- M_INTMOVE(REG_ITMP1, d);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, d);
- i386_alu_reg_reg(cd, ALU_SUB, src->regoff, d);
- }
-
- } else {
- /* workaround for reg alloc */
- if (src->regoff == iptr->dst->regoff) {
- M_INTMOVE(src->prev->regoff, REG_ITMP1);
- i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
- M_INTMOVE(REG_ITMP1, d);
- } else {
- M_INTMOVE(src->prev->regoff, d);
- i386_alu_reg_reg(cd, ALU_SUB, src->regoff, d);
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ if (s2 == d) {
+ M_INTMOVE(s1, REG_ITMP1);
+ M_ISUB(s2, REG_ITMP1);
+ M_INTMOVE(REG_ITMP1, d);
}
+ else {
+ M_INTMOVE(s1, d);
+ M_ISUB(s2, d);
+ }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_ISUBCONST: /* ..., value ==> ..., value + constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
+ /* sx.val.i = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, ALU_SUB, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_ISUB_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- if (src->prev->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_SBB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_SBB, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ if (s2 == GET_LOW_REG(d)) {
+ M_INTMOVE(s1, REG_ITMP1);
+ M_ISUB(s2, REG_ITMP1);
+ M_INTMOVE(REG_ITMP1, GET_LOW_REG(d));
+ }
+ else {
+ M_INTMOVE(s1, GET_LOW_REG(d));
+ M_ISUB(s2, GET_LOW_REG(d));
}
+ /* don't use REG_ITMP1 */
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP3);
+ if (s2 == GET_HIGH_REG(d)) {
+ M_INTMOVE(s1, REG_ITMP2);
+ M_ISUBB(s2, REG_ITMP2);
+ M_INTMOVE(REG_ITMP2, GET_HIGH_REG(d));
+ }
+ else {
+ M_INTMOVE(s1, GET_HIGH_REG(d));
+ M_ISUBB(s2, GET_HIGH_REG(d));
+ }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LSUBCONST: /* ..., value ==> ..., value - constant */
- /* val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO */
- /* else path can never happen? longs stay in memory! */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- if (src->regoff == iptr->dst->regoff) {
- i386_alu_imm_membase(cd, ALU_SUB, iptr->val.l, REG_SP, iptr->dst->regoff * 4);
- i386_alu_imm_membase(cd, ALU_SBB, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4);
+ /* sx.val.l = constant */
- } else {
- /* TODO: could be size optimized with lea -- see gcc output */
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_SUB, iptr->val.l, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_SBB, iptr->val.l >> 32, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ M_ISUB_IMM(iptr->sx.val.l, GET_LOW_REG(d));
+ M_ISUBB_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO OUTPUT: EAX*/ /* EDX really not destroyed by IMUL? */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
-
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_imul_reg_reg(cd, src->prev->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_imul_reg_reg(cd, src->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- i386_mov_reg_reg(cd, src->prev->regoff, REG_ITMP1);
- i386_imul_reg_reg(cd, src->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- }
-
- } else {
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, iptr->dst->regoff);
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- M_INTMOVE(src->prev->regoff, iptr->dst->regoff);
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- M_INTMOVE(src->regoff, iptr->dst->regoff);
- i386_imul_membase_reg(cd, REG_SP, src->prev->regoff * 4, iptr->dst->regoff);
-
- } else {
- if (src->regoff == iptr->dst->regoff) {
- i386_imul_reg_reg(cd, src->prev->regoff, iptr->dst->regoff);
-
- } else {
- M_INTMOVE(src->prev->regoff, iptr->dst->regoff);
- i386_imul_reg_reg(cd, src->regoff, iptr->dst->regoff);
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ if (s2 == d)
+ M_IMUL(s1, d);
+ else {
+ M_INTMOVE(s1, d);
+ M_IMUL(s2, d);
}
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IMULCONST: /* ..., value ==> ..., value * constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: EAX*/ /* EDX really not destroyed by IMUL? */
+ /* sx.val.i = constant */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ M_IMUL_IMM(s1, iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
+ break;
+
+ case ICMD_LMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ s2 = emit_load_s2_low(jd, iptr, EDX);
+ d = codegen_reg_of_dst(jd, iptr, EAX_EDX_PACKED);
- } else {
- i386_imul_imm_reg_reg(cd, iptr->val.i, src->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- }
+ M_INTMOVE(s1, REG_ITMP2);
+ M_IMUL(s2, REG_ITMP2);
- } else {
- if (src->flags & INMEMORY) {
- i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 4, iptr->dst->regoff);
+ s1 = emit_load_s1_low(jd, iptr, EAX);
+ s2 = emit_load_s2_high(jd, iptr, EDX);
+ M_INTMOVE(s2, EDX);
+ M_IMUL(s1, EDX);
+ M_IADD(EDX, REG_ITMP2);
- } else {
- i386_imul_imm_reg_reg(cd, iptr->val.i, src->regoff, iptr->dst->regoff);
- }
- }
- break;
+ s1 = emit_load_s1_low(jd, iptr, EAX);
+ s2 = emit_load_s2_low(jd, iptr, EDX);
+ M_INTMOVE(s1, EAX);
+ M_MUL(s2);
+ M_INTMOVE(EAX, GET_LOW_REG(d));
+ M_IADD(REG_ITMP2, GET_HIGH_REG(d));
- case ICMD_LMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX); /* mem -> EAX */
- /* optimize move EAX -> REG_ITMP3 is slower??? */
-/* i386_mov_reg_reg(cd, EAX, REG_ITMP3); */
- i386_mul_membase(cd, REG_SP, src->regoff * 4); /* mem * EAX -> EDX:EAX */
-
- /* TODO: optimize move EAX -> REG_ITMP3 */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); /* mem -> ITMP3 */
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
- i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
-
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP2); /* mem -> ITMP3 */
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
-
- i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LMULCONST: /* ..., value ==> ..., value * constant */
- /* val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- i386_mov_imm_reg(cd, iptr->val.l, EAX); /* imm -> EAX */
- i386_mul_membase(cd, REG_SP, src->regoff * 4); /* mem * EAX -> EDX:EAX */
- /* TODO: optimize move EAX -> REG_ITMP3 */
- i386_mov_imm_reg(cd, iptr->val.l >> 32, REG_ITMP2); /* imm -> ITMP3 */
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
-
- i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
- i386_mov_imm_reg(cd, iptr->val.l, REG_ITMP2); /* imm -> ITMP3 */
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
-
- i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
+ /* sx.val.l = constant */
+
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, EAX_EDX_PACKED);
+ ICONST(EAX, iptr->sx.val.l);
+ M_MUL(s1);
+ M_IMUL_IMM(s1, iptr->sx.val.l >> 32, REG_ITMP2);
+ M_IADD(REG_ITMP2, EDX);
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ M_IMUL_IMM(s1, iptr->sx.val.l, REG_ITMP2);
+ M_IADD(REG_ITMP2, EDX);
+ M_LNGMOVE(EAX_EDX_PACKED, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EAX */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- var_to_reg_int(s1, src, REG_ITMP2);
- gen_div_check(src);
- if (src->prev->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX);
+ s1 = emit_load_s1(jd, iptr, EAX);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, EAX);
+ emit_arithmetic_check(cd, iptr, s2);
- } else {
- M_INTMOVE(src->prev->regoff, EAX);
- }
+ M_INTMOVE(s1, EAX); /* we need the first operand in EAX */
/* check as described in jvm spec */
- i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, EAX);
- i386_jcc(cd, I386_CC_NE, 3 + 6);
- i386_alu_imm_reg(cd, ALU_CMP, -1, s1);
- i386_jcc(cd, I386_CC_E, 1 + 2);
-
- i386_cltd(cd);
- i386_idiv_reg(cd, s1);
+ M_CMP_IMM(0x80000000, EAX);
+ M_BNE(3 + 6);
+ M_CMP_IMM(-1, s2);
+ M_BEQ(1 + 2);
+ M_CLTD;
+ M_IDIV(s2);
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- M_INTMOVE(EAX, iptr->dst->regoff);
- }
+ M_INTMOVE(EAX, d); /* if INMEMORY then d is already EAX */
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IREM: /* ..., val1, val2 ==> ..., val1 % val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EDX */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- var_to_reg_int(s1, src, REG_ITMP2);
- gen_div_check(src);
- if (src->prev->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX);
+ s1 = emit_load_s1(jd, iptr, EAX);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, EDX);
+ emit_arithmetic_check(cd, iptr, s2);
- } else {
- M_INTMOVE(src->prev->regoff, EAX);
- }
+ M_INTMOVE(s1, EAX); /* we need the first operand in EAX */
/* check as described in jvm spec */
- i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, EAX);
- i386_jcc(cd, I386_CC_NE, 2 + 3 + 6);
- i386_alu_reg_reg(cd, ALU_XOR, EDX, EDX);
- i386_alu_imm_reg(cd, ALU_CMP, -1, s1);
- i386_jcc(cd, I386_CC_E, 1 + 2);
-
- i386_cltd(cd);
- i386_idiv_reg(cd, s1);
-
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4);
+ M_CMP_IMM(0x80000000, EAX);
+ M_BNE(2 + 3 + 6);
+ M_CLR(EDX);
+ M_CMP_IMM(-1, s2);
+ M_BEQ(1 + 2);
+ M_CLTD;
+ M_IDIV(s2);
- } else {
- M_INTMOVE(EDX, iptr->dst->regoff);
- }
+ M_INTMOVE(EDX, d); /* if INMEMORY then d is already EDX */
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IDIVPOW2: /* ..., value ==> ..., value >> constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL */
+ /* sx.val.i = constant */
/* TODO: optimize for `/ 2' */
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
-
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
M_INTMOVE(s1, d);
- i386_test_reg_reg(cd, d, d);
- disp = 2;
- CALCIMMEDIATEBYTES(disp, (1 << iptr->val.i) - 1);
- i386_jcc(cd, I386_CC_NS, disp);
- i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.i) - 1, d);
-
- i386_shift_imm_reg(cd, I386_SAR, iptr->val.i, d);
- store_reg_to_var_int(iptr->dst, d);
+ M_TEST(d);
+ M_BNS(6);
+ M_IADD_IMM32((1 << iptr->sx.val.i) - 1, d);/* 32-bit for jump off */
+ M_SRA_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IREMPOW2: /* ..., value ==> ..., value % constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */
+ /* sx.val.i = constant */
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_ITMP2);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
if (s1 == d) {
- M_INTMOVE(s1, REG_ITMP1);
+ M_MOV(s1, REG_ITMP1);
s1 = REG_ITMP1;
}
-
- disp = 2;
- disp += 2;
- disp += 2;
- CALCIMMEDIATEBYTES(disp, iptr->val.i);
- disp += 2;
-
- /* TODO: optimize */
M_INTMOVE(s1, d);
- i386_alu_imm_reg(cd, ALU_AND, iptr->val.i, d);
- i386_test_reg_reg(cd, s1, s1);
- i386_jcc(cd, I386_CC_GE, disp);
- i386_mov_reg_reg(cd, s1, d);
- i386_neg_reg(cd, d);
- i386_alu_imm_reg(cd, ALU_AND, iptr->val.i, d);
- i386_neg_reg(cd, d);
-
-/* M_INTMOVE(s1, EAX); */
-/* i386_cltd(cd); */
-/* i386_alu_reg_reg(cd, ALU_XOR, EDX, EAX); */
-/* i386_alu_reg_reg(cd, ALU_SUB, EDX, EAX); */
-/* i386_alu_reg_reg(cd, ALU_AND, iptr->val.i, EAX); */
-/* i386_alu_reg_reg(cd, ALU_XOR, EDX, EAX); */
-/* i386_alu_reg_reg(cd, ALU_SUB, EDX, EAX); */
-/* M_INTMOVE(EAX, d); */
-
-/* i386_alu_reg_reg(cd, ALU_XOR, d, d); */
-/* i386_mov_imm_reg(cd, iptr->val.i, ECX); */
-/* i386_shrd_reg_reg(cd, s1, d); */
-/* i386_shift_imm_reg(cd, I386_SHR, 32 - iptr->val.i, d); */
-
- store_reg_to_var_int(iptr->dst, d);
+ M_AND_IMM(iptr->sx.val.i, d);
+ M_TEST(s1);
+ M_BGE(2 + 2 + 6 + 2);
+ M_MOV(s1, d); /* don't use M_INTMOVE, so we know the jump offset */
+ M_NEG(d);
+ M_AND_IMM32(iptr->sx.val.i, d); /* use 32-bit for jump offset */
+ M_NEG(d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
case ICMD_LREM: /* ..., val1, val2 ==> ..., val1 % val2 */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- M_ILD(REG_ITMP2, REG_SP, src->regoff * 4);
- M_OR_MEMBASE(REG_SP, src->regoff * 4 + 4, REG_ITMP2);
- M_TEST(REG_ITMP2);
- M_BEQ(0);
- codegen_addxdivrefs(cd, cd->mcodeptr);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_RESULT_PACKED);
- bte = iptr->val.a;
+ M_INTMOVE(GET_LOW_REG(s2), REG_ITMP3);
+ M_OR(GET_HIGH_REG(s2), REG_ITMP3);
+ /* XXX could be optimized */
+ emit_arithmetic_check(cd, iptr, REG_ITMP3);
+
+ bte = iptr->sx.s23.s3.bte;
md = bte->md;
- M_ILD(REG_ITMP1, REG_SP, src->prev->regoff * 4);
- M_ILD(REG_ITMP2, REG_SP, src->prev->regoff * 4 + 4);
- M_IST(REG_ITMP1, REG_SP, 0 * 4);
- M_IST(REG_ITMP2, REG_SP, 0 * 4 + 4);
+ M_LST(s2, REG_SP, 2 * 4);
- M_ILD(REG_ITMP1, REG_SP, src->regoff * 4);
- M_ILD(REG_ITMP2, REG_SP, src->regoff * 4 + 4);
- M_IST(REG_ITMP1, REG_SP, 2 * 4);
- M_IST(REG_ITMP2, REG_SP, 2 * 4 + 4);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ M_LST(s1, REG_SP, 0 * 4);
- M_MOV_IMM((ptrint) bte->fp, REG_ITMP3);
+ M_MOV_IMM(bte->fp, REG_ITMP3);
M_CALL(REG_ITMP3);
-
- M_IST(REG_RESULT, REG_SP, iptr->dst->regoff * 4);
- M_IST(REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LDIVPOW2: /* ..., value ==> ..., value >> constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- disp = 2;
- CALCIMMEDIATEBYTES(disp, (1 << iptr->val.i) - 1);
- disp += 3;
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
-
- i386_test_reg_reg(cd, REG_ITMP2, REG_ITMP2);
- i386_jcc(cd, I386_CC_NS, disp);
- i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.i) - 1, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2);
- i386_shrd_imm_reg_reg(cd, iptr->val.i, REG_ITMP2, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SAR, iptr->val.i, REG_ITMP2);
-
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
- }
- }
+ /* sx.val.i = constant */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_RESULT_PACKED);
+ M_LNGMOVE(s1, d);
+ M_TEST(GET_HIGH_REG(d));
+ M_BNS(6 + 3);
+ M_IADD_IMM32((1 << iptr->sx.val.i) - 1, GET_LOW_REG(d));
+ M_IADDC_IMM(0, GET_HIGH_REG(d));
+ M_SRLD_IMM(iptr->sx.val.i, GET_HIGH_REG(d), GET_LOW_REG(d));
+ M_SRA_IMM(iptr->sx.val.i, GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
+#if 0
case ICMD_LREMPOW2: /* ..., value ==> ..., value % constant */
- /* val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- /* Intel algorithm -- does not work, because constant is wrong */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP3); */
-
-/* M_INTMOVE(REG_ITMP1, REG_ITMP2); */
-/* i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3); */
-/* i386_jcc(cd, I386_CC_NS, offset); */
-/* i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.l) - 1, REG_ITMP2); */
-/* i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP3); */
-
-/* i386_shrd_imm_reg_reg(cd, iptr->val.l, REG_ITMP3, REG_ITMP2); */
-/* i386_shift_imm_reg(cd, I386_SAR, iptr->val.l, REG_ITMP3); */
-/* i386_shld_imm_reg_reg(cd, iptr->val.l, REG_ITMP2, REG_ITMP3); */
-
-/* i386_shift_imm_reg(cd, I386_SHL, iptr->val.l, REG_ITMP2); */
-
-/* i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP2, REG_ITMP1); */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); */
-/* i386_alu_reg_reg(cd, ALU_SBB, REG_ITMP3, REG_ITMP2); */
-
-/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */
-/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */
+ /* sx.val.l = constant */
+ d = codegen_reg_of_dst(jd, iptr, REG_NULL);
+ if (iptr->dst.var->flags & INMEMORY) {
+ if (iptr->s1.var->flags & INMEMORY) {
/* Alpha algorithm */
disp = 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->vv.regoff * 4);
disp += 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4 + 4);
+ CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->vv.regoff * 4 + 4);
disp += 2;
disp += 3;
/* TODO: hmm, don't know if this is always correct */
disp += 2;
- CALCIMMEDIATEBYTES(disp, iptr->val.l & 0x00000000ffffffff);
+ CALCIMMEDIATEBYTES(disp, iptr->sx.val.l & 0x00000000ffffffff);
disp += 2;
- CALCIMMEDIATEBYTES(disp, iptr->val.l >> 32);
+ CALCIMMEDIATEBYTES(disp, iptr->sx.val.l >> 32);
disp += 2;
disp += 3;
disp += 2;
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
+ emit_mov_membase_reg(cd, REG_SP, iptr->s1.var->vv.regoff * 4, REG_ITMP1);
+ emit_mov_membase_reg(cd, REG_SP, iptr->s1.var->vv.regoff * 4 + 4, REG_ITMP2);
- i386_alu_imm_reg(cd, ALU_AND, iptr->val.l, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_AND, iptr->val.l >> 32, REG_ITMP2);
- i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4 + 4);
- i386_jcc(cd, I386_CC_GE, disp);
+ emit_alu_imm_reg(cd, ALU_AND, iptr->sx.val.l, REG_ITMP1);
+ emit_alu_imm_reg(cd, ALU_AND, iptr->sx.val.l >> 32, REG_ITMP2);
+ emit_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->s1.var->vv.regoff * 4 + 4);
+ emit_jcc(cd, CC_GE, disp);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
+ emit_mov_membase_reg(cd, REG_SP, iptr->s1.var->vv.regoff * 4, REG_ITMP1);
+ emit_mov_membase_reg(cd, REG_SP, iptr->s1.var->vv.regoff * 4 + 4, REG_ITMP2);
- i386_neg_reg(cd, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2);
- i386_neg_reg(cd, REG_ITMP2);
+ emit_neg_reg(cd, REG_ITMP1);
+ emit_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2);
+ emit_neg_reg(cd, REG_ITMP2);
- i386_alu_imm_reg(cd, ALU_AND, iptr->val.l, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_AND, iptr->val.l >> 32, REG_ITMP2);
+ emit_alu_imm_reg(cd, ALU_AND, iptr->sx.val.l, REG_ITMP1);
+ emit_alu_imm_reg(cd, ALU_AND, iptr->sx.val.l >> 32, REG_ITMP2);
- i386_neg_reg(cd, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2);
- i386_neg_reg(cd, REG_ITMP2);
+ emit_neg_reg(cd, REG_ITMP1);
+ emit_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2);
+ emit_neg_reg(cd, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
+ emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst.var->vv.regoff * 4);
+ emit_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst.var->vv.regoff * 4 + 4);
}
}
- break;
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_RESULT_PACKED);
+ M_LNGMOVE(s1, d);
+ M_AND_IMM(iptr->sx.val.l, GET_LOW_REG(d));
+ M_AND_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d));
+ M_TEST(GET_LOW_REG(s1));
+ M_BGE(0);
+ M_LNGMOVE(s1, d);
+ break;
+#endif
case ICMD_ISHL: /* ..., val1, val2 ==> ..., val1 << val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ishift(cd, I386_SHL, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s2, ECX); /* s2 may be equal to d */
+ M_INTMOVE(s1, d);
+ M_SLL(d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_ISHLCONST: /* ..., value ==> ..., value << constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.i = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ishiftconst(cd, I386_SHL, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_SLL_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_ISHR: /* ..., val1, val2 ==> ..., val1 >> val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ishift(cd, I386_SAR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s2, ECX); /* s2 may be equal to d */
+ M_INTMOVE(s1, d);
+ M_SRA(d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_ISHRCONST: /* ..., value ==> ..., value >> constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.i = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ishiftconst(cd, I386_SAR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_SRA_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ishift(cd, I386_SHR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s2, ECX); /* s2 may be equal to d */
+ M_INTMOVE(s1, d);
+ M_SRL(d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IUSHRCONST: /* ..., value ==> ..., value >>> constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.i = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ishiftconst(cd, I386_SHR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_SRL_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LSHL: /* ..., val1, val2 ==> ..., val1 << val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: YES EDX: S|YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY ){
- if (src->prev->flags & INMEMORY) {
-/* if (src->prev->regoff == iptr->dst->regoff) { */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */
-
-/* if (src->flags & INMEMORY) { */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */
-/* } else { */
-/* M_INTMOVE(src->regoff, ECX); */
-/* } */
-
-/* i386_test_imm_reg(cd, 32, ECX); */
-/* i386_jcc(cd, I386_CC_E, 2 + 2); */
-/* i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP2); */
-/* i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1); */
-
-/* i386_shld_reg_membase(cd, REG_ITMP1, REG_SP, src->prev->regoff * 4 + 4); */
-/* i386_shift_membase(cd, I386_SHL, REG_SP, iptr->dst->regoff * 4); */
-
-/* } else { */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3);
-
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX);
- } else {
- M_INTMOVE(src->regoff, ECX);
- }
-
- i386_test_imm_reg(cd, 32, ECX);
- i386_jcc(cd, I386_CC_E, 2 + 2);
- i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP3);
- i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
-
- i386_shld_reg_reg(cd, REG_ITMP1, REG_ITMP3);
- i386_shift_reg(cd, I386_SHL, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
-/* } */
- }
- }
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP13_PACKED);
+ s2 = emit_load_s2(jd, iptr, ECX);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP13_PACKED);
+ M_LNGMOVE(s1, d);
+ M_INTMOVE(s2, ECX);
+ M_TEST_IMM(32, ECX);
+ M_BEQ(2 + 2);
+ M_MOV(GET_LOW_REG(d), GET_HIGH_REG(d));
+ M_CLR(GET_LOW_REG(d));
+ M_SLLD(GET_LOW_REG(d), GET_HIGH_REG(d));
+ M_SLL(GET_LOW_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LSHLCONST: /* ..., value ==> ..., value << constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY ) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
-
- if (iptr->val.i & 0x20) {
- i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP2);
- i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
- i386_shld_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP1, REG_ITMP2);
+ /* sx.val.i = constant */
- } else {
- i386_shld_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP1, REG_ITMP2);
- i386_shift_imm_reg(cd, I386_SHL, iptr->val.i & 0x3f, REG_ITMP1);
- }
-
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ if (iptr->sx.val.i & 0x20) {
+ M_MOV(GET_LOW_REG(d), GET_HIGH_REG(d));
+ M_CLR(GET_LOW_REG(d));
+ M_SLLD_IMM(iptr->sx.val.i & 0x3f, GET_LOW_REG(d),
+ GET_HIGH_REG(d));
+ }
+ else {
+ M_SLLD_IMM(iptr->sx.val.i & 0x3f, GET_LOW_REG(d),
+ GET_HIGH_REG(d));
+ M_SLL_IMM(iptr->sx.val.i & 0x3f, GET_LOW_REG(d));
}
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LSHR: /* ..., val1, val2 ==> ..., val1 >> val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: YES S|EDX: YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY ){
- if (src->prev->flags & INMEMORY) {
-/* if (src->prev->regoff == iptr->dst->regoff) { */
- /* TODO: optimize */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); */
-
-/* if (src->flags & INMEMORY) { */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */
-/* } else { */
-/* M_INTMOVE(src->regoff, ECX); */
-/* } */
-
-/* i386_test_imm_reg(cd, 32, ECX); */
-/* i386_jcc(cd, I386_CC_E, 2 + 3); */
-/* i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1); */
-/* i386_shift_imm_reg(cd, I386_SAR, 31, REG_ITMP2); */
-
-/* i386_shrd_reg_reg(cd, REG_ITMP2, REG_ITMP1); */
-/* i386_shift_reg(cd, I386_SAR, REG_ITMP2); */
-/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */
-/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */
-
-/* } else { */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3);
-
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX);
- } else {
- M_INTMOVE(src->regoff, ECX);
- }
- i386_test_imm_reg(cd, 32, ECX);
- i386_jcc(cd, I386_CC_E, 2 + 3);
- i386_mov_reg_reg(cd, REG_ITMP3, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SAR, 31, REG_ITMP3);
-
- i386_shrd_reg_reg(cd, REG_ITMP3, REG_ITMP1);
- i386_shift_reg(cd, I386_SAR, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
-/* } */
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP13_PACKED);
+ s2 = emit_load_s2(jd, iptr, ECX);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP13_PACKED);
+ M_LNGMOVE(s1, d);
+ M_INTMOVE(s2, ECX);
+ M_TEST_IMM(32, ECX);
+ M_BEQ(2 + 3);
+ M_MOV(GET_HIGH_REG(d), GET_LOW_REG(d));
+ M_SRA_IMM(31, GET_HIGH_REG(d));
+ M_SRLD(GET_HIGH_REG(d), GET_LOW_REG(d));
+ M_SRA(GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LSHRCONST: /* ..., value ==> ..., value >> constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY ) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
-
- if (iptr->val.i & 0x20) {
- i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SAR, 31, REG_ITMP2);
- i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1);
-
- } else {
- i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SAR, iptr->val.i & 0x3f, REG_ITMP2);
- }
+ /* sx.val.i = constant */
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ if (iptr->sx.val.i & 0x20) {
+ M_MOV(GET_HIGH_REG(d), GET_LOW_REG(d));
+ M_SRA_IMM(31, GET_HIGH_REG(d));
+ M_SRLD_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d),
+ GET_LOW_REG(d));
+ }
+ else {
+ M_SRLD_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d),
+ GET_LOW_REG(d));
+ M_SRA_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d));
}
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: YES EDX: S|YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY ){
- if (src->prev->flags & INMEMORY) {
-/* if (src->prev->regoff == iptr->dst->regoff) { */
- /* TODO: optimize */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); */
-
-/* if (src->flags & INMEMORY) { */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */
-/* } else { */
-/* M_INTMOVE(src->regoff, ECX); */
-/* } */
-
-/* i386_test_imm_reg(cd, 32, ECX); */
-/* i386_jcc(cd, I386_CC_E, 2 + 2); */
-/* i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1); */
-/* i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2); */
-
-/* i386_shrd_reg_reg(cd, REG_ITMP2, REG_ITMP1); */
-/* i386_shift_reg(cd, I386_SHR, REG_ITMP2); */
-/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */
-/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */
-
-/* } else { */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3);
-
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX);
- } else {
- M_INTMOVE(src->regoff, ECX);
- }
- i386_test_imm_reg(cd, 32, ECX);
- i386_jcc(cd, I386_CC_E, 2 + 2);
- i386_mov_reg_reg(cd, REG_ITMP3, REG_ITMP1);
- i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP3, REG_ITMP3);
-
- i386_shrd_reg_reg(cd, REG_ITMP3, REG_ITMP1);
- i386_shift_reg(cd, I386_SHR, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
-/* } */
- }
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP13_PACKED);
+ s2 = emit_load_s2(jd, iptr, ECX);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP13_PACKED);
+ M_LNGMOVE(s1, d);
+ M_INTMOVE(s2, ECX);
+ M_TEST_IMM(32, ECX);
+ M_BEQ(2 + 2);
+ M_MOV(GET_HIGH_REG(d), GET_LOW_REG(d));
+ M_CLR(GET_HIGH_REG(d));
+ M_SRLD(GET_HIGH_REG(d), GET_LOW_REG(d));
+ M_SRL(GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LUSHRCONST: /* ..., value ==> ..., value >>> constant */
- /* val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.l = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY ) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
-
- if (iptr->val.i & 0x20) {
- i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1);
- i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2);
- i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1);
-
- } else {
- i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SHR, iptr->val.i & 0x3f, REG_ITMP2);
- }
-
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ if (iptr->sx.val.i & 0x20) {
+ M_MOV(GET_HIGH_REG(d), GET_LOW_REG(d));
+ M_CLR(GET_HIGH_REG(d));
+ M_SRLD_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d),
+ GET_LOW_REG(d));
+ }
+ else {
+ M_SRLD_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d),
+ GET_LOW_REG(d));
+ M_SRL_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d));
}
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IAND: /* ..., val1, val2 ==> ..., val1 & val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialu(cd, ALU_AND, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ if (s2 == d)
+ M_AND(s1, d);
+ else {
+ M_INTMOVE(s1, d);
+ M_AND(s2, d);
+ }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IANDCONST: /* ..., value ==> ..., value & constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.i = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, ALU_AND, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_AND_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LAND: /* ..., val1, val2 ==> ..., val1 & val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_lalu(cd, ALU_AND, src, iptr);
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ if (s2 == GET_LOW_REG(d))
+ M_AND(s1, GET_LOW_REG(d));
+ else {
+ M_INTMOVE(s1, GET_LOW_REG(d));
+ M_AND(s2, GET_LOW_REG(d));
+ }
+ /* REG_ITMP1 probably contains low 32-bit of destination */
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP3);
+ if (s2 == GET_HIGH_REG(d))
+ M_AND(s1, GET_HIGH_REG(d));
+ else {
+ M_INTMOVE(s1, GET_HIGH_REG(d));
+ M_AND(s2, GET_HIGH_REG(d));
+ }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LANDCONST: /* ..., value ==> ..., value & constant */
- /* val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.l = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_laluconst(cd, ALU_AND, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ M_AND_IMM(iptr->sx.val.l, GET_LOW_REG(d));
+ M_AND_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IOR: /* ..., val1, val2 ==> ..., val1 | val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialu(cd, ALU_OR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ if (s2 == d)
+ M_OR(s1, d);
+ else {
+ M_INTMOVE(s1, d);
+ M_OR(s2, d);
+ }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IORCONST: /* ..., value ==> ..., value | constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.i = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, ALU_OR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_OR_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LOR: /* ..., val1, val2 ==> ..., val1 | val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_lalu(cd, ALU_OR, src, iptr);
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ if (s2 == GET_LOW_REG(d))
+ M_OR(s1, GET_LOW_REG(d));
+ else {
+ M_INTMOVE(s1, GET_LOW_REG(d));
+ M_OR(s2, GET_LOW_REG(d));
+ }
+ /* REG_ITMP1 probably contains low 32-bit of destination */
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP3);
+ if (s2 == GET_HIGH_REG(d))
+ M_OR(s1, GET_HIGH_REG(d));
+ else {
+ M_INTMOVE(s1, GET_HIGH_REG(d));
+ M_OR(s2, GET_HIGH_REG(d));
+ }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LORCONST: /* ..., value ==> ..., value | constant */
- /* val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.l = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_laluconst(cd, ALU_OR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ M_OR_IMM(iptr->sx.val.l, GET_LOW_REG(d));
+ M_OR_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialu(cd, ALU_XOR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ if (s2 == d)
+ M_XOR(s1, d);
+ else {
+ M_INTMOVE(s1, d);
+ M_XOR(s2, d);
+ }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IXORCONST: /* ..., value ==> ..., value ^ constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
+ /* sx.val.i = constant */
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, ALU_XOR, src, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ M_INTMOVE(s1, d);
+ M_XOR_IMM(iptr->sx.val.i, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_lalu(cd, ALU_XOR, src, iptr);
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ if (s2 == GET_LOW_REG(d))
+ M_XOR(s1, GET_LOW_REG(d));
+ else {
+ M_INTMOVE(s1, GET_LOW_REG(d));
+ M_XOR(s2, GET_LOW_REG(d));
+ }
+ /* REG_ITMP1 probably contains low 32-bit of destination */
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP3);
+ if (s2 == GET_HIGH_REG(d))
+ M_XOR(s1, GET_HIGH_REG(d));
+ else {
+ M_INTMOVE(s1, GET_HIGH_REG(d));
+ M_XOR(s2, GET_HIGH_REG(d));
+ }
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_LXORCONST: /* ..., value ==> ..., value ^ constant */
- /* val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_laluconst(cd, ALU_XOR, src, iptr);
- break;
-
- case ICMD_IINC: /* ..., value ==> ..., value + constant */
- /* op1 = variable, val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL */
+ /* sx.val.l = constant */
- var = &(rd->locals[iptr->op1][TYPE_INT]);
- if (var->flags & INMEMORY)
- M_IADD_IMM_MEMBASE(iptr->val.i, REG_SP, var->regoff * 4);
- else {
- /* `inc reg' is slower on p4's (regarding to ia32
- optimization reference manual and benchmarks) and
- as fast on athlon's. */
- M_IADD_IMM(iptr->val.i, var->regoff);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED);
+ M_LNGMOVE(s1, d);
+ M_XOR_IMM(iptr->sx.val.l, GET_LOW_REG(d));
+ M_XOR_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d));
+ emit_store_dst(jd, iptr, d);
break;
/* floating operations ************************************************/
-#if 0
-#define ROUND_TO_SINGLE \
- i386_fstps_membase(cd, REG_SP, -8); \
- i386_flds_membase(cd, REG_SP, -8);
-
-#define ROUND_TO_DOUBLE \
- i386_fstpl_membase(cd, REG_SP, -8); \
- i386_fldl_membase(cd, REG_SP, -8);
-
-#define FPU_SET_24BIT_MODE \
- if (!fpu_in_24bit_mode) { \
- i386_fldcw_mem(cd, &fpu_ctrlwrd_24bit); \
- fpu_in_24bit_mode = 1; \
- }
-#define FPU_SET_53BIT_MODE \
- if (fpu_in_24bit_mode) { \
- i386_fldcw_mem(cd, &fpu_ctrlwrd_53bit); \
- fpu_in_24bit_mode = 0; \
- }
-#else
-#define ROUND_TO_SINGLE
-#define ROUND_TO_DOUBLE
-#define FPU_SET_24BIT_MODE
-#define FPU_SET_53BIT_MODE
-#endif
case ICMD_FNEG: /* ..., value ==> ..., - value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_24BIT_MODE;
- var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- i386_fchs(cd);
- store_reg_to_var_flt(iptr->dst, d);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ emit_fchs(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_DNEG: /* ..., value ==> ..., - value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_53BIT_MODE;
- var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- i386_fchs(cd);
- store_reg_to_var_flt(iptr->dst, d);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ emit_fchs(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_FADD: /* ..., val1, val2 ==> ..., val1 + val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_24BIT_MODE;
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
- var_to_reg_flt(s2, src, REG_FTMP2);
- i386_faddp(cd);
- fpu_st_offset--;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ emit_faddp(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_DADD: /* ..., val1, val2 ==> ..., val1 + val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_53BIT_MODE;
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
- var_to_reg_flt(s2, src, REG_FTMP2);
- i386_faddp(cd);
- fpu_st_offset--;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ emit_faddp(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_FSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_24BIT_MODE;
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
- var_to_reg_flt(s2, src, REG_FTMP2);
- i386_fsubp(cd);
- fpu_st_offset--;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ emit_fsubp(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_DSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_53BIT_MODE;
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
- var_to_reg_flt(s2, src, REG_FTMP2);
- i386_fsubp(cd);
- fpu_st_offset--;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ emit_fsubp(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_FMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_24BIT_MODE;
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
- var_to_reg_flt(s2, src, REG_FTMP2);
- i386_fmulp(cd);
- fpu_st_offset--;
- ROUND_TO_SINGLE;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ emit_fmulp(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_DMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
-
- FPU_SET_53BIT_MODE;
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
-
-/* i386_fldt_mem(cd, subnormal_bias1); */
-/* i386_fmulp(cd); */
- var_to_reg_flt(s2, src, REG_FTMP2);
-
- i386_fmulp(cd);
- fpu_st_offset--;
-
-/* i386_fldt_mem(cd, subnormal_bias2); */
-/* i386_fmulp(cd); */
-
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ emit_fmulp(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_FDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_24BIT_MODE;
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
- var_to_reg_flt(s2, src, REG_FTMP2);
- i386_fdivp(cd);
- fpu_st_offset--;
- ROUND_TO_SINGLE;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ emit_fdivp(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_DDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
-
- FPU_SET_53BIT_MODE;
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
-/* i386_fldt_mem(cd, subnormal_bias1); */
-/* i386_fmulp(cd); */
-
- var_to_reg_flt(s2, src, REG_FTMP2);
-
- i386_fdivp(cd);
- fpu_st_offset--;
-
-/* i386_fldt_mem(cd, subnormal_bias2); */
-/* i386_fmulp(cd); */
-
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ emit_fdivp(cd);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_FREM: /* ..., val1, val2 ==> ..., val1 % val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_24BIT_MODE;
/* exchanged to skip fxch */
- var_to_reg_flt(s2, src, REG_FTMP2);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
-/* i386_fxch(cd); */
- i386_fprem(cd);
- i386_wait(cd);
- i386_fnstsw(cd);
- i386_sahf(cd);
- i386_jcc(cd, I386_CC_P, -(2 + 1 + 2 + 1 + 6));
- store_reg_to_var_flt(iptr->dst, d);
- i386_ffree_reg(cd, 0);
- i386_fincstp(cd);
- fpu_st_offset--;
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+/* emit_fxch(cd); */
+ emit_fprem(cd);
+ emit_wait(cd);
+ emit_fnstsw(cd);
+ emit_sahf(cd);
+ emit_jcc(cd, CC_P, -(2 + 1 + 2 + 1 + 6));
+ emit_store_dst(jd, iptr, d);
+ emit_ffree_reg(cd, 0);
+ emit_fincstp(cd);
break;
case ICMD_DREM: /* ..., val1, val2 ==> ..., val1 % val2 */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- FPU_SET_53BIT_MODE;
/* exchanged to skip fxch */
- var_to_reg_flt(s2, src, REG_FTMP2);
- var_to_reg_flt(s1, src->prev, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
-/* i386_fxch(cd); */
- i386_fprem(cd);
- i386_wait(cd);
- i386_fnstsw(cd);
- i386_sahf(cd);
- i386_jcc(cd, I386_CC_P, -(2 + 1 + 2 + 1 + 6));
- store_reg_to_var_flt(iptr->dst, d);
- i386_ffree_reg(cd, 0);
- i386_fincstp(cd);
- fpu_st_offset--;
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+/* emit_fxch(cd); */
+ emit_fprem(cd);
+ emit_wait(cd);
+ emit_fnstsw(cd);
+ emit_sahf(cd);
+ emit_jcc(cd, CC_P, -(2 + 1 + 2 + 1 + 6));
+ emit_store_dst(jd, iptr, d);
+ emit_ffree_reg(cd, 0);
+ emit_fincstp(cd);
break;
case ICMD_I2F: /* ..., value ==> ..., (float) value */
case ICMD_I2D: /* ..., value ==> ..., (double) value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- if (src->flags & INMEMORY) {
- i386_fildl_membase(cd, REG_SP, src->regoff * 4);
- fpu_st_offset++;
+ var = VAROP(iptr->s1);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ if (var->flags & INMEMORY) {
+ emit_fildl_membase(cd, REG_SP, var->vv.regoff * 4);
} else {
- disp = dseg_adds4(cd, 0);
- i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(cd, cd->mcodeptr);
- i386_mov_reg_membase(cd, src->regoff, REG_ITMP1, disp);
- i386_fildl_membase(cd, REG_ITMP1, disp);
- fpu_st_offset++;
+ /* XXX not thread safe! */
+ disp = dseg_add_unique_s4(cd, 0);
+ emit_mov_imm_reg(cd, 0, REG_ITMP1);
+ dseg_adddata(cd);
+ emit_mov_reg_membase(cd, var->vv.regoff, REG_ITMP1, disp);
+ emit_fildl_membase(cd, REG_ITMP1, disp);
}
- store_reg_to_var_flt(iptr->dst, d);
+
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_L2F: /* ..., value ==> ..., (float) value */
case ICMD_L2D: /* ..., value ==> ..., (double) value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- if (src->flags & INMEMORY) {
- i386_fildll_membase(cd, REG_SP, src->regoff * 4);
- fpu_st_offset++;
+ var = VAROP(iptr->s1);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ if (var->flags & INMEMORY) {
+ emit_fildll_membase(cd, REG_SP, var->vv.regoff * 4);
} else {
log_text("L2F: longs have to be in memory");
assert(0);
}
- store_reg_to_var_flt(iptr->dst, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_F2I: /* ..., value ==> ..., (int) value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: D|YES ECX: NO EDX: NO OUTPUT: EAX*/
- var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_NULL);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_NULL);
- i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(cd, cd->mcodeptr);
+ emit_mov_imm_reg(cd, 0, REG_ITMP1);
+ dseg_adddata(cd);
/* Round to zero, 53-bit mode, exception masked */
- disp = dseg_adds4(cd, 0x0e7f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x0e7f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
+
+ var = VAROP(iptr->dst);
+ var1 = VAROP(iptr->s1);
- if (iptr->dst->flags & INMEMORY) {
- i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 4);
- fpu_st_offset--;
+ if (var->flags & INMEMORY) {
+ emit_fistpl_membase(cd, REG_SP, var->vv.regoff * 4);
/* Round to nearest, 53-bit mode, exceptions masked */
- disp = dseg_adds4(cd, 0x027f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x027f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4);
+ emit_alu_imm_membase(cd, ALU_CMP, 0x80000000,
+ REG_SP, var->vv.regoff * 4);
disp = 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var1->vv.regoff * 4);
disp += 5 + 2 + 3;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4);
} else {
- disp = dseg_adds4(cd, 0);
- i386_fistpl_membase(cd, REG_ITMP1, disp);
- fpu_st_offset--;
- i386_mov_membase_reg(cd, REG_ITMP1, disp, iptr->dst->regoff);
+ /* XXX not thread safe! */
+ disp = dseg_add_unique_s4(cd, 0);
+ emit_fistpl_membase(cd, REG_ITMP1, disp);
+ emit_mov_membase_reg(cd, REG_ITMP1, disp, var->vv.regoff);
/* Round to nearest, 53-bit mode, exceptions masked */
- disp = dseg_adds4(cd, 0x027f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x027f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, iptr->dst->regoff);
+ emit_alu_imm_reg(cd, ALU_CMP, 0x80000000, var->vv.regoff);
disp = 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- disp += 5 + 2 + ((REG_RESULT == iptr->dst->regoff) ? 0 : 2);
+ CALCOFFSETBYTES(disp, REG_SP, var1->vv.regoff * 4);
+ disp += 5 + 2 + ((REG_RESULT == var->vv.regoff) ? 0 : 2);
}
- i386_jcc(cd, I386_CC_NE, disp);
+ emit_jcc(cd, CC_NE, disp);
/* XXX: change this when we use registers */
- i386_flds_membase(cd, REG_SP, src->regoff * 4);
- i386_mov_imm_reg(cd, (ptrint) asm_builtin_f2i, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
+ emit_flds_membase(cd, REG_SP, var1->vv.regoff * 4);
+ emit_mov_imm_reg(cd, (ptrint) asm_builtin_f2i, REG_ITMP1);
+ emit_call_reg(cd, REG_ITMP1);
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
+ if (var->flags & INMEMORY) {
+ emit_mov_reg_membase(cd, REG_RESULT, REG_SP, var->vv.regoff * 4);
} else {
- M_INTMOVE(REG_RESULT, iptr->dst->regoff);
+ M_INTMOVE(REG_RESULT, var->vv.regoff);
}
break;
case ICMD_D2I: /* ..., value ==> ..., (int) value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: D|YES ECX: NO EDX: NO OUTPUT: EAX*/
- var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_NULL);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_NULL);
- i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(cd, cd->mcodeptr);
+ emit_mov_imm_reg(cd, 0, REG_ITMP1);
+ dseg_adddata(cd);
/* Round to zero, 53-bit mode, exception masked */
- disp = dseg_adds4(cd, 0x0e7f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x0e7f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
- if (iptr->dst->flags & INMEMORY) {
- i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 4);
- fpu_st_offset--;
+ var = VAROP(iptr->dst);
+ var1 = VAROP(iptr->s1);
+
+ if (var->flags & INMEMORY) {
+ emit_fistpl_membase(cd, REG_SP, var->vv.regoff * 4);
/* Round to nearest, 53-bit mode, exceptions masked */
- disp = dseg_adds4(cd, 0x027f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x027f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4);
+ emit_alu_imm_membase(cd, ALU_CMP, 0x80000000,
+ REG_SP, var->vv.regoff * 4);
disp = 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var1->vv.regoff * 4);
disp += 5 + 2 + 3;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4);
} else {
- disp = dseg_adds4(cd, 0);
- i386_fistpl_membase(cd, REG_ITMP1, disp);
- fpu_st_offset--;
- i386_mov_membase_reg(cd, REG_ITMP1, disp, iptr->dst->regoff);
+ /* XXX not thread safe! */
+ disp = dseg_add_unique_s4(cd, 0);
+ emit_fistpl_membase(cd, REG_ITMP1, disp);
+ emit_mov_membase_reg(cd, REG_ITMP1, disp, var->vv.regoff);
/* Round to nearest, 53-bit mode, exceptions masked */
- disp = dseg_adds4(cd, 0x027f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x027f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, iptr->dst->regoff);
+ emit_alu_imm_reg(cd, ALU_CMP, 0x80000000, var->vv.regoff);
disp = 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- disp += 5 + 2 + ((REG_RESULT == iptr->dst->regoff) ? 0 : 2);
+ CALCOFFSETBYTES(disp, REG_SP, var1->vv.regoff * 4);
+ disp += 5 + 2 + ((REG_RESULT == var->vv.regoff) ? 0 : 2);
}
- i386_jcc(cd, I386_CC_NE, disp);
+ emit_jcc(cd, CC_NE, disp);
/* XXX: change this when we use registers */
- i386_fldl_membase(cd, REG_SP, src->regoff * 4);
- i386_mov_imm_reg(cd, (ptrint) asm_builtin_d2i, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
+ emit_fldl_membase(cd, REG_SP, var1->vv.regoff * 4);
+ emit_mov_imm_reg(cd, (ptrint) asm_builtin_d2i, REG_ITMP1);
+ emit_call_reg(cd, REG_ITMP1);
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
+ if (var->flags & INMEMORY) {
+ emit_mov_reg_membase(cd, REG_RESULT, REG_SP, var->vv.regoff * 4);
} else {
- M_INTMOVE(REG_RESULT, iptr->dst->regoff);
+ M_INTMOVE(REG_RESULT, var->vv.regoff);
}
break;
case ICMD_F2L: /* ..., value ==> ..., (long) value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: YES OUTPUT: REG_NULL*/
- var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_NULL);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_NULL);
- i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(cd, cd->mcodeptr);
+ emit_mov_imm_reg(cd, 0, REG_ITMP1);
+ dseg_adddata(cd);
/* Round to zero, 53-bit mode, exception masked */
- disp = dseg_adds4(cd, 0x0e7f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x0e7f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
+
+ var = VAROP(iptr->dst);
+ var1 = VAROP(iptr->s1);
- if (iptr->dst->flags & INMEMORY) {
- i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 4);
- fpu_st_offset--;
+ if (var->flags & INMEMORY) {
+ emit_fistpll_membase(cd, REG_SP, var->vv.regoff * 4);
/* Round to nearest, 53-bit mode, exceptions masked */
- disp = dseg_adds4(cd, 0x027f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x027f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4 + 4);
+ emit_alu_imm_membase(cd, ALU_CMP, 0x80000000,
+ REG_SP, var->vv.regoff * 4 + 4);
disp = 6 + 4;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4);
disp += 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var1->vv.regoff * 4);
disp += 5 + 2;
disp += 3;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4);
disp += 3;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4 + 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4 + 4);
- i386_jcc(cd, I386_CC_NE, disp);
+ emit_jcc(cd, CC_NE, disp);
- i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->dst->regoff * 4);
+ emit_alu_imm_membase(cd, ALU_CMP, 0,
+ REG_SP, var->vv.regoff * 4);
disp = 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var1->vv.regoff * 4);
disp += 5 + 2 + 3;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4);
- i386_jcc(cd, I386_CC_NE, disp);
+ emit_jcc(cd, CC_NE, disp);
/* XXX: change this when we use registers */
- i386_flds_membase(cd, REG_SP, src->regoff * 4);
- i386_mov_imm_reg(cd, (ptrint) asm_builtin_f2l, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4);
+ emit_flds_membase(cd, REG_SP, var1->vv.regoff * 4);
+ emit_mov_imm_reg(cd, (ptrint) asm_builtin_f2l, REG_ITMP1);
+ emit_call_reg(cd, REG_ITMP1);
+ emit_mov_reg_membase(cd, REG_RESULT, REG_SP, var->vv.regoff * 4);
+ emit_mov_reg_membase(cd, REG_RESULT2,
+ REG_SP, var->vv.regoff * 4 + 4);
} else {
log_text("F2L: longs have to be in memory");
break;
case ICMD_D2L: /* ..., value ==> ..., (long) value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: YES OUTPUT: REG_NULL*/
- var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_NULL);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_NULL);
- i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(cd, cd->mcodeptr);
+ emit_mov_imm_reg(cd, 0, REG_ITMP1);
+ dseg_adddata(cd);
/* Round to zero, 53-bit mode, exception masked */
- disp = dseg_adds4(cd, 0x0e7f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x0e7f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
+
+ var = VAROP(iptr->dst);
+ var1 = VAROP(iptr->s1);
- if (iptr->dst->flags & INMEMORY) {
- i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 4);
- fpu_st_offset--;
+ if (var->flags & INMEMORY) {
+ emit_fistpll_membase(cd, REG_SP, var->vv.regoff * 4);
/* Round to nearest, 53-bit mode, exceptions masked */
- disp = dseg_adds4(cd, 0x027f);
- i386_fldcw_membase(cd, REG_ITMP1, disp);
+ disp = dseg_add_s4(cd, 0x027f);
+ emit_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4 + 4);
+ emit_alu_imm_membase(cd, ALU_CMP, 0x80000000,
+ REG_SP, var->vv.regoff * 4 + 4);
disp = 6 + 4;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4);
disp += 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var1->vv.regoff * 4);
disp += 5 + 2;
disp += 3;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4);
disp += 3;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4 + 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4 + 4);
- i386_jcc(cd, I386_CC_NE, disp);
+ emit_jcc(cd, CC_NE, disp);
- i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->dst->regoff * 4);
+ emit_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, var->vv.regoff * 4);
disp = 3;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var1->vv.regoff * 4);
disp += 5 + 2 + 3;
- CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, var->vv.regoff * 4);
- i386_jcc(cd, I386_CC_NE, disp);
+ emit_jcc(cd, CC_NE, disp);
/* XXX: change this when we use registers */
- i386_fldl_membase(cd, REG_SP, src->regoff * 4);
- i386_mov_imm_reg(cd, (ptrint) asm_builtin_d2l, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4);
+ emit_fldl_membase(cd, REG_SP, var1->vv.regoff * 4);
+ emit_mov_imm_reg(cd, (ptrint) asm_builtin_d2l, REG_ITMP1);
+ emit_call_reg(cd, REG_ITMP1);
+ emit_mov_reg_membase(cd, REG_RESULT, REG_SP, var->vv.regoff * 4);
+ emit_mov_reg_membase(cd, REG_RESULT2,
+ REG_SP, var->vv.regoff * 4 + 4);
} else {
log_text("D2L: longs have to be in memory");
break;
case ICMD_F2D: /* ..., value ==> ..., (double) value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
/* nothing to do */
- store_reg_to_var_flt(iptr->dst, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_D2F: /* ..., value ==> ..., (float) value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
- var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
/* nothing to do */
- store_reg_to_var_flt(iptr->dst, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_FCMPL: /* ..., val1, val2 ==> ..., val1 fcmpl val2 */
case ICMD_DCMPL:
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
/* exchanged to skip fxch */
- var_to_reg_flt(s2, src->prev, REG_FTMP1);
- var_to_reg_flt(s1, src, REG_FTMP2);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
-/* i386_fxch(cd); */
- i386_fucompp(cd);
- fpu_st_offset -= 2;
- i386_fnstsw(cd);
- i386_test_imm_reg(cd, 0x400, EAX); /* unordered treat as GT */
- i386_jcc(cd, I386_CC_E, 6);
- i386_alu_imm_reg(cd, ALU_AND, 0x000000ff, EAX);
- i386_sahf(cd);
- i386_mov_imm_reg(cd, 0, d); /* does not affect flags */
- i386_jcc(cd, I386_CC_E, 6 + 3 + 5 + 3);
- i386_jcc(cd, I386_CC_B, 3 + 5);
- i386_alu_imm_reg(cd, ALU_SUB, 1, d);
- i386_jmp_imm(cd, 3);
- i386_alu_imm_reg(cd, ALU_ADD, 1, d);
- store_reg_to_var_int(iptr->dst, d);
+ s2 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s1 = emit_load_s2(jd, iptr, REG_FTMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+/* emit_fxch(cd); */
+ emit_fucompp(cd);
+ emit_fnstsw(cd);
+ emit_test_imm_reg(cd, 0x400, EAX); /* unordered treat as GT */
+ emit_jcc(cd, CC_E, 6);
+ emit_alu_imm_reg(cd, ALU_AND, 0x000000ff, EAX);
+ emit_sahf(cd);
+ emit_mov_imm_reg(cd, 0, d); /* does not affect flags */
+ emit_jcc(cd, CC_E, 6 + 3 + 5 + 3);
+ emit_jcc(cd, CC_B, 3 + 5);
+ emit_alu_imm_reg(cd, ALU_SUB, 1, d);
+ emit_jmp_imm(cd, 3);
+ emit_alu_imm_reg(cd, ALU_ADD, 1, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_FCMPG: /* ..., val1, val2 ==> ..., val1 fcmpg val2 */
case ICMD_DCMPG:
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
/* exchanged to skip fxch */
- var_to_reg_flt(s2, src->prev, REG_FTMP1);
- var_to_reg_flt(s1, src, REG_FTMP2);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
-/* i386_fxch(cd); */
- i386_fucompp(cd);
- fpu_st_offset -= 2;
- i386_fnstsw(cd);
- i386_test_imm_reg(cd, 0x400, EAX); /* unordered treat as LT */
- i386_jcc(cd, I386_CC_E, 3);
- i386_movb_imm_reg(cd, 1, REG_AH);
- i386_sahf(cd);
- i386_mov_imm_reg(cd, 0, d); /* does not affect flags */
- i386_jcc(cd, I386_CC_E, 6 + 3 + 5 + 3);
- i386_jcc(cd, I386_CC_B, 3 + 5);
- i386_alu_imm_reg(cd, ALU_SUB, 1, d);
- i386_jmp_imm(cd, 3);
- i386_alu_imm_reg(cd, ALU_ADD, 1, d);
- store_reg_to_var_int(iptr->dst, d);
+ s2 = emit_load_s1(jd, iptr, REG_FTMP1);
+ s1 = emit_load_s2(jd, iptr, REG_FTMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+/* emit_fxch(cd); */
+ emit_fucompp(cd);
+ emit_fnstsw(cd);
+ emit_test_imm_reg(cd, 0x400, EAX); /* unordered treat as LT */
+ emit_jcc(cd, CC_E, 3);
+ emit_movb_imm_reg(cd, 1, REG_AH);
+ emit_sahf(cd);
+ emit_mov_imm_reg(cd, 0, d); /* does not affect flags */
+ emit_jcc(cd, CC_E, 6 + 3 + 5 + 3);
+ emit_jcc(cd, CC_B, 3 + 5);
+ emit_alu_imm_reg(cd, ALU_SUB, 1, d);
+ emit_jmp_imm(cd, 3);
+ emit_alu_imm_reg(cd, ALU_ADD, 1, d);
+ emit_store_dst(jd, iptr, d);
break;
/* memory operations **************************************************/
case ICMD_ARRAYLENGTH: /* ..., arrayref ==> ..., length */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- gen_nullptr_check(s1);
- i386_mov_membase_reg(cd, s1, OFFSET(java_arrayheader, size), d);
- store_reg_to_var_int(iptr->dst, d);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ emit_nullpointer_check(cd, iptr, s1);
+ M_ILD(d, s1, OFFSET(java_arrayheader, size));
+ emit_store_dst(jd, iptr, d);
break;
- case ICMD_AALOAD: /* ..., arrayref, index ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_mov_memindex_reg(cd, OFFSET(java_objectarray, data[0]), s1, s2, 2, d);
- store_reg_to_var_int(iptr->dst, d);
+ case ICMD_BALOAD: /* ..., arrayref, index ==> ..., value */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_movsbl_memindex_reg(cd, OFFSET(java_bytearray, data[0]),
+ s1, s2, 0, d);
+ emit_store_dst(jd, iptr, d);
break;
- case ICMD_LALOAD: /* ..., arrayref, index ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(rd, iptr->dst, REG_ITMP3);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
-
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]), s1, s2, 3, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4);
- i386_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
- }
+ case ICMD_CALOAD: /* ..., arrayref, index ==> ..., value */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_movzwl_memindex_reg(cd, OFFSET(java_chararray, data[0]),
+ s1, s2, 1, d);
+ emit_store_dst(jd, iptr, d);
+ break;
+
+ case ICMD_SALOAD: /* ..., arrayref, index ==> ..., value */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_movswl_memindex_reg(cd, OFFSET(java_shortarray, data[0]),
+ s1, s2, 1, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_IALOAD: /* ..., arrayref, index ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_mov_memindex_reg(cd, OFFSET(java_intarray, data[0]), s1, s2, 2, d);
- store_reg_to_var_int(iptr->dst, d);
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_mov_memindex_reg(cd, OFFSET(java_intarray, data[0]),
+ s1, s2, 2, d);
+ emit_store_dst(jd, iptr, d);
+ break;
+
+ case ICMD_LALOAD: /* ..., arrayref, index ==> ..., value */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP3);
+ emit_array_checks(cd, iptr, s1, s2);
+
+ var = VAROP(iptr->dst);
+
+ assert(var->flags & INMEMORY);
+ emit_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]),
+ s1, s2, 3, REG_ITMP3);
+ emit_mov_reg_membase(cd, REG_ITMP3, REG_SP, var->vv.regoff * 4);
+ emit_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]) + 4,
+ s1, s2, 3, REG_ITMP3);
+ emit_mov_reg_membase(cd, REG_ITMP3, REG_SP, var->vv.regoff * 4 + 4);
break;
case ICMD_FALOAD: /* ..., arrayref, index ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_flds_memindex(cd, OFFSET(java_floatarray, data[0]), s1, s2, 2);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_flds_memindex(cd, OFFSET(java_floatarray, data[0]), s1, s2, 2);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_DALOAD: /* ..., arrayref, index ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(rd, iptr->dst, REG_FTMP3);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_fldl_memindex(cd, OFFSET(java_doublearray, data[0]), s1, s2, 3);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP3);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_fldl_memindex(cd, OFFSET(java_doublearray, data[0]), s1, s2,3);
+ emit_store_dst(jd, iptr, d);
break;
- case ICMD_CALOAD: /* ..., arrayref, index ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_movzwl_memindex_reg(cd, OFFSET(java_chararray, data[0]), s1, s2, 1, d);
- store_reg_to_var_int(iptr->dst, d);
- break;
+ case ICMD_AALOAD: /* ..., arrayref, index ==> ..., value */
- case ICMD_SALOAD: /* ..., arrayref, index ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_movswl_memindex_reg(cd, OFFSET(java_shortarray, data[0]), s1, s2, 1, d);
- store_reg_to_var_int(iptr->dst, d);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP1);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_mov_memindex_reg(cd, OFFSET(java_objectarray, data[0]),
+ s1, s2, 2, d);
+ emit_store_dst(jd, iptr, d);
break;
- case ICMD_BALOAD: /* ..., arrayref, index ==> ..., value */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
+
+ case ICMD_BASTORE: /* ..., arrayref, index, value ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ s3 = emit_load_s3(jd, iptr, REG_ITMP3);
+ if (s3 >= EBP) {
+ /* because EBP, ESI, EDI have no xH and xL nibbles */
+ M_INTMOVE(s3, REG_ITMP3);
+ s3 = REG_ITMP3;
}
- i386_movsbl_memindex_reg(cd, OFFSET(java_bytearray, data[0]), s1, s2, 0, d);
- store_reg_to_var_int(iptr->dst, d);
+ emit_movb_reg_memindex(cd, s3, OFFSET(java_bytearray, data[0]),
+ s1, s2, 0);
break;
+ case ICMD_CASTORE: /* ..., arrayref, index, value ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ s3 = emit_load_s3(jd, iptr, REG_ITMP3);
+ emit_movw_reg_memindex(cd, s3, OFFSET(java_chararray, data[0]),
+ s1, s2, 1);
+ break;
- case ICMD_LASTORE: /* ..., arrayref, index, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
+ case ICMD_SASTORE: /* ..., arrayref, index, value ==> ... */
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP3);
- i386_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0]), s1, s2, 3);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP3);
- i386_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ s3 = emit_load_s3(jd, iptr, REG_ITMP3);
+ emit_movw_reg_memindex(cd, s3, OFFSET(java_shortarray, data[0]),
+ s1, s2, 1);
break;
case ICMD_IASTORE: /* ..., arrayref, index, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- var_to_reg_int(s3, src, REG_ITMP3);
- i386_mov_reg_memindex(cd, s3, OFFSET(java_intarray, data[0]), s1, s2, 2);
- break;
- case ICMD_FASTORE: /* ..., arrayref, index, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- var_to_reg_flt(s3, src, REG_FTMP1);
- i386_fstps_memindex(cd, OFFSET(java_floatarray, data[0]), s1, s2, 2);
- fpu_st_offset--;
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ s3 = emit_load_s3(jd, iptr, REG_ITMP3);
+ emit_mov_reg_memindex(cd, s3, OFFSET(java_intarray, data[0]),
+ s1, s2, 2);
break;
- case ICMD_DASTORE: /* ..., arrayref, index, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- var_to_reg_flt(s3, src, REG_FTMP1);
- i386_fstpl_memindex(cd, OFFSET(java_doublearray, data[0]), s1, s2, 3);
- fpu_st_offset--;
- break;
+ case ICMD_LASTORE: /* ..., arrayref, index, value ==> ... */
- case ICMD_CASTORE: /* ..., arrayref, index, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- var_to_reg_int(s3, src, REG_ITMP3);
- i386_movw_reg_memindex(cd, s3, OFFSET(java_chararray, data[0]), s1, s2, 1);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+
+ var = VAROP(iptr->sx.s23.s3);
+
+ assert(var->flags & INMEMORY);
+ emit_mov_membase_reg(cd, REG_SP, var->vv.regoff * 4, REG_ITMP3);
+ emit_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0])
+ , s1, s2, 3);
+ emit_mov_membase_reg(cd, REG_SP, var->vv.regoff * 4 + 4, REG_ITMP3);
+ emit_mov_reg_memindex(cd, REG_ITMP3,
+ OFFSET(java_longarray, data[0]) + 4, s1, s2, 3);
break;
- case ICMD_SASTORE: /* ..., arrayref, index, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- var_to_reg_int(s3, src, REG_ITMP3);
- i386_movw_reg_memindex(cd, s3, OFFSET(java_shortarray, data[0]), s1, s2, 1);
+ case ICMD_FASTORE: /* ..., arrayref, index, value ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ s3 = emit_load_s3(jd, iptr, REG_FTMP1);
+ emit_fstps_memindex(cd, OFFSET(java_floatarray, data[0]), s1, s2,2);
break;
- case ICMD_BASTORE: /* ..., arrayref, index, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- var_to_reg_int(s3, src, REG_ITMP3);
- if (s3 >= EBP) { /* because EBP, ESI, EDI have no xH and xL nibbles */
- M_INTMOVE(s3, REG_ITMP3);
- s3 = REG_ITMP3;
- }
- i386_movb_reg_memindex(cd, s3, OFFSET(java_bytearray, data[0]), s1, s2, 0);
+ case ICMD_DASTORE: /* ..., arrayref, index, value ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ s3 = emit_load_s3(jd, iptr, REG_FTMP1);
+ emit_fstpl_memindex(cd, OFFSET(java_doublearray, data[0]),
+ s1, s2, 3);
break;
case ICMD_AASTORE: /* ..., arrayref, index, value ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- var_to_reg_int(s3, src, REG_ITMP3);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ s3 = emit_load_s3(jd, iptr, REG_ITMP3);
M_AST(s1, REG_SP, 0 * 4);
M_AST(s3, REG_SP, 1 * 4);
- M_MOV_IMM((ptrint) BUILTIN_canstore, REG_ITMP1);
+ M_MOV_IMM(BUILTIN_canstore, REG_ITMP1);
M_CALL(REG_ITMP1);
M_TEST(REG_RESULT);
M_BEQ(0);
- codegen_addxstorerefs(cd, cd->mcodeptr);
+ codegen_add_arraystoreexception_ref(cd);
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- var_to_reg_int(s3, src, REG_ITMP3);
- i386_mov_reg_memindex(cd, s3, OFFSET(java_objectarray, data[0]), s1, s2, 2);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ s3 = emit_load_s3(jd, iptr, REG_ITMP3);
+ emit_mov_reg_memindex(cd, s3, OFFSET(java_objectarray, data[0]),
+ s1, s2, 2);
break;
- case ICMD_IASTORECONST: /* ..., arrayref, index ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_mov_imm_memindex(cd, iptr->val.i, OFFSET(java_intarray, data[0]), s1, s2, 2);
+ case ICMD_BASTORECONST: /* ..., arrayref, index ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_movb_imm_memindex(cd, iptr->sx.s23.s3.constval,
+ OFFSET(java_bytearray, data[0]), s1, s2, 0);
break;
- case ICMD_LASTORECONST: /* ..., arrayref, index ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
+ case ICMD_CASTORECONST: /* ..., arrayref, index ==> ... */
- i386_mov_imm_memindex(cd, (u4) (iptr->val.l & 0x00000000ffffffff), OFFSET(java_longarray, data[0]), s1, s2, 3);
- i386_mov_imm_memindex(cd, (u4) (iptr->val.l >> 32), OFFSET(java_longarray, data[0]) + 4, s1, s2, 3);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_movw_imm_memindex(cd, iptr->sx.s23.s3.constval,
+ OFFSET(java_chararray, data[0]), s1, s2, 1);
break;
- case ICMD_AASTORECONST: /* ..., arrayref, index ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_mov_imm_memindex(cd, 0, OFFSET(java_objectarray, data[0]), s1, s2, 2);
+ case ICMD_SASTORECONST: /* ..., arrayref, index ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_movw_imm_memindex(cd, iptr->sx.s23.s3.constval,
+ OFFSET(java_shortarray, data[0]), s1, s2, 1);
break;
- case ICMD_BASTORECONST: /* ..., arrayref, index ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_movb_imm_memindex(cd, iptr->val.i, OFFSET(java_bytearray, data[0]), s1, s2, 0);
+ case ICMD_IASTORECONST: /* ..., arrayref, index ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_mov_imm_memindex(cd, iptr->sx.s23.s3.constval,
+ OFFSET(java_intarray, data[0]), s1, s2, 2);
break;
- case ICMD_CASTORECONST: /* ..., arrayref, index ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_movw_imm_memindex(cd, iptr->val.i, OFFSET(java_chararray, data[0]), s1, s2, 1);
+ case ICMD_LASTORECONST: /* ..., arrayref, index ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_mov_imm_memindex(cd,
+ (u4) (iptr->sx.s23.s3.constval & 0x00000000ffffffff),
+ OFFSET(java_longarray, data[0]), s1, s2, 3);
+ emit_mov_imm_memindex(cd,
+ ((s4)iptr->sx.s23.s3.constval) >> 31,
+ OFFSET(java_longarray, data[0]) + 4, s1, s2, 3);
break;
- case ICMD_SASTORECONST: /* ..., arrayref, index ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
-
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- i386_movw_imm_memindex(cd, iptr->val.i, OFFSET(java_shortarray, data[0]), s1, s2, 1);
+ case ICMD_AASTORECONST: /* ..., arrayref, index ==> ... */
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ emit_array_checks(cd, iptr, s1, s2);
+ emit_mov_imm_memindex(cd, 0,
+ OFFSET(java_objectarray, data[0]), s1, s2, 2);
break;
case ICMD_GETSTATIC: /* ... ==> ..., value */
- /* op1 = type, val.a = field address */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EAX*/
- if (iptr->val.a == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_get_putstatic,
- (unresolved_field *) iptr->target, 0);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ unresolved_field *uf = iptr->sx.s23.s3.uf;
+
+ fieldtype = uf->fieldref->parseddesc.fd->type;
+
+ codegen_addpatchref(cd, PATCHER_get_putstatic,
+ iptr->sx.s23.s3.uf, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
disp = 0;
- } else {
- fieldinfo *fi = iptr->val.a;
+ }
+ else {
+ fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field;
+
+ fieldtype = fi->type;
if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_clinit, fi->class, 0);
+ codegen_addpatchref(cd, PATCHER_clinit, fi->class, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
M_MOV_IMM(disp, REG_ITMP1);
- switch (iptr->op1) {
+ switch (fieldtype) {
case TYPE_INT:
case TYPE_ADR:
- d = reg_of_var(rd, iptr->dst, REG_ITMP2);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
M_ILD(d, REG_ITMP1, 0);
- store_reg_to_var_int(iptr->dst, d);
break;
case TYPE_LNG:
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- /* Using both REG_ITMP2 and REG_ITMP3 is faster
- than only using REG_ITMP2 alternating. */
- i386_mov_membase_reg(cd, REG_ITMP1, 0, REG_ITMP2);
- i386_mov_membase_reg(cd, REG_ITMP1, 4, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
- } else {
- log_text("GETSTATIC: longs have to be in memory");
- assert(0);
- }
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP23_PACKED);
+ M_LLD(d, REG_ITMP1, 0);
break;
case TYPE_FLT:
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- i386_flds_membase(cd, REG_ITMP1, 0);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ M_FLD(d, REG_ITMP1, 0);
break;
case TYPE_DBL:
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- i386_fldl_membase(cd, REG_ITMP1, 0);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ M_DLD(d, REG_ITMP1, 0);
break;
}
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_PUTSTATIC: /* ..., value ==> ... */
- /* op1 = type, val.a = field address */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
- if (iptr->val.a == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_get_putstatic,
- (unresolved_field *) iptr->target, 0);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ unresolved_field *uf = iptr->sx.s23.s3.uf;
+
+ fieldtype = uf->fieldref->parseddesc.fd->type;
+
+ codegen_addpatchref(cd, PATCHER_get_putstatic,
+ iptr->sx.s23.s3.uf, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
disp = 0;
- } else {
- fieldinfo *fi = iptr->val.a;
+ }
+ else {
+ fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field;
+
+ fieldtype = fi->type;
if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_clinit, fi->class, 0);
+ codegen_addpatchref(cd, PATCHER_clinit, fi->class, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
M_MOV_IMM(disp, REG_ITMP1);
- switch (iptr->op1) {
+ switch (fieldtype) {
case TYPE_INT:
case TYPE_ADR:
- var_to_reg_int(s2, src, REG_ITMP2);
- M_IST(s2, REG_ITMP1, 0);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP2);
+ M_IST(s1, REG_ITMP1, 0);
break;
case TYPE_LNG:
- if (src->flags & INMEMORY) {
- /* Using both REG_ITMP2 and REG_ITMP3 is faster
- than only using REG_ITMP2 alternating. */
- s2 = src->regoff;
-
- i386_mov_membase_reg(cd, REG_SP, s2 * 4, REG_ITMP2);
- i386_mov_membase_reg(cd, REG_SP, s2 * 4 + 4, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_ITMP1, 0);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_ITMP1, 4);
- } else {
- log_text("PUTSTATIC: longs have to be in memory");
- assert(0);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP23_PACKED);
+ M_LST(s1, REG_ITMP1, 0);
break;
case TYPE_FLT:
- var_to_reg_flt(s2, src, REG_FTMP1);
- i386_fstps_membase(cd, REG_ITMP1, 0);
- fpu_st_offset--;
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ emit_fstps_membase(cd, REG_ITMP1, 0);
break;
case TYPE_DBL:
- var_to_reg_flt(s2, src, REG_FTMP1);
- i386_fstpl_membase(cd, REG_ITMP1, 0);
- fpu_st_offset--;
+ s1 = emit_load_s1(jd, iptr, REG_FTMP1);
+ emit_fstpl_membase(cd, REG_ITMP1, 0);
break;
}
break;
case ICMD_PUTSTATICCONST: /* ... ==> ... */
/* val = value (in current instruction) */
- /* op1 = type, val.a = field address (in */
/* following NOP) */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
- if (iptr[1].val.a == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_get_putstatic,
- (unresolved_field *) iptr[1].target, 0);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ unresolved_field *uf = iptr->sx.s23.s3.uf;
+
+ fieldtype = uf->fieldref->parseddesc.fd->type;
+
+ codegen_addpatchref(cd, PATCHER_get_putstatic,
+ uf, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
disp = 0;
- } else {
- fieldinfo *fi = iptr[1].val.a;
+ }
+ else {
+ fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field;
+
+ fieldtype = fi->type;
if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_clinit, fi->class, 0);
+ codegen_addpatchref(cd, PATCHER_clinit, fi->class, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
M_MOV_IMM(disp, REG_ITMP1);
- switch (iptr[1].op1) {
+ switch (fieldtype) {
case TYPE_INT:
- case TYPE_FLT:
case TYPE_ADR:
- i386_mov_imm_membase(cd, iptr->val.i, REG_ITMP1, 0);
+ M_IST_IMM(iptr->sx.s23.s2.constval, REG_ITMP1, 0);
break;
case TYPE_LNG:
- case TYPE_DBL:
- i386_mov_imm_membase(cd, iptr->val.l, REG_ITMP1, 0);
- i386_mov_imm_membase(cd, iptr->val.l >> 32, REG_ITMP1, 4);
+ M_IST_IMM(iptr->sx.s23.s2.constval & 0xffffffff, REG_ITMP1, 0);
+ M_IST_IMM(((s4)iptr->sx.s23.s2.constval) >> 31, REG_ITMP1, 4);
break;
+ default:
+ assert(0);
}
break;
case ICMD_GETFIELD: /* .., objectref. ==> ..., value */
- /* op1 = type, val.i = field offset */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */
- var_to_reg_int(s1, src, REG_ITMP1);
- gen_nullptr_check(s1);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ emit_nullpointer_check(cd, iptr, s1);
+
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ unresolved_field *uf = iptr->sx.s23.s3.uf;
- if (iptr->val.a == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_getfield,
- (unresolved_field *) iptr->target, 0);
+ fieldtype = uf->fieldref->parseddesc.fd->type;
+
+ codegen_addpatchref(cd, PATCHER_getfield,
+ iptr->sx.s23.s3.uf, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
disp = 0;
- } else {
- disp = ((fieldinfo *) (iptr->val.a))->offset;
+ }
+ else {
+ fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field;
+
+ fieldtype = fi->type;
+ disp = fi->offset;
}
- switch (iptr->op1) {
+ switch (fieldtype) {
case TYPE_INT:
case TYPE_ADR:
- d = reg_of_var(rd, iptr->dst, REG_ITMP2);
- i386_mov_membase32_reg(cd, s1, disp, d);
- store_reg_to_var_int(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
+ M_ILD32(d, s1, disp);
break;
case TYPE_LNG:
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_mov_membase32_reg(cd, s1, disp, REG_ITMP2);
- i386_mov_membase32_reg(cd, s1, disp + 4, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP23_PACKED);
+ M_LLD32(d, s1, disp);
break;
case TYPE_FLT:
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- i386_flds_membase32(cd, s1, disp);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ M_FLD32(d, s1, disp);
break;
case TYPE_DBL:
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- i386_fldl_membase32(cd, s1, disp);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
+ d = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+ M_DLD32(d, s1, disp);
break;
}
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_PUTFIELD: /* ..., objectref, value ==> ... */
- /* op1 = type, val.a = field address */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- gen_nullptr_check(s1);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ emit_nullpointer_check(cd, iptr, s1);
+
+ /* must be done here because of code patching */
- if ((iptr->op1 == TYPE_INT) || IS_ADR_TYPE(iptr->op1)) {
- var_to_reg_int(s2, src, REG_ITMP2);
- } else if (IS_FLT_DBL_TYPE(iptr->op1)) {
- var_to_reg_flt(s2, src, REG_FTMP2);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ unresolved_field *uf = iptr->sx.s23.s3.uf;
+
+ fieldtype = uf->fieldref->parseddesc.fd->type;
+ }
+ else {
+ fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field;
+
+ fieldtype = fi->type;
}
- if (iptr->val.a == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_putfield,
- (unresolved_field *) iptr->target, 0);
+ if (!IS_FLT_DBL_TYPE(fieldtype)) {
+ if (IS_2_WORD_TYPE(fieldtype))
+ s2 = emit_load_s2(jd, iptr, REG_ITMP23_PACKED);
+ else
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ }
+ else
+ s2 = emit_load_s2(jd, iptr, REG_FTMP2);
+
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ unresolved_field *uf = iptr->sx.s23.s3.uf;
+
+ codegen_addpatchref(cd, PATCHER_putfield, uf, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
disp = 0;
- } else {
- disp = ((fieldinfo *) (iptr->val.a))->offset;
+ }
+ else {
+ fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field;
+
+ disp = fi->offset;
}
- switch (iptr->op1) {
+ switch (fieldtype) {
case TYPE_INT:
case TYPE_ADR:
- i386_mov_reg_membase32(cd, s2, s1, disp);
+ M_IST32(s2, s1, disp);
break;
case TYPE_LNG:
- if (src->flags & INMEMORY) {
- i386_mov_membase32_reg(cd, REG_SP, src->regoff * 4, REG_ITMP2);
- i386_mov_membase32_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP3);
- i386_mov_reg_membase32(cd, REG_ITMP2, s1, disp);
- i386_mov_reg_membase32(cd, REG_ITMP3, s1, disp + 4);
- } else {
- log_text("PUTFIELD: longs have to be in memory");
- assert(0);
- }
+ M_LST32(s2, s1, disp);
break;
case TYPE_FLT:
- i386_fstps_membase32(cd, s1, disp);
- fpu_st_offset--;
+ emit_fstps_membase32(cd, s1, disp);
break;
case TYPE_DBL:
- i386_fstpl_membase32(cd, s1, disp);
- fpu_st_offset--;
+ emit_fstpl_membase32(cd, s1, disp);
break;
}
break;
case ICMD_PUTFIELDCONST: /* ..., objectref ==> ... */
/* val = value (in current instruction) */
- /* op1 = type, val.a = field address (in */
/* following NOP) */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
- var_to_reg_int(s1, src, REG_ITMP1);
- gen_nullptr_check(s1);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ emit_nullpointer_check(cd, iptr, s1);
+
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ unresolved_field *uf = iptr->sx.s23.s3.uf;
- if (iptr[1].val.a == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_putfieldconst,
- (unresolved_field *) iptr[1].target, 0);
+ fieldtype = uf->fieldref->parseddesc.fd->type;
+
+ codegen_addpatchref(cd, PATCHER_putfieldconst,
+ uf, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
disp = 0;
- } else {
- disp = ((fieldinfo *) (iptr[1].val.a))->offset;
+ }
+ else
+ {
+ fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field;
+
+ fieldtype = fi->type;
+ disp = fi->offset;
}
- switch (iptr[1].op1) {
+
+ switch (fieldtype) {
case TYPE_INT:
- case TYPE_FLT:
case TYPE_ADR:
- i386_mov_imm_membase32(cd, iptr->val.i, s1, disp);
+ M_IST32_IMM(iptr->sx.s23.s2.constval, s1, disp);
break;
case TYPE_LNG:
- case TYPE_DBL:
- i386_mov_imm_membase32(cd, iptr->val.l, s1, disp);
- i386_mov_imm_membase32(cd, iptr->val.l >> 32, s1, disp + 4);
+ M_IST32_IMM(iptr->sx.s23.s2.constval & 0xffffffff, s1, disp);
+ M_IST32_IMM(((s4)iptr->sx.s23.s2.constval) >> 31, s1, disp + 4);
break;
+ default:
+ assert(0);
}
break;
/* branch operations **************************************************/
case ICMD_ATHROW: /* ..., objectref ==> ... (, objectref) */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */
- var_to_reg_int(s1, src, REG_ITMP1);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
M_INTMOVE(s1, REG_ITMP1_XPTR);
#ifdef ENABLE_VERIFIER
- if (iptr->val.a) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_athrow_areturn,
- (unresolved_class *) iptr->val.a, 0);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ codegen_addpatchref(cd, PATCHER_athrow_areturn,
+ iptr->sx.s23.s2.uc, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
M_CALL_IMM(0); /* passing exception pc */
M_POP(REG_ITMP2_XPC);
- M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
+ M_MOV_IMM(asm_handle_exception, REG_ITMP3);
M_JMP(REG_ITMP3);
break;
- case ICMD_INLINE_GOTO:
- M_COPY(src,iptr->dst);
- /* FALLTHROUGH! */
case ICMD_GOTO: /* ... ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
+ case ICMD_RET: /* ... ==> ... */
- i386_jmp_imm(cd, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+#if defined(ENABLE_SSA)
+ if ( ls != NULL ) {
+ last_cmd_was_goto = true;
+ /* In case of a Goto phimoves have to be inserted before the */
+ /* jump */
+ codegen_insert_phi_moves(jd, bptr);
+ }
+#endif
+ M_JMP_IMM(0);
+ codegen_addreference(cd, iptr->dst.block);
+ ALIGNCODENOP;
break;
case ICMD_JSR: /* ... ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- i386_call_imm(cd, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ M_JMP_IMM(0);
+ codegen_addreference(cd, iptr->sx.s23.s3.jsrtarget.block);
break;
- case ICMD_RET: /* ... ==> ... */
- /* op1 = local variable */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- var = &(rd->locals[iptr->op1][TYPE_ADR]);
- var_to_reg_int(s1, var, REG_ITMP1);
- i386_jmp_reg(cd, s1);
- break;
-
case ICMD_IFNULL: /* ..., value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4);
- } else {
- i386_test_reg_reg(cd, src->regoff, src->regoff);
- }
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ M_TEST(s1);
+ M_BEQ(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IFNONNULL: /* ..., value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4);
- } else {
- i386_test_reg_reg(cd, src->regoff, src->regoff);
- }
- i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ M_TEST(s1);
+ M_BNE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IFEQ: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
-
- } else {
- i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
- }
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ M_CMP_IMM(iptr->sx.val.i, s1);
+ M_BEQ(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IFLT: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
-
- } else {
- i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
- }
- i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ M_CMP_IMM(iptr->sx.val.i, s1);
+ M_BLT(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IFLE: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
- } else {
- i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
- }
- i386_jcc(cd, I386_CC_LE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ M_CMP_IMM(iptr->sx.val.i, s1);
+ M_BLE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IFNE: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
- } else {
- i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
- }
- i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ M_CMP_IMM(iptr->sx.val.i, s1);
+ M_BNE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IFGT: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
-
- } else {
- i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
- }
- i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ M_CMP_IMM(iptr->sx.val.i, s1);
+ M_BGT(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IFGE: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
-
- } else {
- i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
- }
- i386_jcc(cd, I386_CC_GE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ M_CMP_IMM(iptr->sx.val.i, s1);
+ M_BGE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LEQ: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if (src->flags & INMEMORY) {
- if (iptr->val.l == 0) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_OR, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
- i386_alu_imm_reg(cd, ALU_XOR, iptr->val.l >> 32, REG_ITMP2);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_imm_reg(cd, ALU_XOR, iptr->val.l, REG_ITMP1);
- i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ if (iptr->sx.val.l == 0) {
+ M_INTMOVE(GET_LOW_REG(s1), REG_ITMP1);
+ M_OR(GET_HIGH_REG(s1), REG_ITMP1);
+ }
+ else {
+ M_LNGMOVE(s1, REG_ITMP12_PACKED);
+ M_XOR_IMM(iptr->sx.val.l, REG_ITMP1);
+ M_XOR_IMM(iptr->sx.val.l >> 32, REG_ITMP2);
+ M_OR(REG_ITMP2, REG_ITMP1);
}
- i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ M_BEQ(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LLT: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4);
- i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
-
- disp = 3 + 6;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- CALCIMMEDIATEBYTES(disp, iptr->val.l);
-
- i386_jcc(cd, I386_CC_G, disp);
-
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4);
- i386_jcc(cd, I386_CC_B, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ if (iptr->sx.val.l == 0) {
+ /* If high 32-bit are less than zero, then the 64-bits
+ are too. */
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ M_CMP_IMM(0, s1);
+ M_BLT(0);
+ }
+ else {
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ M_CMP_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(s1));
+ M_BLT(0);
+ codegen_addreference(cd, iptr->dst.block);
+ M_BGT(6 + 6);
+ M_CMP_IMM32(iptr->sx.val.l, GET_LOW_REG(s1));
+ M_BB(0);
}
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LLE: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4);
- i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
-
- disp = 3 + 6;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- CALCIMMEDIATEBYTES(disp, iptr->val.l);
-
- i386_jcc(cd, I386_CC_G, disp);
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4);
- i386_jcc(cd, I386_CC_BE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ M_CMP_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(s1));
+ M_BLT(0);
+ codegen_addreference(cd, iptr->dst.block);
+ M_BGT(6 + 6);
+ M_CMP_IMM32(iptr->sx.val.l, GET_LOW_REG(s1));
+ M_BBE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LNE: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if (src->flags & INMEMORY) {
- if (iptr->val.l == 0) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_OR, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- } else {
- i386_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_imm_reg(cd, iptr->val.l >> 32, REG_ITMP2);
- i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
- i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ if (iptr->sx.val.l == 0) {
+ M_INTMOVE(GET_LOW_REG(s1), REG_ITMP1);
+ M_OR(GET_HIGH_REG(s1), REG_ITMP1);
}
- i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
- i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ else {
+ M_LNGMOVE(s1, REG_ITMP12_PACKED);
+ M_XOR_IMM(iptr->sx.val.l, REG_ITMP1);
+ M_XOR_IMM(iptr->sx.val.l >> 32, REG_ITMP2);
+ M_OR(REG_ITMP2, REG_ITMP1);
+ }
+ M_BNE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LGT: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4);
- i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
-
- disp = 3 + 6;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- CALCIMMEDIATEBYTES(disp, iptr->val.l);
- i386_jcc(cd, I386_CC_L, disp);
-
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4);
- i386_jcc(cd, I386_CC_A, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ M_CMP_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(s1));
+ M_BGT(0);
+ codegen_addreference(cd, iptr->dst.block);
+ M_BLT(6 + 6);
+ M_CMP_IMM32(iptr->sx.val.l, GET_LOW_REG(s1));
+ M_BA(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LGE: /* ..., value ==> ... */
- /* op1 = target JavaVM pc, val.l = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4);
- i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- disp = 3 + 6;
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- CALCIMMEDIATEBYTES(disp, iptr->val.l);
-
- i386_jcc(cd, I386_CC_L, disp);
-
- i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4);
- i386_jcc(cd, I386_CC_AE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- }
+ if (iptr->sx.val.l == 0) {
+ /* If high 32-bit are greater equal zero, then the
+ 64-bits are too. */
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ M_CMP_IMM(0, s1);
+ M_BGE(0);
+ }
+ else {
+ s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED);
+ M_CMP_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(s1));
+ M_BGT(0);
+ codegen_addreference(cd, iptr->dst.block);
+ M_BLT(6 + 6);
+ M_CMP_IMM32(iptr->sx.val.l, GET_LOW_REG(s1));
+ M_BAE(0);
+ }
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_ICMPEQ: /* ..., value, value ==> ... */
case ICMD_IF_ACMPEQ: /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
-
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
-
- } else {
- i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
- }
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
+ M_BEQ(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LCMPEQ: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2);
- i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
- i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1);
- i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
- }
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ M_INTMOVE(s1, REG_ITMP1);
+ M_XOR(s2, REG_ITMP1);
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP3);
+ M_INTMOVE(s1, REG_ITMP2);
+ M_XOR(s2, REG_ITMP2);
+ M_OR(REG_ITMP1, REG_ITMP2);
+ M_BEQ(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_ICMPNE: /* ..., value, value ==> ... */
case ICMD_IF_ACMPNE: /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
-
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
- } else {
- i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
- }
- i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
+ M_BNE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LCMPNE: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2);
- i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
- i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1);
- i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
- }
- i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ M_INTMOVE(s1, REG_ITMP1);
+ M_XOR(s2, REG_ITMP1);
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP2);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP3);
+ M_INTMOVE(s1, REG_ITMP2);
+ M_XOR(s2, REG_ITMP2);
+ M_OR(REG_ITMP1, REG_ITMP2);
+ M_BNE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_ICMPLT: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
-
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
-
- } else {
- i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
- }
- i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
+ M_BLT(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LCMPLT: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- M_BLT(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
-
- disp = 3 + 3 + 6;
- CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4);
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- M_BGT(disp);
-
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_jcc(cd, I386_CC_B, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- }
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
+ M_BLT(0);
+ codegen_addreference(cd, iptr->dst.block);
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ M_BGT(2 + 6);
+ M_CMP(s2, s1);
+ M_BB(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_ICMPGT: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
-
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
-
- } else {
- i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
M_BGT(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LCMPGT: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- M_BGT(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
-
- disp = 3 + 3 + 6;
- CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4);
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- M_BLT(disp);
-
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_jcc(cd, I386_CC_A, 0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- }
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
+ M_BGT(0);
+ codegen_addreference(cd, iptr->dst.block);
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ M_BLT(2 + 6);
+ M_CMP(s2, s1);
+ M_BA(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_ICMPLE: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
-
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
- } else {
- i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
M_BLE(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LCMPLE: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- M_BLT(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- disp = 3 + 3 + 6;
- CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4);
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
-
- M_BGT(disp);
-
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1);
- M_BBE(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- }
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
+ M_BLT(0);
+ codegen_addreference(cd, iptr->dst.block);
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ M_BGT(2 + 6);
+ M_CMP(s2, s1);
+ M_BBE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_ICMPGE: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
- } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
-
- } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
-
- } else {
- i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
- }
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
M_BGE(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IF_LCMPGE: /* ..., value, value ==> ... */
- /* op1 = target JavaVM pc */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
- M_BGT(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
-
- disp = 3 + 3 + 6;
- CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4);
- CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
-
- M_BLT(disp);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
- i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1);
- M_BAE(0);
- codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- }
- break;
-
- /* (value xx 0) ? IFxx_ICONST : ELSE_ICONST */
-
- case ICMD_ELSE_ICONST: /* handled by IFxx_ICONST */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- break;
-
- case ICMD_IFEQ_ICONST: /* ..., value ==> ..., constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ifcc_iconst(cd, I386_CC_NE, src, iptr);
- break;
-
- case ICMD_IFNE_ICONST: /* ..., value ==> ..., constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ifcc_iconst(cd, I386_CC_E, src, iptr);
- break;
-
- case ICMD_IFLT_ICONST: /* ..., value ==> ..., constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ifcc_iconst(cd, I386_CC_GE, src, iptr);
- break;
-
- case ICMD_IFGE_ICONST: /* ..., value ==> ..., constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ifcc_iconst(cd, I386_CC_L, src, iptr);
- break;
-
- case ICMD_IFGT_ICONST: /* ..., value ==> ..., constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ifcc_iconst(cd, I386_CC_LE, src, iptr);
- break;
-
- case ICMD_IFLE_ICONST: /* ..., value ==> ..., constant */
- /* val.i = constant */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ifcc_iconst(cd, I386_CC_G, src, iptr);
+ s1 = emit_load_s1_high(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_high(jd, iptr, REG_ITMP2);
+ M_CMP(s2, s1);
+ M_BGT(0);
+ codegen_addreference(cd, iptr->dst.block);
+ s1 = emit_load_s1_low(jd, iptr, REG_ITMP1);
+ s2 = emit_load_s2_low(jd, iptr, REG_ITMP2);
+ M_BLT(2 + 6);
+ M_CMP(s2, s1);
+ M_BAE(0);
+ codegen_addreference(cd, iptr->dst.block);
break;
case ICMD_IRETURN: /* ..., retvalue ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */
- var_to_reg_int(s1, src, REG_RESULT);
+ REPLACEMENT_POINT_RETURN(cd, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_RESULT);
M_INTMOVE(s1, REG_RESULT);
goto nowperformreturn;
case ICMD_LRETURN: /* ..., retvalue ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_RESULT);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_RESULT2);
-
- } else {
- log_text("LRETURN: longs have to be in memory");
- assert(0);
- }
+ REPLACEMENT_POINT_RETURN(cd, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_RESULT_PACKED);
+ M_LNGMOVE(s1, REG_RESULT_PACKED);
goto nowperformreturn;
case ICMD_ARETURN: /* ..., retvalue ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */
- var_to_reg_int(s1, src, REG_RESULT);
+ REPLACEMENT_POINT_RETURN(cd, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_RESULT);
M_INTMOVE(s1, REG_RESULT);
#ifdef ENABLE_VERIFIER
- if (iptr->val.a) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_athrow_areturn,
- (unresolved_class *) iptr->val.a, 0);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ codegen_addpatchref(cd, PATCHER_athrow_areturn,
+ iptr->sx.s23.s2.uc, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
case ICMD_FRETURN: /* ..., retvalue ==> ... */
case ICMD_DRETURN:
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */
- var_to_reg_flt(s1, src, REG_FRESULT);
- /* this may be an early return -- keep the offset correct for the
- remaining code */
- fpu_st_offset--;
+ REPLACEMENT_POINT_RETURN(cd, iptr);
+ s1 = emit_load_s1(jd, iptr, REG_FRESULT);
goto nowperformreturn;
case ICMD_RETURN: /* ... ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
+
+ REPLACEMENT_POINT_RETURN(cd, iptr);
nowperformreturn:
{
s4 i, p;
- p = parentargs_base;
+ p = cd->stackframesize;
- /* call trace function */
- if (opt_verbosecall) {
- i386_alu_imm_reg(cd, ALU_SUB, 4 + 8 + 8 + 4, REG_SP);
-
- i386_mov_imm_membase(cd, (s4) m, REG_SP, 0);
-
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, 4);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, 4 + 4);
-
- i386_fstl_membase(cd, REG_SP, 4 + 8);
- i386_fsts_membase(cd, REG_SP, 4 + 8 + 8);
-
- i386_mov_imm_reg(cd, (s4) builtin_displaymethodstop, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
-
- i386_mov_membase_reg(cd, REG_SP, 4, REG_RESULT);
- i386_mov_membase_reg(cd, REG_SP, 4 + 4, REG_RESULT2);
-
- i386_alu_imm_reg(cd, ALU_ADD, 4 + 8 + 8 + 4, REG_SP);
- }
+#if !defined(NDEBUG)
+ emit_verbosecall_exit(jd);
+#endif
-#if defined(USE_THREADS)
+#if defined(ENABLE_THREADS)
if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
M_ALD(REG_ITMP2, REG_SP, rd->memuse * 4);
break;
case ICMD_LRETURN:
- M_IST(REG_RESULT, REG_SP, rd->memuse * 4);
- M_IST(REG_RESULT2, REG_SP, rd->memuse * 4 + 4);
+ M_LST(REG_RESULT_PACKED, REG_SP, rd->memuse * 4);
break;
case ICMD_FRETURN:
- i386_fstps_membase(cd, REG_SP, rd->memuse * 4);
+ emit_fstps_membase(cd, REG_SP, rd->memuse * 4);
break;
case ICMD_DRETURN:
- i386_fstpl_membase(cd, REG_SP, rd->memuse * 4);
+ emit_fstpl_membase(cd, REG_SP, rd->memuse * 4);
break;
}
M_AST(REG_ITMP2, REG_SP, 0);
- M_MOV_IMM((ptrint) BUILTIN_monitorexit, REG_ITMP1);
- M_CALL(REG_ITMP1);
+ M_MOV_IMM(LOCK_monitor_exit, REG_ITMP3);
+ M_CALL(REG_ITMP3);
/* and now restore the proper return value */
switch (iptr->opc) {
break;
case ICMD_LRETURN:
- M_ILD(REG_RESULT, REG_SP, rd->memuse * 4);
- M_ILD(REG_RESULT2, REG_SP, rd->memuse * 4 + 4);
+ M_LLD(REG_RESULT_PACKED, REG_SP, rd->memuse * 4);
break;
case ICMD_FRETURN:
- i386_flds_membase(cd, REG_SP, rd->memuse * 4);
+ emit_flds_membase(cd, REG_SP, rd->memuse * 4);
break;
case ICMD_DRETURN:
- i386_fldl_membase(cd, REG_SP, rd->memuse * 4);
+ emit_fldl_membase(cd, REG_SP, rd->memuse * 4);
break;
}
}
for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
p--;
- i386_fldl_membase(cd, REG_SP, p * 4);
- fpu_st_offset++;
+ emit_fldl_membase(cd, REG_SP, p * 4);
if (iptr->opc == ICMD_FRETURN || iptr->opc == ICMD_DRETURN) {
- i386_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset + 1);
+ assert(0);
+/* emit_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset + 1); */
} else {
- i386_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset);
+ assert(0);
+/* emit_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset); */
}
- fpu_st_offset--;
}
/* deallocate stack */
- if (parentargs_base)
- M_AADD_IMM(parentargs_base * 4, REG_SP);
+ if (cd->stackframesize)
+ M_AADD_IMM(cd->stackframesize * 4, REG_SP);
- i386_ret(cd);
+ emit_ret(cd);
}
break;
case ICMD_TABLESWITCH: /* ..., index ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
{
- s4 i, l, *s4ptr;
- void **tptr;
+ s4 i, l;
+ branch_target_t *table;
- tptr = (void **) iptr->target;
+ table = iptr->dst.table;
- s4ptr = iptr->val.a;
- l = s4ptr[1]; /* low */
- i = s4ptr[2]; /* high */
+ l = iptr->sx.s23.s2.tablelow;
+ i = iptr->sx.s23.s3.tablehigh;
- var_to_reg_int(s1, src, REG_ITMP1);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
M_INTMOVE(s1, REG_ITMP1);
- if (l != 0) {
- i386_alu_imm_reg(cd, ALU_SUB, l, REG_ITMP1);
- }
+
+ if (l != 0)
+ M_ISUB_IMM(l, REG_ITMP1);
+
i = i - l + 1;
/* range check */
+ M_CMP_IMM(i - 1, REG_ITMP1);
+ M_BA(0);
- i386_alu_imm_reg(cd, ALU_CMP, i - 1, REG_ITMP1);
- i386_jcc(cd, I386_CC_A, 0);
-
- codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
+ codegen_addreference(cd, table[0].block); /* default target */
/* build jump table top down and use address of lowest entry */
- tptr += i;
+ table += i;
while (--i >= 0) {
- dseg_addtarget(cd, (basicblock *) tptr[0]);
- --tptr;
+ dseg_add_target(cd, table->block);
+ --table;
}
- /* length of dataseg after last dseg_addtarget is used by load */
+ /* length of dataseg after last dseg_addtarget is used
+ by load */
- i386_mov_imm_reg(cd, 0, REG_ITMP2);
- dseg_adddata(cd, cd->mcodeptr);
- i386_mov_memindex_reg(cd, -(cd->dseglen), REG_ITMP2, REG_ITMP1, 2, REG_ITMP1);
- i386_jmp_reg(cd, REG_ITMP1);
+ M_MOV_IMM(0, REG_ITMP2);
+ dseg_adddata(cd);
+ emit_mov_memindex_reg(cd, -(cd->dseglen), REG_ITMP2, REG_ITMP1, 2, REG_ITMP1);
+ M_JMP(REG_ITMP1);
}
break;
case ICMD_LOOKUPSWITCH: /* ..., key ==> ... */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
{
- s4 i, l, val, *s4ptr;
- void **tptr;
+ s4 i;
+ lookup_target_t *lookup;
- tptr = (void **) iptr->target;
+ lookup = iptr->dst.lookup;
- s4ptr = iptr->val.a;
- l = s4ptr[0]; /* default */
- i = s4ptr[1]; /* count */
+ i = iptr->sx.s23.s2.lookupcount;
MCODECHECK((i<<2)+8);
- var_to_reg_int(s1, src, REG_ITMP1); /* reg compare should always be faster */
- while (--i >= 0) {
- s4ptr += 2;
- ++tptr;
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
- val = s4ptr[0];
- i386_alu_imm_reg(cd, ALU_CMP, val, s1);
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
+ while (--i >= 0) {
+ M_CMP_IMM(lookup->value, s1);
+ M_BEQ(0);
+ codegen_addreference(cd, lookup->target.block);
+ lookup++;
}
- i386_jmp_imm(cd, 0);
+ M_JMP_IMM(0);
- tptr = (void **) iptr->target;
- codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
+ codegen_addreference(cd, iptr->sx.s23.s3.lookupdefault.block);
}
break;
case ICMD_BUILTIN: /* ..., [arg1, [arg2 ...]] ==> ... */
- /* op1 = arg count val.a = builtintable entry */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX*/
- bte = iptr->val.a;
+ bte = iptr->sx.s23.s3.bte;
md = bte->md;
goto gen_method;
case ICMD_INVOKESTATIC: /* ..., [arg1, [arg2 ...]] ==> ... */
- /* op1 = arg count, val.a = method pointer */
case ICMD_INVOKESPECIAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */
case ICMD_INVOKEVIRTUAL:/* op1 = arg count, val.a = method pointer */
case ICMD_INVOKEINTERFACE:
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX */
+ REPLACEMENT_POINT_INVOKE(cd, iptr);
- lm = iptr->val.a;
-
- if (lm == NULL) {
- unresolved_method *um = iptr->target;
- md = um->methodref->parseddesc.md;
- } else {
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ md = iptr->sx.s23.s3.um->methodref->parseddesc.md;
+ lm = NULL;
+ }
+ else {
+ lm = iptr->sx.s23.s3.fmiref->p.method;
md = lm->parseddesc;
}
/* copy arguments to registers or stack location */
- for (s3 = s3 - 1; s3 >= 0; s3--, src = src->prev) {
- if (src->varkind == ARGVAR)
+ for (s3 = s3 - 1; s3 >= 0; s3--) {
+ var = VAR(iptr->sx.s23.s2.args[s3]);
+
+ /* Already Preallocated (ARGVAR) ? */
+ if (var->flags & PREALLOC)
continue;
- if (IS_INT_LNG_TYPE(src->type)) {
+ if (IS_INT_LNG_TYPE(var->type)) {
if (!md->params[s3].inmemory) {
log_text("No integer argument registers available!");
assert(0);
- } else {
- if (!IS_2_WORD_TYPE(src->type)) {
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(
- cd, REG_SP, src->regoff * 4, REG_ITMP1);
- i386_mov_reg_membase(
- cd, REG_ITMP1, REG_SP,
- md->params[s3].regoff * 4);
- } else {
- i386_mov_reg_membase(
- cd, src->regoff, REG_SP,
- md->params[s3].regoff * 4);
- }
+ } else {
+ if (IS_2_WORD_TYPE(var->type)) {
+ d = emit_load(jd, iptr, var, REG_ITMP12_PACKED);
+ M_LST(d, REG_SP, md->params[s3].regoff * 4);
} else {
- if (src->flags & INMEMORY) {
- M_LNGMEMMOVE(
- src->regoff, md->params[s3].regoff);
- } else {
- log_text("copy arguments: longs have to be in memory");
- assert(0);
- }
+ d = emit_load(jd, iptr, var, REG_ITMP1);
+ M_IST(d, REG_SP, md->params[s3].regoff * 4);
}
}
+
} else {
if (!md->params[s3].inmemory) {
- log_text("No float argument registers available!");
- assert(0);
- } else {
- var_to_reg_flt(d, src, REG_FTMP1);
- if (src->type == TYPE_FLT) {
- i386_fstps_membase(
- cd, REG_SP, md->params[s3].regoff * 4);
+ s1 = rd->argfltregs[md->params[s3].regoff];
+ d = emit_load(jd, iptr, var, s1);
+ M_FLTMOVE(d, s1);
- } else {
- i386_fstpl_membase(
- cd, REG_SP, md->params[s3].regoff * 4);
- }
+ } else {
+ d = emit_load(jd, iptr, var, REG_FTMP1);
+ if (IS_2_WORD_TYPE(var->type))
+ M_DST(d, REG_SP, md->params[s3].regoff * 4);
+ else
+ M_FST(d, REG_SP, md->params[s3].regoff * 4);
}
}
} /* end of for */
M_MOV_IMM(disp, REG_ITMP1);
M_CALL(REG_ITMP1);
- /* if op1 == true, we need to check for an exception */
- if (iptr->op1 == true) {
+ if (INSTRUCTION_MUST_CHECK(iptr)) {
M_TEST(REG_RESULT);
M_BEQ(0);
- codegen_addxexceptionrefs(cd, cd->mcodeptr);
+ codegen_add_fillinstacktrace_ref(cd);
}
break;
case ICMD_INVOKESPECIAL:
- i386_mov_membase_reg(cd, REG_SP, 0, REG_ITMP1);
- gen_nullptr_check(REG_ITMP1);
-
- /* access memory for hardware nullptr */
- i386_mov_membase_reg(cd, REG_ITMP1, 0, REG_ITMP1);
+ M_ALD(REG_ITMP1, REG_SP, 0);
+ M_TEST(REG_ITMP1);
+ M_BEQ(0);
+ codegen_add_nullpointerexception_ref(cd);
/* fall through */
case ICMD_INVOKESTATIC:
if (lm == NULL) {
- unresolved_method *um = iptr->target;
+ unresolved_method *um = iptr->sx.s23.s3.um;
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_invokestatic_special, um, 0);
+ codegen_addpatchref(cd, PATCHER_invokestatic_special,
+ um, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
disp = 0;
d = md->returntype.type;
-
- } else {
+ }
+ else {
disp = (ptrint) lm->stubroutine;
d = lm->parseddesc->returntype.type;
}
case ICMD_INVOKEVIRTUAL:
M_ALD(REG_ITMP1, REG_SP, 0 * 4);
- gen_nullptr_check(REG_ITMP1);
+ emit_nullpointer_check(cd, iptr, s1);
if (lm == NULL) {
- unresolved_method *um = iptr->target;
+ unresolved_method *um = iptr->sx.s23.s3.um;
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_invokevirtual, um, 0);
+ codegen_addpatchref(cd, PATCHER_invokevirtual, um, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
s1 = 0;
d = md->returntype.type;
-
- } else {
+ }
+ else {
s1 = OFFSET(vftbl_t, table[0]) +
sizeof(methodptr) * lm->vftblindex;
d = md->returntype.type;
}
- M_ALD(REG_ITMP2, REG_ITMP1, OFFSET(java_objectheader, vftbl));
- i386_mov_membase32_reg(cd, REG_ITMP2, s1, REG_ITMP1);
- M_CALL(REG_ITMP1);
+ M_ALD(REG_METHODPTR, REG_ITMP1,
+ OFFSET(java_objectheader, vftbl));
+ M_ALD32(REG_ITMP3, REG_METHODPTR, s1);
+ M_CALL(REG_ITMP3);
break;
case ICMD_INVOKEINTERFACE:
M_ALD(REG_ITMP1, REG_SP, 0 * 4);
- gen_nullptr_check(REG_ITMP1);
+ emit_nullpointer_check(cd, iptr, s1);
if (lm == NULL) {
- unresolved_method *um = iptr->target;
+ unresolved_method *um = iptr->sx.s23.s3.um;
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_invokeinterface, um, 0);
+ codegen_addpatchref(cd, PATCHER_invokeinterface, um, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
s1 = 0;
s2 = 0;
d = md->returntype.type;
-
- } else {
+ }
+ else {
s1 = OFFSET(vftbl_t, interfacetable[0]) -
sizeof(methodptr) * lm->class->index;
d = md->returntype.type;
}
- M_ALD(REG_ITMP1, REG_ITMP1, OFFSET(java_objectheader, vftbl));
- i386_mov_membase32_reg(cd, REG_ITMP1, s1, REG_ITMP2);
- i386_mov_membase32_reg(cd, REG_ITMP2, s2, REG_ITMP1);
- M_CALL(REG_ITMP1);
+ M_ALD(REG_METHODPTR, REG_ITMP1,
+ OFFSET(java_objectheader, vftbl));
+ M_ALD32(REG_METHODPTR, REG_METHODPTR, s1);
+ M_ALD32(REG_ITMP3, REG_METHODPTR, s2);
+ M_CALL(REG_ITMP3);
break;
}
+ /* store size of call code in replacement point */
+
+ REPLACEMENT_POINT_INVOKE_RETURN(cd, iptr);
+
/* d contains return type */
if (d != TYPE_VOID) {
- d = reg_of_var(rd, iptr->dst, REG_NULL);
-
- if (IS_INT_LNG_TYPE(iptr->dst->type)) {
- if (IS_2_WORD_TYPE(iptr->dst->type)) {
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(
- cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
- i386_mov_reg_membase(
- cd, REG_RESULT2, REG_SP,
- iptr->dst->regoff * 4 + 4);
- } else {
- log_text("RETURN: longs have to be in memory");
- assert(0);
+#if defined(ENABLE_SSA)
+ if ((ls == NULL) || (!IS_TEMPVAR_INDEX(iptr->dst.varindex)) ||
+ (ls->lifetime[-iptr->dst.varindex-1].type != -1))
+ /* a "living" stackslot */
+#endif
+ {
+ if (IS_INT_LNG_TYPE(d)) {
+ if (IS_2_WORD_TYPE(d)) {
+ s1 = codegen_reg_of_dst(jd, iptr, REG_RESULT_PACKED);
+ M_LNGMOVE(REG_RESULT_PACKED, s1);
}
-
- } else {
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
-
- } else {
- M_INTMOVE(REG_RESULT, iptr->dst->regoff);
+ else {
+ s1 = codegen_reg_of_dst(jd, iptr, REG_RESULT);
+ M_INTMOVE(REG_RESULT, s1);
}
}
-
- } else {
- /* fld from called function -- has other fpu_st_offset counter */
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
+ else {
+ s1 = codegen_reg_of_dst(jd, iptr, REG_NULL);
+ }
+ emit_store_dst(jd, iptr, s1);
}
}
break;
case ICMD_CHECKCAST: /* ..., objectref ==> ..., objectref */
- /* op1: 0 == array, 1 == class */
/* val.a: (classinfo*) superclass */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: YES ECX: I|YES EDX: I|YES OUTPUT: REG_NULL */
-
/* superclass is an interface:
*
* OK if ((sub == NULL) ||
* super->vftbl->diffval));
*/
- if (iptr->op1 == 1) {
+ if (!(iptr->flags.bits & INS_FLAG_ARRAY)) {
/* object type cast-check */
classinfo *super;
vftbl_t *supervftbl;
s4 superindex;
- super = (classinfo *) iptr->val.a;
-
- if (!super) {
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ super = NULL;
superindex = 0;
supervftbl = NULL;
-
- } else {
+ }
+ else {
+ super = iptr->sx.s23.s3.c.cls;
superindex = super->index;
supervftbl = super->vftbl;
}
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+#if defined(ENABLE_THREADS)
codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase);
#endif
- var_to_reg_int(s1, src, REG_ITMP1);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
/* calculate interface checkcast code size */
s3 += 2 /* cmp */ + 6 /* jcc */;
- if (!super)
+ if (super == NULL)
s3 += (opt_showdisassemble ? 5 : 0);
/* if class is not resolved, check which code to call */
- if (!super) {
- i386_test_reg_reg(cd, s1, s1);
- i386_jcc(cd, I386_CC_Z, 5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3);
+ if (super == NULL) {
+ M_TEST(s1);
+ M_BEQ(5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3);
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_checkcast_instanceof_flags,
- (constant_classref *) iptr->target, 0);
+ codegen_addpatchref(cd, PATCHER_checkcast_instanceof_flags,
+ iptr->sx.s23.s3.c.ref, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
- i386_mov_imm_reg(cd, 0, REG_ITMP2); /* super->flags */
- i386_alu_imm_reg(cd, ALU_AND, ACC_INTERFACE, REG_ITMP2);
- i386_jcc(cd, I386_CC_Z, s2 + 5);
+ M_MOV_IMM(0, REG_ITMP2); /* super->flags */
+ M_AND_IMM32(ACC_INTERFACE, REG_ITMP2);
+ M_BEQ(s2 + 5);
}
/* interface checkcast code */
- if (!super || (super->flags & ACC_INTERFACE)) {
- if (super) {
- i386_test_reg_reg(cd, s1, s1);
- i386_jcc(cd, I386_CC_Z, s2);
+ if ((super == NULL) || (super->flags & ACC_INTERFACE)) {
+ if (super != NULL) {
+ M_TEST(s1);
+ M_BEQ(s2);
}
- i386_mov_membase_reg(cd, s1,
- OFFSET(java_objectheader, vftbl),
- REG_ITMP2);
+ M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
- if (!super) {
- codegen_addpatchref(cd, cd->mcodeptr,
+ if (super == NULL) {
+ codegen_addpatchref(cd,
PATCHER_checkcast_instanceof_interface,
- (constant_classref *) iptr->target, 0);
+ iptr->sx.s23.s3.c.ref,
+ 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
}
- i386_mov_membase32_reg(cd, REG_ITMP2,
- OFFSET(vftbl_t, interfacetablelength),
- REG_ITMP3);
- i386_alu_imm32_reg(cd, ALU_SUB, superindex, REG_ITMP3);
- i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3);
- i386_jcc(cd, I386_CC_LE, 0);
- codegen_addxcastrefs(cd, cd->mcodeptr);
- i386_mov_membase32_reg(cd, REG_ITMP2,
- OFFSET(vftbl_t, interfacetable[0]) -
- superindex * sizeof(methodptr*),
- REG_ITMP3);
- i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3);
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addxcastrefs(cd, cd->mcodeptr);
-
- if (!super)
- i386_jmp_imm(cd, s3);
+ M_ILD32(REG_ITMP3,
+ REG_ITMP2, OFFSET(vftbl_t, interfacetablelength));
+ M_ISUB_IMM32(superindex, REG_ITMP3);
+ M_TEST(REG_ITMP3);
+ M_BLE(0);
+ codegen_add_classcastexception_ref(cd, s1);
+ M_ALD32(REG_ITMP3, REG_ITMP2,
+ OFFSET(vftbl_t, interfacetable[0]) -
+ superindex * sizeof(methodptr*));
+ M_TEST(REG_ITMP3);
+ M_BEQ(0);
+ codegen_add_classcastexception_ref(cd, s1);
+
+ if (super == NULL)
+ M_JMP_IMM(s3);
}
/* class checkcast code */
- if (!super || !(super->flags & ACC_INTERFACE)) {
- if (super) {
- i386_test_reg_reg(cd, s1, s1);
- i386_jcc(cd, I386_CC_Z, s3);
+ if ((super == NULL) || !(super->flags & ACC_INTERFACE)) {
+ if (super != NULL) {
+ M_TEST(s1);
+ M_BEQ(s3);
}
- i386_mov_membase_reg(cd, s1,
- OFFSET(java_objectheader, vftbl),
- REG_ITMP2);
+ M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
- if (!super) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_checkcast_class,
- (constant_classref *) iptr->target, 0);
+ if (super == NULL) {
+ codegen_addpatchref(cd, PATCHER_checkcast_class,
+ iptr->sx.s23.s3.c.ref,
+ 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
}
- i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP3);
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+ M_MOV_IMM(supervftbl, REG_ITMP3);
+#if defined(ENABLE_THREADS)
codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase);
#endif
- i386_mov_membase32_reg(cd, REG_ITMP2,
- OFFSET(vftbl_t, baseval),
- REG_ITMP2);
+ M_ILD32(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, baseval));
/* if (s1 != REG_ITMP1) { */
- /* i386_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, baseval), REG_ITMP1); */
- /* i386_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, diffval), REG_ITMP3); */
- /* #if defined(USE_THREADS) && defined(NATIVE_THREADS) */
+ /* emit_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, baseval), REG_ITMP1); */
+ /* emit_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, diffval), REG_ITMP3); */
+ /* #if defined(ENABLE_THREADS) */
/* codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase); */
/* #endif */
- /* i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP1, REG_ITMP2); */
+ /* emit_alu_reg_reg(cd, ALU_SUB, REG_ITMP1, REG_ITMP2); */
/* } else { */
- i386_mov_membase32_reg(cd, REG_ITMP3,
- OFFSET(vftbl_t, baseval),
- REG_ITMP3);
- i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP3, REG_ITMP2);
- i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP3);
- i386_mov_membase_reg(cd, REG_ITMP3,
- OFFSET(vftbl_t, diffval),
- REG_ITMP3);
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+ M_ILD32(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, baseval));
+ M_ISUB(REG_ITMP3, REG_ITMP2);
+ M_MOV_IMM(supervftbl, REG_ITMP3);
+ M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, diffval));
+#if defined(ENABLE_THREADS)
codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
#endif
/* } */
- i386_alu_reg_reg(cd, ALU_CMP, REG_ITMP3, REG_ITMP2);
- i386_jcc(cd, I386_CC_A, 0); /* (u) REG_ITMP2 > (u) REG_ITMP3 -> jump */
- codegen_addxcastrefs(cd, cd->mcodeptr);
+ M_CMP(REG_ITMP3, REG_ITMP2);
+ M_BA(0); /* (u) REG_ITMP2 > (u) REG_ITMP3 -> jump */
+ codegen_add_classcastexception_ref(cd, s1);
}
- d = reg_of_var(rd, iptr->dst, REG_ITMP3);
- } else {
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP3);
+ }
+ else {
/* array type cast-check */
- var_to_reg_int(s1, src, REG_ITMP1);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP2);
M_AST(s1, REG_SP, 0 * 4);
- if (iptr->val.a == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_builtin_arraycheckcast,
- iptr->target, 0);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ codegen_addpatchref(cd, PATCHER_builtin_arraycheckcast,
+ iptr->sx.s23.s3.c.ref, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
}
- M_AST_IMM((ptrint) iptr->val.a, REG_SP, 1 * 4);
- M_MOV_IMM((ptrint) BUILTIN_arraycheckcast, REG_ITMP3);
+ M_AST_IMM(iptr->sx.s23.s3.c.cls, REG_SP, 1 * 4);
+ M_MOV_IMM(BUILTIN_arraycheckcast, REG_ITMP3);
M_CALL(REG_ITMP3);
+
+ s1 = emit_load_s1(jd, iptr, REG_ITMP2);
M_TEST(REG_RESULT);
M_BEQ(0);
- codegen_addxcastrefs(cd, cd->mcodeptr);
+ codegen_add_classcastexception_ref(cd, s1);
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, s1);
+ d = codegen_reg_of_dst(jd, iptr, s1);
}
+
M_INTMOVE(s1, d);
- store_reg_to_var_int(iptr->dst, d);
+ emit_store_dst(jd, iptr, d);
break;
case ICMD_INSTANCEOF: /* ..., objectref ==> ..., intresult */
-
- /* op1: 0 == array, 1 == class */
/* val.a: (classinfo*) superclass */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|D|YES ECX: YES S|D|EDX: S|D|YES OUTPUT: REG_NULL*/
- /* ????? Really necessary to block all ????? */
/* superclass is an interface:
*
vftbl_t *supervftbl;
s4 superindex;
- super = (classinfo *) iptr->val.a;
-
- if (!super) {
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ super = NULL;
superindex = 0;
supervftbl = NULL;
} else {
+ super = iptr->sx.s23.s3.c.cls;
superindex = super->index;
supervftbl = super->vftbl;
}
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+#if defined(ENABLE_THREADS)
codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase);
#endif
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_ITMP2);
+ s1 = emit_load_s1(jd, iptr, REG_ITMP1);
+ d = codegen_reg_of_dst(jd, iptr, REG_ITMP2);
if (s1 == d) {
M_INTMOVE(s1, REG_ITMP1);
s1 = REG_ITMP1;
if (!super)
s3 += (opt_showdisassemble ? 5 : 0);
- i386_alu_reg_reg(cd, ALU_XOR, d, d);
+ M_CLR(d);
/* if class is not resolved, check which code to call */
if (!super) {
- i386_test_reg_reg(cd, s1, s1);
- i386_jcc(cd, I386_CC_Z, 5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3);
+ M_TEST(s1);
+ M_BEQ(5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3);
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_checkcast_instanceof_flags,
- (constant_classref *) iptr->target, 0);
+ codegen_addpatchref(cd, PATCHER_checkcast_instanceof_flags,
+ iptr->sx.s23.s3.c.ref, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
- i386_mov_imm_reg(cd, 0, REG_ITMP3); /* super->flags */
- i386_alu_imm32_reg(cd, ALU_AND, ACC_INTERFACE, REG_ITMP3);
- i386_jcc(cd, I386_CC_Z, s2 + 5);
+ M_MOV_IMM(0, REG_ITMP3); /* super->flags */
+ M_AND_IMM32(ACC_INTERFACE, REG_ITMP3);
+ M_BEQ(s2 + 5);
}
/* interface instanceof code */
M_BEQ(s2);
}
- i386_mov_membase_reg(cd, s1,
- OFFSET(java_objectheader, vftbl),
- REG_ITMP1);
+ M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
if (!super) {
- codegen_addpatchref(cd, cd->mcodeptr,
+ codegen_addpatchref(cd,
PATCHER_checkcast_instanceof_interface,
- (constant_classref *) iptr->target, 0);
+ iptr->sx.s23.s3.c.ref, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
}
- i386_mov_membase32_reg(cd, REG_ITMP1,
- OFFSET(vftbl_t, interfacetablelength),
- REG_ITMP3);
- i386_alu_imm32_reg(cd, ALU_SUB, superindex, REG_ITMP3);
- i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3);
+ M_ILD32(REG_ITMP3,
+ REG_ITMP1, OFFSET(vftbl_t, interfacetablelength));
+ M_ISUB_IMM32(superindex, REG_ITMP3);
+ M_TEST(REG_ITMP3);
disp = (2 + 4 /* mov_membase32_reg */ + 2 /* test */ +
6 /* jcc */ + 5 /* mov_imm_reg */);
M_BLE(disp);
- i386_mov_membase32_reg(cd, REG_ITMP1,
- OFFSET(vftbl_t, interfacetable[0]) -
- superindex * sizeof(methodptr*),
- REG_ITMP1);
+ M_ALD32(REG_ITMP1, REG_ITMP1,
+ OFFSET(vftbl_t, interfacetable[0]) -
+ superindex * sizeof(methodptr*));
M_TEST(REG_ITMP1);
-/* i386_setcc_reg(cd, I386_CC_A, d); */
-/* i386_jcc(cd, I386_CC_BE, 5); */
+/* emit_setcc_reg(cd, CC_A, d); */
+/* emit_jcc(cd, CC_BE, 5); */
M_BEQ(5);
M_MOV_IMM(1, d);
M_BEQ(s3);
}
- i386_mov_membase_reg(cd, s1,
- OFFSET(java_objectheader, vftbl),
- REG_ITMP1);
+ M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
if (!super) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_instanceof_class,
- (constant_classref *) iptr->target, 0);
+ codegen_addpatchref(cd, PATCHER_instanceof_class,
+ iptr->sx.s23.s3.c.ref, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
}
- i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP2);
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+ M_MOV_IMM(supervftbl, REG_ITMP2);
+#if defined(ENABLE_THREADS)
codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase);
#endif
- i386_mov_membase_reg(cd, REG_ITMP1,
- OFFSET(vftbl_t, baseval),
- REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP2,
- OFFSET(vftbl_t, diffval),
- REG_ITMP3);
- i386_mov_membase_reg(cd, REG_ITMP2,
- OFFSET(vftbl_t, baseval),
- REG_ITMP2);
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+ M_ILD(REG_ITMP1, REG_ITMP1, OFFSET(vftbl_t, baseval));
+ M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, diffval));
+ M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, baseval));
+#if defined(ENABLE_THREADS)
codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
#endif
- i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP2, REG_ITMP1);
- i386_alu_reg_reg(cd, ALU_XOR, d, d); /* may be REG_ITMP2 */
- i386_alu_reg_reg(cd, ALU_CMP, REG_ITMP3, REG_ITMP1);
- i386_jcc(cd, I386_CC_A, 5);
- i386_mov_imm_reg(cd, 1, d);
+ M_ISUB(REG_ITMP2, REG_ITMP1);
+ M_CLR(d); /* may be REG_ITMP2 */
+ M_CMP(REG_ITMP3, REG_ITMP1);
+ M_BA(5);
+ M_MOV_IMM(1, d);
}
- store_reg_to_var_int(iptr->dst, d);
+ emit_store_dst(jd, iptr, d);
}
break;
break;
case ICMD_MULTIANEWARRAY:/* ..., cnt1, [cnt2, ...] ==> ..., arrayref */
- /* op1 = dimension, val.a = class */
- /* REG_RES Register usage: see icmd_uses_reg_res.inc */
- /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX */
/* check for negative sizes and copy sizes to stack if necessary */
- MCODECHECK((iptr->op1 << 1) + 64);
+ MCODECHECK((iptr->s1.argcount << 1) + 64);
- for (s1 = iptr->op1; --s1 >= 0; src = src->prev) {
+ for (s1 = iptr->s1.argcount; --s1 >= 0; ) {
/* copy SAVEDVAR sizes to stack */
+ var = VAR(iptr->sx.s23.s2.args[s1]);
- if (src->varkind != ARGVAR) {
- if (src->flags & INMEMORY) {
- M_ILD(REG_ITMP1, REG_SP, src->regoff * 4);
+ /* Already Preallocated? */
+ if (!(var->flags & PREALLOC)) {
+ if (var->flags & INMEMORY) {
+ M_ILD(REG_ITMP1, REG_SP, var->vv.regoff * 4);
M_IST(REG_ITMP1, REG_SP, (s1 + 3) * 4);
-
- } else {
- M_IST(src->regoff, REG_SP, (s1 + 3) * 4);
}
+ else
+ M_IST(var->vv.regoff, REG_SP, (s1 + 3) * 4);
}
}
/* is a patcher function set? */
- if (iptr->val.a == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr,
- PATCHER_builtin_multianewarray,
- (constant_classref *) iptr->target, 0);
+ if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
+ codegen_addpatchref(cd, PATCHER_builtin_multianewarray,
+ iptr->sx.s23.s3.c.ref, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
disp = 0;
- } else {
- disp = (ptrint) iptr->val.a;
}
+ else
+ disp = (ptrint) iptr->sx.s23.s3.c.cls;
/* a0 = dimension count */
- M_IST_IMM(iptr->op1, REG_SP, 0 * 4);
+ M_IST_IMM(iptr->s1.argcount, REG_SP, 0 * 4);
/* a1 = arraydescriptor */
M_AADD_IMM(3 * 4, REG_ITMP1);
M_AST(REG_ITMP1, REG_SP, 2 * 4);
- M_MOV_IMM((ptrint) BUILTIN_multianewarray, REG_ITMP1);
+ M_MOV_IMM(BUILTIN_multianewarray, REG_ITMP1);
M_CALL(REG_ITMP1);
/* check for exception before result assignment */
M_TEST(REG_RESULT);
M_BEQ(0);
- codegen_addxexceptionrefs(cd, cd->mcodeptr);
+ codegen_add_fillinstacktrace_ref(cd);
- s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
+ s1 = codegen_reg_of_dst(jd, iptr, REG_RESULT);
M_INTMOVE(REG_RESULT, s1);
- store_reg_to_var_int(iptr->dst, s1);
+ emit_store_dst(jd, iptr, s1);
break;
default:
} /* for instruction */
- /* copy values to interface registers */
+ MCODECHECK(64);
- src = bptr->outstack;
- len = bptr->outdepth;
- MCODECHECK(64+len);
-#if defined(ENABLE_LSRA)
+#if defined(ENABLE_LSRA) && !defined(ENABLE_SSA)
if (!opt_lsra)
#endif
- while (src) {
- len--;
- if ((src->varkind != STACKVAR)) {
- s2 = src->type;
- if (IS_FLT_DBL_TYPE(s2)) {
- var_to_reg_flt(s1, src, REG_FTMP1);
- if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
- M_FLTMOVE(s1, rd->interfaces[len][s2].regoff);
-
- } else {
- log_text("double store");
- assert(0);
-/* M_DST(s1, REG_SP, 4 * interfaces[len][s2].regoff); */
- }
-
- } else {
- var_to_reg_int(s1, src, REG_ITMP1);
- if (!IS_2_WORD_TYPE(rd->interfaces[len][s2].type)) {
- if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
- M_INTMOVE(s1, rd->interfaces[len][s2].regoff);
-
- } else {
- i386_mov_reg_membase(cd, s1, REG_SP, rd->interfaces[len][s2].regoff * 4);
- }
-
- } else {
- if (rd->interfaces[len][s2].flags & INMEMORY) {
- M_LNGMEMMOVE(s1, rd->interfaces[len][s2].regoff);
-
- } else {
- log_text("copy interface registers: longs have to be in memory (end)");
- assert(0);
- }
- }
- }
- }
- src = src->prev;
+#if defined(ENABLE_SSA)
+ if ( ls != NULL ) {
+ /* by edge splitting, in Blocks with phi moves there can only */
+ /* be a goto as last command, no other Jump/Branch Command */
+ if (!last_cmd_was_goto)
+ codegen_insert_phi_moves(jd, bptr);
}
+#endif
+
/* At the end of a basic block we may have to append some nops,
because the patcher stub calling code might be longer than the
actual instruction. So codepatching does not change the
dseg_createlinenumbertable(cd);
- {
-
- u1 *xcodeptr;
- branchref *bref;
-
- /* generate ArithmeticException stubs */
- xcodeptr = NULL;
-
- for (bref = cd->xdivrefs; bref != NULL; bref = bref->next) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- cd->mcodeptr - cd->mcodebase);
-
- MCODECHECK(512);
+ /* generate exception and patcher stubs */
- M_MOV_IMM(0, REG_ITMP2_XPC);
- dseg_adddata(cd, cd->mcodeptr);
- M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
+ emit_exception_stubs(jd);
+ emit_patcher_stubs(jd);
+ REPLACEMENT_EMIT_STUBS(jd);
- if (xcodeptr != NULL) {
- M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
-
- } else {
- xcodeptr = cd->mcodeptr;
+ codegen_finish(jd);
- M_ASUB_IMM(4 * 4, REG_SP);
+ /* everything's ok */
- M_AST_IMM(0, REG_SP, 0 * 4);
- dseg_adddata(cd, cd->mcodeptr);
- M_MOV(REG_SP, REG_ITMP3);
- M_AADD_IMM(4 * 4, REG_ITMP3);
- M_AST(REG_ITMP3, REG_SP, 1 * 4);
- M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
- M_AST(REG_ITMP3, REG_SP, 2 * 4);
- M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ return true;
+}
- M_MOV_IMM((ptrint) stacktrace_inline_arithmeticexception,
- REG_ITMP3);
- M_CALL(REG_ITMP3);
+#if defined(ENABLE_SSA)
+void codegen_insert_phi_moves(jitdata *jd, basicblock *bptr) {
+ /* look for phi moves */
+ int t_a,s_a,i, type;
+ int t_lt, s_lt; /* lifetime indices of phi_moves */
+ s4 t_regoff, s_regoff, s_flags, t_flags;
+ codegendata *cd;
+ lsradata *ls;
- M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
- M_AADD_IMM(4 * 4, REG_SP);
+ MCODECHECK(512);
- M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
- M_JMP(REG_ITMP3);
+ ls = jd->ls;
+ cd = jd->cd;
+
+ /* Moves from phi functions with highest indices have to be */
+ /* inserted first, since this is the order as is used for */
+ /* conflict resolution */
+ for(i = ls->num_phi_moves[bptr->nr] - 1; i >= 0 ; i--) {
+ t_a = ls->phi_moves[bptr->nr][i][0];
+ s_a = ls->phi_moves[bptr->nr][i][1];
+#if defined(SSA_DEBUG_VERBOSE)
+ if (compileverbose)
+ printf("BB %3i Move %3i <- %3i ", bptr->nr, t_a, s_a);
+#endif
+ if (t_a >= 0) {
+ /* local var lifetimes */
+ t_lt = ls->maxlifetimes + t_a;
+ type = ls->lifetime[t_lt].type;
}
- }
-
- /* generate ArrayIndexOutOfBoundsException stubs */
-
- xcodeptr = NULL;
-
- for (bref = cd->xboundrefs; bref != NULL; bref = bref->next) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- cd->mcodeptr - cd->mcodebase);
-
- MCODECHECK(512);
-
- /* move index register into REG_ITMP1 */
-
- M_INTMOVE(bref->reg, REG_ITMP1);
-
- M_MOV_IMM(0, REG_ITMP2_XPC);
- dseg_adddata(cd, cd->mcodeptr);
- M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
-
- if (xcodeptr != NULL) {
- M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
-
- } else {
- xcodeptr = cd->mcodeptr;
-
- M_ASUB_IMM(5 * 4, REG_SP);
-
- M_AST_IMM(0, REG_SP, 0 * 4);
- dseg_adddata(cd, cd->mcodeptr);
- M_MOV(REG_SP, REG_ITMP3);
- M_AADD_IMM(5 * 4, REG_ITMP3);
- M_AST(REG_ITMP3, REG_SP, 1 * 4);
- M_ALD(REG_ITMP3, REG_SP, (5 + parentargs_base) * 4);
- M_AST(REG_ITMP3, REG_SP, 2 * 4);
- M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
- M_AST(REG_ITMP1, REG_SP, 4 * 4); /* don't use REG_ITMP1 till here */
-
- M_MOV_IMM((ptrint) stacktrace_inline_arrayindexoutofboundsexception,
- REG_ITMP3);
- M_CALL(REG_ITMP3);
-
- M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
- M_AADD_IMM(5 * 4, REG_SP);
-
- M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
- M_JMP(REG_ITMP3);
+ else {
+ t_lt = -t_a-1;
+ type = ls->lifetime[t_lt].local_ss->s->type;
+ /* stackslot lifetime */
}
- }
-
- /* generate ArrayStoreException stubs */
-
- xcodeptr = NULL;
-
- for (bref = cd->xstorerefs; bref != NULL; bref = bref->next) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- cd->mcodeptr - cd->mcodebase);
-
- MCODECHECK(512);
-
- M_MOV_IMM(0, REG_ITMP2_XPC);
- dseg_adddata(cd, cd->mcodeptr);
- M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
-
- if (xcodeptr != NULL) {
- M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
-
- } else {
- xcodeptr = cd->mcodeptr;
-
- M_ASUB_IMM(4 * 4, REG_SP);
- M_AST_IMM(0, REG_SP, 0 * 4);
- dseg_adddata(cd, cd->mcodeptr);
- M_MOV(REG_SP, REG_ITMP3);
- M_AADD_IMM(4 * 4, REG_ITMP3);
- M_AST(REG_ITMP3, REG_SP, 1 * 4);
- M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
- M_AST(REG_ITMP3, REG_SP, 2 * 4);
- M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
-
- M_MOV_IMM((ptrint) stacktrace_inline_arraystoreexception,
- REG_ITMP3);
- M_CALL(REG_ITMP3);
-
- M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
- M_AADD_IMM(4 * 4, REG_SP);
-
- M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
- M_JMP(REG_ITMP3);
+ if (type == -1) {
+#if defined(SSA_DEBUG_VERBOSE)
+ if (compileverbose)
+ printf("...returning - phi lifetimes where joined\n");
+#endif
+ return;
}
- }
-
- /* generate ClassCastException stubs */
-
- xcodeptr = NULL;
-
- for (bref = cd->xcastrefs; bref != NULL; bref = bref->next) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- cd->mcodeptr - cd->mcodebase);
-
- MCODECHECK(512);
-
- M_MOV_IMM(0, REG_ITMP2_XPC);
- dseg_adddata(cd, cd->mcodeptr);
- M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
-
- if (xcodeptr != NULL) {
- M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
-
- } else {
- xcodeptr = cd->mcodeptr;
- M_ASUB_IMM(4 * 4, REG_SP);
-
- M_AST_IMM(0, REG_SP, 0 * 4);
- dseg_adddata(cd, cd->mcodeptr);
- M_MOV(REG_SP, REG_ITMP3);
- M_AADD_IMM(4 * 4, REG_ITMP3);
- M_AST(REG_ITMP3, REG_SP, 1 * 4);
- M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
- M_AST(REG_ITMP3, REG_SP, 2 * 4);
- M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
-
- M_MOV_IMM((ptrint) stacktrace_inline_classcastexception, REG_ITMP3);
- M_CALL(REG_ITMP3);
-
- M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
- M_AADD_IMM(4 * 4, REG_SP);
-
- M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
- M_JMP(REG_ITMP3);
+ if (s_a >= 0) {
+ /* local var lifetimes */
+ s_lt = ls->maxlifetimes + s_a;
+ type = ls->lifetime[s_lt].type;
+ }
+ else {
+ s_lt = -s_a-1;
+ type = ls->lifetime[s_lt].type;
+ /* stackslot lifetime */
}
- }
-
- /* generate NullPointerException stubs */
- xcodeptr = NULL;
-
- for (bref = cd->xnullrefs; bref != NULL; bref = bref->next) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- cd->mcodeptr - cd->mcodebase);
-
- MCODECHECK(512);
+ if (type == -1) {
+#if defined(SSA_DEBUG_VERBOSE)
+ if (compileverbose)
+ printf("...returning - phi lifetimes where joined\n");
+#endif
+ return;
+ }
- M_MOV_IMM(0, REG_ITMP2_XPC);
- dseg_adddata(cd, cd->mcodeptr);
- M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
-
- if (xcodeptr != NULL) {
- M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
-
- } else {
- xcodeptr = cd->mcodeptr;
+ if (t_a >= 0) {
+ t_flags = VAR(t_a)->flags;
+ t_regoff = VAR(t_a)->vv.regoff;
- M_ASUB_IMM(4 * 4, REG_SP);
-
- M_AST_IMM(0, REG_SP, 0 * 4);
- dseg_adddata(cd, cd->mcodeptr);
- M_MOV(REG_SP, REG_ITMP3);
- M_AADD_IMM(4 * 4, REG_ITMP3);
- M_AST(REG_ITMP3, REG_SP, 1 * 4);
- M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
- M_AST(REG_ITMP3, REG_SP, 2 * 4);
- M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
-
- M_MOV_IMM((ptrint) stacktrace_inline_nullpointerexception,
- REG_ITMP3);
- M_CALL(REG_ITMP3);
-
- M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
- M_AADD_IMM(4 * 4, REG_SP);
-
- M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
- M_JMP(REG_ITMP3);
}
- }
-
- /* generate exception check stubs */
-
- xcodeptr = NULL;
-
- for (bref = cd->xexceptionrefs; bref != NULL; bref = bref->next) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- cd->mcodeptr - cd->mcodebase);
-
- MCODECHECK(512);
-
- M_MOV_IMM(0, REG_ITMP2_XPC);
- dseg_adddata(cd, cd->mcodeptr);
- M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
+ else {
+ t_flags = ls->lifetime[t_lt].local_ss->s->flags;
+ t_regoff = ls->lifetime[t_lt].local_ss->s->regoff;
+ }
- if (xcodeptr != NULL) {
- M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
-
+ if (s_a >= 0) {
+ /* local var move */
+ s_flags = VAR(s_a)->flags;
+ s_regoff = VAR(s_a)->vv.regoff;
} else {
- xcodeptr = cd->mcodeptr;
-
- M_ASUB_IMM(4 * 4, REG_SP);
-
- M_AST_IMM(0, REG_SP, 0 * 4);
- dseg_adddata(cd, cd->mcodeptr);
- M_MOV(REG_SP, REG_ITMP3);
- M_AADD_IMM(4 * 4, REG_ITMP3);
- M_AST(REG_ITMP3, REG_SP, 1 * 4);
- M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
- M_AST(REG_ITMP3, REG_SP, 2 * 4);
- M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
-
- M_MOV_IMM((ptrint) stacktrace_inline_fillInStackTrace, REG_ITMP3);
- M_CALL(REG_ITMP3);
-
- M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
- M_AADD_IMM(4 * 4, REG_SP);
-
- M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
- M_JMP(REG_ITMP3);
+ /* stackslot lifetime */
+ s_flags = ls->lifetime[s_lt].local_ss->s->flags;
+ s_regoff = ls->lifetime[s_lt].local_ss->s->regoff;
}
- }
-
- /* generate code patching stub call code */
-
- {
- patchref *pref;
- codegendata *tmpcd;
- u8 mcode;
-
- tmpcd = DNEW(codegendata);
-
- for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
- /* check code segment size */
-
- MCODECHECK(512);
-
- /* Get machine code which is patched back in later. A */
- /* `call rel32' is 5 bytes long. */
-
- xcodeptr = cd->mcodebase + pref->branchpos;
- mcode = *((u8 *) xcodeptr);
-
- /* patch in `call rel32' to call the following code */
-
- tmpcd->mcodeptr = xcodeptr; /* set dummy mcode pointer */
- i386_call_imm(tmpcd, cd->mcodeptr - (xcodeptr + 5));
- /* move pointer to java_objectheader onto stack */
-
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- (void) dseg_addaddress(cd, get_dummyLR()); /* monitorPtr */
- off = dseg_addaddress(cd, NULL); /* vftbl */
-
- M_MOV_IMM(0, REG_ITMP3);
- dseg_adddata(cd, cd->mcodeptr);
- M_AADD_IMM(off, REG_ITMP3);
- M_PUSH(REG_ITMP3);
-#else
- M_PUSH_IMM(0);
+ if (type == -1) {
+#if defined(SSA_DEBUG_VERBOSE)
+ if (compileverbose)
+ printf("...returning - phi lifetimes where joined\n");
#endif
+ return;
+ }
- /* move machine code bytes and classinfo pointer into registers */
-
- M_PUSH_IMM((ptrint) (mcode >> 32));
- M_PUSH_IMM((ptrint) mcode);
- M_PUSH_IMM((ptrint) pref->ref);
- M_PUSH_IMM((ptrint) pref->patcher);
+ cg_move(cd, type, s_regoff, s_flags, t_regoff, t_flags);
- M_MOV_IMM((ptrint) asm_wrapper_patcher, REG_ITMP3);
- M_JMP(REG_ITMP3);
+#if defined(SSA_DEBUG_VERBOSE)
+ if (compileverbose) {
+ if (IS_INMEMORY(t_flags) && IS_INMEMORY(s_flags)) {
+ /* mem -> mem */
+ printf("M%3i <- M%3i",t_regoff,s_regoff);
+ }
+ else if (IS_INMEMORY(s_flags)) {
+ /* mem -> reg */
+ printf("R%3i <- M%3i",t_regoff,s_regoff);
+ }
+ else if (IS_INMEMORY(t_flags)) {
+ /* reg -> mem */
+ printf("M%3i <- R%3i",t_regoff,s_regoff);
+ }
+ else {
+ /* reg -> reg */
+ printf("R%3i <- R%3i",t_regoff,s_regoff);
+ }
+ printf("\n");
}
+#endif /* defined(SSA_DEBUG_VERBOSE) */
}
+}
- /* generate replacement-out stubs */
-
- {
- int i;
-
- replacementpoint = cd->code->rplpoints;
- for (i=0; i<cd->code->rplpointcount; ++i, ++replacementpoint) {
- /* check code segment size */
-
- MCODECHECK(512);
-
- /* note start of stub code */
-
- replacementpoint->outcode = (u1*) (ptrint)(cd->mcodeptr - cd->mcodebase);
-
- /* push address of `rplpoint` struct */
-
- M_PUSH_IMM((ptrint) replacementpoint);
-
- /* jump to replacement function */
-
- M_PUSH_IMM((ptrint) asm_replacement_out);
- M_RET;
+void cg_move(codegendata *cd, s4 type, s4 src_regoff, s4 src_flags,
+ s4 dst_regoff, s4 dst_flags) {
+ if ((IS_INMEMORY(dst_flags)) && (IS_INMEMORY(src_flags))) {
+ /* mem -> mem */
+ if (dst_regoff != src_regoff) {
+ if (!IS_2_WORD_TYPE(type)) {
+ if (IS_FLT_DBL_TYPE(type)) {
+ emit_flds_membase(cd, REG_SP, src_regoff * 4);
+ emit_fstps_membase(cd, REG_SP, dst_regoff * 4);
+ } else{
+ emit_mov_membase_reg(cd, REG_SP, src_regoff * 4,
+ REG_ITMP1);
+ emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, dst_regoff * 4);
+ }
+ } else { /* LONG OR DOUBLE */
+ if (IS_FLT_DBL_TYPE(type)) {
+ emit_fldl_membase( cd, REG_SP, src_regoff * 4);
+ emit_fstpl_membase(cd, REG_SP, dst_regoff * 4);
+ } else {
+ emit_mov_membase_reg(cd, REG_SP, src_regoff * 4,
+ REG_ITMP1);
+ emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, dst_regoff * 4);
+ emit_mov_membase_reg(cd, REG_SP, src_regoff * 4 + 4,
+ REG_ITMP1);
+ emit_mov_reg_membase(cd, REG_ITMP1, REG_SP,
+ dst_regoff * 4 + 4);
+ }
+ }
+ }
+ } else {
+ if (IS_FLT_DBL_TYPE(type)) {
+ log_text("cg_move: flt/dbl type have to be in memory\n");
+/* assert(0); */
+ }
+ if (IS_2_WORD_TYPE(type)) {
+ log_text("cg_move: longs have to be in memory\n");
+/* assert(0); */
+ }
+ if (IS_INMEMORY(src_flags)) {
+ /* mem -> reg */
+ emit_mov_membase_reg(cd, REG_SP, src_regoff * 4, dst_regoff);
+ } else if (IS_INMEMORY(dst_flags)) {
+ /* reg -> mem */
+ emit_mov_reg_membase(cd, src_regoff, REG_SP, dst_regoff * 4);
+ } else {
+ /* reg -> reg */
+ /* only ints can be in regs on i386 */
+ M_INTMOVE(src_regoff,dst_regoff);
}
}
- }
-
- codegen_finish(m, cd, (ptrint) (cd->mcodeptr - cd->mcodebase));
-
- /* everything's ok */
-
- return true;
}
-
+#endif /* defined(ENABLE_SSA) */
/* createcompilerstub **********************************************************
*******************************************************************************/
-#define COMPILERSTUB_DATASIZE 2 * SIZEOF_VOID_P
+#define COMPILERSTUB_DATASIZE 3 * SIZEOF_VOID_P
#define COMPILERSTUB_CODESIZE 12
#define COMPILERSTUB_SIZE COMPILERSTUB_DATASIZE + COMPILERSTUB_CODESIZE
cd = DNEW(codegendata);
cd->mcodeptr = s;
- /* Store the methodinfo* in the same place as in the methodheader
- for compiled methods. */
+ /* The codeinfo pointer is actually a pointer to the
+ methodinfo. This fakes a codeinfo structure. */
d[0] = (ptrint) asm_call_jit_compiler;
d[1] = (ptrint) m;
+ d[2] = (ptrint) &d[1]; /* fake code->m */
- M_MOV_IMM((ptrint) m, REG_ITMP1);
+ /* code for the stub */
- /* we use REG_ITMP3 cause ECX (REG_ITMP2) is used for patching */
- M_MOV_IMM((ptrint) asm_call_jit_compiler, REG_ITMP3);
+ M_MOV_IMM(m, REG_ITMP1); /* method info */
+ M_MOV_IMM(asm_call_jit_compiler, REG_ITMP3);
M_JMP(REG_ITMP3);
#if defined(ENABLE_STATISTICS)
*******************************************************************************/
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
-/* this way we can call the function directly with a memory call */
-
-static java_objectheader **(*callgetexceptionptrptr)() = builtin_get_exceptionptrptr;
-#endif
-
-u1 *createnativestub(functionptr f, methodinfo *m, codegendata *cd,
- registerdata *rd, methoddesc *nmd)
+u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd)
{
- methoddesc *md;
- s4 nativeparams;
- s4 stackframesize;
- s4 i, j; /* count variables */
- s4 t;
- s4 s1, s2, disp;
+ methodinfo *m;
+ codeinfo *code;
+ codegendata *cd;
+ registerdata *rd;
+ methoddesc *md;
+ s4 nativeparams;
+ s4 i, j; /* count variables */
+ s4 t;
+ s4 s1, s2;
+
+ /* get required compiler data */
+
+ m = jd->m;
+ code = jd->code;
+ cd = jd->cd;
+ rd = jd->rd;
/* set some variables */
/* calculate stackframe size */
- stackframesize =
+ cd->stackframesize =
sizeof(stackframeinfo) / SIZEOF_VOID_P +
sizeof(localref_table) / SIZEOF_VOID_P +
1 + /* function pointer */
4 * 4 + /* 4 arguments (start_native_call) */
nmd->memuse;
+ /* keep stack 16-byte aligned */
+
+ cd->stackframesize |= 0x3;
+
/* create method header */
- (void) dseg_addaddress(cd, m); /* MethodPointer */
- (void) dseg_adds4(cd, stackframesize * 4); /* FrameSize */
- (void) dseg_adds4(cd, 0); /* IsSync */
- (void) dseg_adds4(cd, 0); /* IsLeaf */
- (void) dseg_adds4(cd, 0); /* IntSave */
- (void) dseg_adds4(cd, 0); /* FltSave */
+ (void) dseg_add_unique_address(cd, code); /* CodeinfoPointer */
+ (void) dseg_add_unique_s4(cd, cd->stackframesize * 4); /* FrameSize */
+ (void) dseg_add_unique_s4(cd, 0); /* IsSync */
+ (void) dseg_add_unique_s4(cd, 0); /* IsLeaf */
+ (void) dseg_add_unique_s4(cd, 0); /* IntSave */
+ (void) dseg_add_unique_s4(cd, 0); /* FltSave */
(void) dseg_addlinenumbertablesize(cd);
- (void) dseg_adds4(cd, 0); /* ExTableSize */
-
- /* initialize mcode variables */
-
- cd->mcodeptr = (u1 *) cd->mcodebase;
- cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize);
+ (void) dseg_add_unique_s4(cd, 0); /* ExTableSize */
/* generate native method profiling code */
- if (opt_prof) {
+ if (JITDATA_HAS_FLAG_INSTRUMENT(jd)) {
/* count frequency */
- M_MOV_IMM((ptrint) m, REG_ITMP1);
- M_IADD_IMM_MEMBASE(1, REG_ITMP1, OFFSET(methodinfo, frequency));
+ M_MOV_IMM(code, REG_ITMP1);
+ M_IADD_IMM_MEMBASE(1, REG_ITMP1, OFFSET(codeinfo, frequency));
}
/* calculate stackframe size for native function */
- M_ASUB_IMM(stackframesize * 4, REG_SP);
-
- if (opt_verbosecall) {
- s4 p, t;
-
- disp = stackframesize * 4;
-
- M_ASUB_IMM(TRACE_ARGS_NUM * 8 + 4, REG_SP);
-
- for (p = 0; p < md->paramcount && p < TRACE_ARGS_NUM; p++) {
- t = md->paramtypes[p].type;
- if (IS_INT_LNG_TYPE(t)) {
- if (IS_2_WORD_TYPE(t)) {
- M_ILD(REG_ITMP1, REG_SP,
- 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
- M_ILD(REG_ITMP2, REG_SP,
- 4 + TRACE_ARGS_NUM * 8 + 4 + disp + 4);
- M_IST(REG_ITMP1, REG_SP, p * 8);
- M_IST(REG_ITMP2, REG_SP, p * 8 + 4);
-
- } else if (t == TYPE_ADR) {
- M_ALD(REG_ITMP1, REG_SP,
- 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
- M_CLR(REG_ITMP2);
- M_AST(REG_ITMP1, REG_SP, p * 8);
- M_AST(REG_ITMP2, REG_SP, p * 8 + 4);
-
- } else {
- M_ILD(EAX, REG_SP, 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
- i386_cltd(cd);
- M_IST(EAX, REG_SP, p * 8);
- M_IST(EDX, REG_SP, p * 8 + 4);
- }
-
- } else {
- if (!IS_2_WORD_TYPE(t)) {
- i386_flds_membase(cd, REG_SP,
- 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
- i386_fstps_membase(cd, REG_SP, p * 8);
- i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2);
- M_IST(REG_ITMP2, REG_SP, p * 8 + 4);
-
- } else {
- i386_fldl_membase(cd, REG_SP,
- 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
- i386_fstpl_membase(cd, REG_SP, p * 8);
- }
- }
- disp += (IS_2_WORD_TYPE(t)) ? 8 : 4;
- }
-
- M_CLR(REG_ITMP1);
- for (p = md->paramcount; p < TRACE_ARGS_NUM; p++) {
- M_IST(REG_ITMP1, REG_SP, p * 8);
- M_IST(REG_ITMP1, REG_SP, p * 8 + 4);
- }
-
- M_AST_IMM((ptrint) m, REG_SP, TRACE_ARGS_NUM * 8);
+ M_ASUB_IMM(cd->stackframesize * 4, REG_SP);
- M_MOV_IMM((ptrint) builtin_trace_args, REG_ITMP1);
- M_CALL(REG_ITMP1);
-
- M_AADD_IMM(TRACE_ARGS_NUM * 8 + 4, REG_SP);
- }
+#if !defined(NDEBUG)
+ emit_verbosecall_enter(jd);
+#endif
/* get function address (this must happen before the stackframeinfo) */
#if !defined(WITH_STATIC_CLASSPATH)
if (f == NULL) {
- codegen_addpatchref(cd, cd->mcodeptr, PATCHER_resolve_native, m, 0);
+ codegen_addpatchref(cd, PATCHER_resolve_native, m, 0);
if (opt_showdisassemble) {
M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
/* Mark the whole fpu stack as free for native functions (only for saved */
/* register count == 0). */
- i386_ffree_reg(cd, 0);
- i386_ffree_reg(cd, 1);
- i386_ffree_reg(cd, 2);
- i386_ffree_reg(cd, 3);
- i386_ffree_reg(cd, 4);
- i386_ffree_reg(cd, 5);
- i386_ffree_reg(cd, 6);
- i386_ffree_reg(cd, 7);
+ emit_ffree_reg(cd, 0);
+ emit_ffree_reg(cd, 1);
+ emit_ffree_reg(cd, 2);
+ emit_ffree_reg(cd, 3);
+ emit_ffree_reg(cd, 4);
+ emit_ffree_reg(cd, 5);
+ emit_ffree_reg(cd, 6);
+ emit_ffree_reg(cd, 7);
/* prepare data structures for native function call */
M_MOV(REG_SP, REG_ITMP1);
- M_AADD_IMM(stackframesize * 4, REG_ITMP1);
+ M_AADD_IMM(cd->stackframesize * 4, REG_ITMP1);
M_AST(REG_ITMP1, REG_SP, 0 * 4);
M_IST_IMM(0, REG_SP, 1 * 4);
- dseg_adddata(cd, cd->mcodeptr);
+ dseg_adddata(cd);
M_MOV(REG_SP, REG_ITMP2);
- M_AADD_IMM(stackframesize * 4 + SIZEOF_VOID_P, REG_ITMP2);
+ M_AADD_IMM(cd->stackframesize * 4 + SIZEOF_VOID_P, REG_ITMP2);
M_AST(REG_ITMP2, REG_SP, 2 * 4);
- M_ALD(REG_ITMP3, REG_SP, stackframesize * 4);
+ M_ALD(REG_ITMP3, REG_SP, cd->stackframesize * 4);
M_AST(REG_ITMP3, REG_SP, 3 * 4);
- M_MOV_IMM((ptrint) codegen_start_native_call, REG_ITMP1);
+ M_MOV_IMM(codegen_start_native_call, REG_ITMP1);
M_CALL(REG_ITMP1);
M_ALD(REG_ITMP3, REG_SP, 4 * 4);
if (!md->params[i].inmemory) {
/* no integer argument registers */
} else { /* float/double in memory can be copied like int/longs */
- s1 = (md->params[i].regoff + stackframesize + 1) * 4;
+ s1 = (md->params[i].regoff + cd->stackframesize + 1) * 4;
s2 = nmd->params[j].regoff * 4;
M_ILD(REG_ITMP1, REG_SP, s1);
/* if function is static, put class into second argument */
if (m->flags & ACC_STATIC)
- M_AST_IMM((ptrint) m->class, REG_SP, 1 * 4);
+ M_AST_IMM(m->class, REG_SP, 1 * 4);
/* put env into first argument */
- M_AST_IMM((ptrint) _Jv_env, REG_SP, 0 * 4);
+ M_AST_IMM(_Jv_env, REG_SP, 0 * 4);
/* call the native function */
/* save return value */
- if (IS_INT_LNG_TYPE(md->returntype.type)) {
- if (IS_2_WORD_TYPE(md->returntype.type))
- M_IST(REG_RESULT2, REG_SP, 2 * 4);
- M_IST(REG_RESULT, REG_SP, 1 * 4);
-
- } else {
- if (IS_2_WORD_TYPE(md->returntype.type))
- i386_fstl_membase(cd, REG_SP, 1 * 4);
- else
- i386_fsts_membase(cd, REG_SP, 1 * 4);
+ if (md->returntype.type != TYPE_VOID) {
+ if (IS_INT_LNG_TYPE(md->returntype.type)) {
+ if (IS_2_WORD_TYPE(md->returntype.type))
+ M_IST(REG_RESULT2, REG_SP, 2 * 4);
+ M_IST(REG_RESULT, REG_SP, 1 * 4);
+ }
+ else {
+ if (IS_2_WORD_TYPE(md->returntype.type))
+ emit_fstl_membase(cd, REG_SP, 1 * 4);
+ else
+ emit_fsts_membase(cd, REG_SP, 1 * 4);
+ }
}
- /* remove data structures for native function call */
+#if !defined(NDEBUG)
+ emit_verbosecall_exit(jd);
+#endif
+
+ /* remove native stackframe info */
M_MOV(REG_SP, REG_ITMP1);
- M_AADD_IMM(stackframesize * 4, REG_ITMP1);
+ M_AADD_IMM(cd->stackframesize * 4, REG_ITMP1);
M_AST(REG_ITMP1, REG_SP, 0 * 4);
- M_MOV_IMM((ptrint) codegen_finish_native_call, REG_ITMP1);
+ M_MOV_IMM(codegen_finish_native_call, REG_ITMP1);
M_CALL(REG_ITMP1);
+ M_MOV(REG_RESULT, REG_ITMP2); /* REG_ITMP3 == REG_RESULT2 */
- if (opt_verbosecall) {
- /* restore return value */
+ /* restore return value */
+ if (md->returntype.type != TYPE_VOID) {
if (IS_INT_LNG_TYPE(md->returntype.type)) {
if (IS_2_WORD_TYPE(md->returntype.type))
M_ILD(REG_RESULT2, REG_SP, 2 * 4);
M_ILD(REG_RESULT, REG_SP, 1 * 4);
-
- } else {
+ }
+ else {
if (IS_2_WORD_TYPE(md->returntype.type))
- i386_fldl_membase(cd, REG_SP, 1 * 4);
+ emit_fldl_membase(cd, REG_SP, 1 * 4);
else
- i386_flds_membase(cd, REG_SP, 1 * 4);
+ emit_flds_membase(cd, REG_SP, 1 * 4);
}
+ }
- M_ASUB_IMM(4 + 8 + 8 + 4, REG_SP);
-
- M_AST_IMM((ptrint) m, REG_SP, 0);
-
- M_IST(REG_RESULT, REG_SP, 4);
- M_IST(REG_RESULT2, REG_SP, 4 + 4);
-
- i386_fstl_membase(cd, REG_SP, 4 + 8);
- i386_fsts_membase(cd, REG_SP, 4 + 8 + 8);
-
- M_MOV_IMM((ptrint) builtin_displaymethodstop, REG_ITMP1);
- M_CALL(REG_ITMP1);
-
- M_AADD_IMM(4 + 8 + 8 + 4, REG_SP);
- }
+ M_AADD_IMM(cd->stackframesize * 4, REG_SP);
/* check for exception */
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
-/* i386_call_mem(cd, (ptrint) builtin_get_exceptionptrptr); */
- i386_call_mem(cd, (ptrint) &callgetexceptionptrptr);
-#else
- M_MOV_IMM((ptrint) &_no_threads_exceptionptr, REG_RESULT);
-#endif
- /* we can't use REG_ITMP3 == REG_RESULT2 */
- M_ALD(REG_ITMP2, REG_RESULT, 0);
-
- /* restore return value */
-
- if (IS_INT_LNG_TYPE(md->returntype.type)) {
- if (IS_2_WORD_TYPE(md->returntype.type))
- M_ILD(REG_RESULT2, REG_SP, 2 * 4);
- M_ILD(REG_RESULT, REG_SP, 1 * 4);
-
- } else {
- if (IS_2_WORD_TYPE(md->returntype.type))
- i386_fldl_membase(cd, REG_SP, 1 * 4);
- else
- i386_flds_membase(cd, REG_SP, 1 * 4);
- }
-
- M_AADD_IMM(stackframesize * 4, REG_SP);
-
M_TEST(REG_ITMP2);
M_BNE(1);
/* handle exception */
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- i386_push_reg(cd, REG_ITMP2);
-/* i386_call_mem(cd, (ptrint) builtin_get_exceptionptrptr); */
- i386_call_mem(cd, (ptrint) &callgetexceptionptrptr);
- i386_mov_imm_membase(cd, 0, REG_RESULT, 0);
- i386_pop_reg(cd, REG_ITMP1_XPTR);
-#else
M_MOV(REG_ITMP2, REG_ITMP1_XPTR);
- M_MOV_IMM((ptrint) &_exceptionptr, REG_ITMP2);
- i386_mov_imm_membase(cd, 0, REG_ITMP2, 0);
-#endif
M_ALD(REG_ITMP2_XPC, REG_SP, 0);
M_ASUB_IMM(2, REG_ITMP2_XPC);
- M_MOV_IMM((ptrint) asm_handle_nat_exception, REG_ITMP3);
+ M_MOV_IMM(asm_handle_nat_exception, REG_ITMP3);
M_JMP(REG_ITMP3);
- /* process patcher calls **************************************************/
-
- {
- u1 *xcodeptr;
- patchref *pref;
- codegendata *tmpcd;
- u8 mcode;
-
- tmpcd = DNEW(codegendata);
-
- for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
- /* Get machine code which is patched back in later. A */
- /* `call rel32' is 5 bytes long. */
-
- xcodeptr = cd->mcodebase + pref->branchpos;
- mcode = *((u8 *) xcodeptr);
-
- /* patch in `call rel32' to call the following code */
-
- tmpcd->mcodeptr = xcodeptr; /* set dummy mcode pointer */
- i386_call_imm(tmpcd, cd->mcodeptr - (xcodeptr + 5));
-
- /* move pointer to java_objectheader onto stack */
-
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- /* create a virtual java_objectheader */
+ /* generate patcher stubs */
- (void) dseg_addaddress(cd, get_dummyLR()); /* monitorPtr */
- disp = dseg_addaddress(cd, NULL); /* vftbl */
-
- M_MOV_IMM(0, REG_ITMP3);
- dseg_adddata(cd, cd->mcodeptr);
- M_AADD_IMM(disp, REG_ITMP3);
- M_PUSH(REG_ITMP3);
-#else
- M_PUSH_IMM(0);
-#endif
-
- /* move machine code bytes and classinfo pointer onto stack */
-
- M_PUSH_IMM((ptrint) (mcode >> 32));
- M_PUSH_IMM((ptrint) mcode);
- M_PUSH_IMM((ptrint) pref->ref);
- M_PUSH_IMM((ptrint) pref->patcher);
-
- M_MOV_IMM((ptrint) asm_wrapper_patcher, REG_ITMP3);
- M_JMP(REG_ITMP3);
- }
- }
+ emit_patcher_stubs(jd);
- codegen_finish(m, cd, (s4) ((u1 *) cd->mcodeptr - cd->mcodebase));
+ codegen_finish(jd);
- return cd->code->entrypoint;
+ return code->entrypoint;
}
projects / cacao.git / blobdiff