-/* jit/i386/codegen.c - machine code generator for i386
+/* src/vm/jit/i386/codegen.c - machine code generator for i386
- Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
- Institut f. Computersprachen, TU Wien
- R. Grafl, A. Krall, C. Kruegel, C. Oates, R. Obermaisser, M. Probst,
- S. Ring, E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich,
- J. Wenninger
+ Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
+ C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
+ E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
+ J. Wenninger, Institut f. Computersprachen - TU Wien
This file is part of CACAO.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA.
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
- Contact: cacao@complang.tuwien.ac.at
+ Contact: cacao@cacaojvm.org
Authors: Andreas Krall
Christian Thalinger
- $Id: codegen.c 1506 2004-11-14 14:48:49Z jowenn $
+ Changes: Joseph Wenninger
+ Christian Ullrich
+
+ $Id: codegen.c 4393 2006-01-31 15:41:22Z twisti $
*/
-#define _GNU_SOURCE
#include "config.h"
-#include "global.h"
-#include <stdio.h>
-#include <signal.h>
-#include <sys/ucontext.h>
-#include "types.h"
-#include "main.h"
-#include "builtin.h"
-#include "asmpart.h"
-#include "exceptions.h"
-#include "jni.h"
-#include "loader.h"
-#include "tables.h"
-#include "native.h"
-#include "jit/jit.h"
-#include "jit/parse.h"
-#include "jit/reg.h"
-#include "jit/i386/codegen.h"
-#include "jit/i386/emitfuncs.h"
-
-
-/* register descripton - array ************************************************/
-
-/* #define REG_RES 0 reserved register for OS or code generator */
-/* #define REG_RET 1 return value register */
-/* #define REG_EXC 2 exception value register (only old jit) */
-/* #define REG_SAV 3 (callee) saved register */
-/* #define REG_TMP 4 scratch temporary register (caller saved) */
-/* #define REG_ARG 5 argument register (caller saved) */
-
-/* #define REG_END -1 last entry in tables */
-
-int nregdescint[] = {
- REG_RET, REG_RES, REG_RES, REG_TMP, REG_RES, REG_SAV, REG_SAV, REG_SAV,
- REG_END
-};
-
-
-int nregdescfloat[] = {
- /* rounding problems with callee saved registers */
-/* REG_SAV, REG_SAV, REG_SAV, REG_SAV, REG_TMP, REG_TMP, REG_RES, REG_RES, */
-/* REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_RES, REG_RES, */
- REG_RES, REG_RES, REG_RES, REG_RES, REG_RES, REG_RES, REG_RES, REG_RES,
- REG_END
-};
-
-
-/*******************************************************************************
-
- include independent code generation stuff -- include after register
- descriptions to avoid extern definitions
-
-*******************************************************************************/
-
-#include "jit/codegen.inc"
-#include "jit/reg.inc"
-
-
-void codegen_stubcalled() {
- log_text("Stub has been called");
-}
-
-void codegen_general_stubcalled() {
- log_text("general exception stub has been called");
-}
-
-
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
-void thread_restartcriticalsection(ucontext_t *uc)
-{
- void *critical;
- if ((critical = thread_checkcritical((void*) uc->uc_mcontext.gregs[REG_EIP])) != NULL)
- uc->uc_mcontext.gregs[REG_EIP] = (u4) critical;
-}
-#endif
-
-
-#define PREPARE_NATIVE_STACKINFO \
- i386_push_reg(cd, REG_ITMP1); /*save itmp1, needed by some stubs */ \
- i386_alu_imm_reg(cd, I386_SUB, 2*4, REG_SP); /* build stack frame (2 * 4 bytes), together with previous =3*4 */ \
- i386_mov_imm_reg(cd, (s4) codegen_stubcalled,REG_ITMP1); \
- i386_call_reg(cd, REG_ITMP1); /*call codegen_stubcalled*/ \
- i386_mov_imm_reg(cd, (s4) builtin_asm_get_stackframeinfo,REG_ITMP1); \
- i386_call_reg(cd, REG_ITMP1); /*call builtin_asm_get_stackframeinfo*/ \
- i386_mov_reg_membase(cd, REG_RESULT,REG_SP,1*4); /* save thread pointer to native call stack*/ \
- i386_mov_membase_reg(cd, REG_RESULT,0,REG_ITMP2); /* get old value of thread specific native call stack */ \
- i386_mov_reg_membase(cd, REG_ITMP2,REG_SP,0*4); /* store value on stack */ \
- i386_mov_reg_membase(cd, REG_SP,REG_RESULT,0); /* store pointer to new stack frame information */ \
- i386_mov_membase_reg(cd, REG_SP,2*4,REG_ITMP1); /* restore ITMP1, need for some stubs*/ \
- i386_mov_imm_membase(cd, 0,REG_SP, 2*4); /* builtin */
-
-
-#define REMOVE_NATIVE_STACKINFO \
- i386_mov_membase_reg(cd, REG_SP,0,REG_ITMP2); \
- i386_mov_membase_reg(cd, REG_SP,4,REG_ITMP3); \
- i386_mov_reg_membase(cd, REG_ITMP2,REG_ITMP3,0); \
- i386_alu_imm_reg(cd, I386_ADD,3*4,REG_SP);
-
-
-/* NullPointerException signal handler for hardware null pointer check */
-
-void catch_NullPointerException(int sig, siginfo_t *siginfo, void *_p)
-{
- sigset_t nsig;
-/* long faultaddr; */
-
- struct ucontext *_uc = (struct ucontext *) _p;
- struct sigcontext *sigctx = (struct sigcontext *) &_uc->uc_mcontext;
- struct sigaction act;
-
- /* Reset signal handler - necessary for SysV, does no harm for BSD */
-
-/* instr = *((int*)(sigctx->eip)); */
-/* faultaddr = sigctx->sc_regs[(instr >> 16) & 0x1f]; */
-
-/* fprintf(stderr, "null=%d %p addr=%p\n", sig, sigctx, sigctx->eip);*/
-
-/* if (faultaddr == 0) { */
-/* signal(sig, (void *) catch_NullPointerException); */
- act.sa_sigaction = (void *) catch_NullPointerException;
- act.sa_flags = SA_SIGINFO;
- sigaction(sig, &act, NULL); /* reinstall handler */
-
- sigemptyset(&nsig);
- sigaddset(&nsig, sig);
- sigprocmask(SIG_UNBLOCK, &nsig, NULL); /* unblock signal */
-
- sigctx->ecx = sigctx->eip; /* REG_ITMP2_XPC */
- sigctx->eax = (u4) string_java_lang_NullPointerException;
- sigctx->eip = (u4) asm_throw_and_handle_exception;
-
- return;
-/* } else { */
-/* faultaddr += (long) ((instr << 16) >> 16); */
-/* fprintf(stderr, "faulting address: 0x%08x\n", faultaddr); */
-/* panic("Stack overflow"); */
-/* } */
-}
-
-
-/* ArithmeticException signal handler for hardware divide by zero check */
-
-void catch_ArithmeticException(int sig, siginfo_t *siginfo, void *_p)
-{
- sigset_t nsig;
-
-/* void **_p = (void **) &sig; */
-/* struct sigcontext *sigctx = (struct sigcontext *) ++_p; */
- struct ucontext *_uc = (struct ucontext *) _p;
- struct sigcontext *sigctx = (struct sigcontext *) &_uc->uc_mcontext;
- struct sigaction act;
-
- /* Reset signal handler - necessary for SysV, does no harm for BSD */
-
-/* signal(sig, (void *) catch_ArithmeticException); */
- act.sa_sigaction = (void *) catch_ArithmeticException;
- act.sa_flags = SA_SIGINFO;
- sigaction(sig, &act, NULL); /* reinstall handler */
-
- sigemptyset(&nsig);
- sigaddset(&nsig, sig);
- sigprocmask(SIG_UNBLOCK, &nsig, NULL); /* unblock signal */
-
- sigctx->ecx = sigctx->eip; /* REG_ITMP2_XPC */
- sigctx->eip = (u4) asm_throw_and_handle_hardware_arithmetic_exception;
-
- return;
-}
-
-
-void init_exceptions(void)
-{
- struct sigaction act;
-
- /* install signal handlers we need to convert to exceptions */
- sigemptyset(&act.sa_mask);
-
- if (!checknull) {
-#if defined(SIGSEGV)
-/* signal(SIGSEGV, (void *) catch_NullPointerException); */
- act.sa_sigaction = (void *) catch_NullPointerException;
- act.sa_flags = SA_SIGINFO;
- sigaction(SIGSEGV, &act, NULL);
-#endif
+#include <assert.h>
+#include <stdio.h>
-#if defined(SIGBUS)
-/* signal(SIGBUS, (void *) catch_NullPointerException); */
- act.sa_sigaction = (void *) catch_NullPointerException;
- act.sa_flags = SA_SIGINFO;
- sigaction(SIGBUS, &act, NULL);
+#include "vm/types.h"
+
+#include "vm/jit/i386/md-abi.h"
+
+#include "vm/jit/i386/codegen.h"
+#include "vm/jit/i386/emitfuncs.h"
+
+#include "cacao/cacao.h"
+#include "native/jni.h"
+#include "native/native.h"
+#include "vm/builtin.h"
+#include "vm/exceptions.h"
+#include "vm/global.h"
+#include "vm/loader.h"
+#include "vm/options.h"
+#include "vm/stringlocal.h"
+#include "vm/utf8.h"
+#include "vm/jit/asmpart.h"
+#include "vm/jit/codegen-common.h"
+#include "vm/jit/dseg.h"
+#include "vm/jit/jit.h"
+#include "vm/jit/parse.h"
+#include "vm/jit/patcher.h"
+#include "vm/jit/reg.h"
+
+#if defined(ENABLE_LSRA)
+# ifdef LSRA_USES_REG_RES
+# include "vm/jit/i386/icmd_uses_reg_res.inc"
+# endif
+# include "vm/jit/allocator/lsra.h"
#endif
- }
-
-/* signal(SIGFPE, (void *) catch_ArithmeticException); */
- act.sa_sigaction = (void *) catch_ArithmeticException;
- act.sa_flags = SA_SIGINFO;
- sigaction(SIGFPE, &act, NULL);
-}
-/* function codegen ************************************************************
+/* codegen *********************************************************************
- generates machine code
+ Generates machine code.
*******************************************************************************/
-void codegen(methodinfo *m, codegendata *cd, registerdata *rd)
+bool codegen(methodinfo *m, codegendata *cd, registerdata *rd)
{
- s4 len, s1, s2, s3, d;
- s4 a;
- stackptr src;
- varinfo *var;
- basicblock *bptr;
- instruction *iptr;
- s4 parentargs_base;
- u2 currentline;
- s4 fpu_st_offset = 0;
-
- exceptiontable *ex;
+ s4 len, s1, s2, s3, d, off, disp;
+ s4 parentargs_base;
+ stackptr src;
+ varinfo *var;
+ basicblock *bptr;
+ instruction *iptr;
+ exceptiontable *ex;
+ u2 currentline;
+ methodinfo *lm; /* local methodinfo for ICMD_INVOKE* */
+ builtintable_entry *bte;
+ methoddesc *md;
+ s4 fpu_st_offset = 0;
+
+ /* prevent compiler warnings */
+
+ d = 0;
+ currentline = 0;
+ lm = NULL;
+ bte = NULL;
{
- s4 i, p, pa, t, l;
+ s4 i, p, t, l;
s4 savedregs_num = 0;
+ s4 stack_off = 0;
/* space to save used callee saved registers */
- savedregs_num += (rd->savintregcnt - rd->maxsavintreguse);
- savedregs_num += (rd->savfltregcnt - rd->maxsavfltreguse);
+ savedregs_num += (INT_SAV_CNT - rd->savintreguse);
- parentargs_base = rd->maxmemuse + savedregs_num;
+ /* float register are saved on 2 4-byte stackslots */
+ savedregs_num += (FLT_SAV_CNT - rd->savfltreguse) * 2;
-#if defined(USE_THREADS) /* space to save argument of monitor_enter */
+ parentargs_base = rd->memuse + savedregs_num;
- if (checksync && (m->flags & ACC_SYNCHRONIZED))
- parentargs_base++;
+
+#if defined(USE_THREADS)
+ /* space to save argument of monitor_enter */
+ if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
+ /* reserve 2 slots for long/double return values for monitorexit */
+
+ if (IS_2_WORD_TYPE(m->parseddesc->returntype.type))
+ parentargs_base += 2;
+ else
+ parentargs_base++;
+ }
#endif
- /* create method header */
+/* create method header */
(void) dseg_addaddress(cd, m); /* MethodPointer */
- (void) dseg_adds4(cd, parentargs_base * 8); /* FrameSize */
+ (void) dseg_adds4(cd, parentargs_base * 4); /* FrameSize */
#if defined(USE_THREADS)
-
/* IsSync contains the offset relative to the stack pointer for the
argument of monitor_exit used in the exception handler. Since the
offset could be zero and give a wrong meaning of the flag it is
*/
if (checksync && (m->flags & ACC_SYNCHRONIZED))
- (void) dseg_adds4(cd, (rd->maxmemuse + 1) * 8); /* IsSync */
+ (void) dseg_adds4(cd, (rd->memuse + 1) * 4); /* IsSync */
else
-
#endif
-
- (void) dseg_adds4(cd, 0); /* IsSync */
+ (void) dseg_adds4(cd, 0); /* IsSync */
- (void) dseg_adds4(cd, m->isleafmethod); /* IsLeaf */
- (void) dseg_adds4(cd, rd->savintregcnt - rd->maxsavintreguse); /* IntSave */
- (void) dseg_adds4(cd, rd->savfltregcnt - rd->maxsavfltreguse); /* FltSave */
+ (void) dseg_adds4(cd, m->isleafmethod); /* IsLeaf */
+ (void) dseg_adds4(cd, INT_SAV_CNT - rd->savintreguse); /* IntSave */
+ (void) dseg_adds4(cd, FLT_SAV_CNT - rd->savfltreguse); /* FltSave */
/* adds a reference for the length of the line number counter. We don't
know the size yet, since we evaluate the information during code
dseg_addtarget(cd, ex->start);
dseg_addtarget(cd, ex->end);
dseg_addtarget(cd, ex->handler);
- (void) dseg_addaddress(cd, ex->catchtype);
+ (void) dseg_addaddress(cd, ex->catchtype.cls);
}
-
/* initialize mcode variables */
cd->mcodeptr = cd->mcodebase;
cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize);
- MCODECHECK(128 + m->paramcount);
- /* create stack frame (if necessary) */
+ /* initialize the last patcher pointer */
+
+ cd->lastmcodeptr = cd->mcodeptr;
- if (parentargs_base) {
- i386_alu_imm_reg(cd, I386_SUB, parentargs_base * 8, REG_SP);
+ /* generate profiling code */
+
+ if (opt_prof) {
+ M_MOV_IMM((ptrint) m, REG_ITMP1);
+ M_IADD_IMM_MEMBASE(1, REG_ITMP1, OFFSET(methodinfo, executioncount));
}
+ /* create stack frame (if necessary) */
+
+ if (parentargs_base)
+ M_ASUB_IMM(parentargs_base * 4, REG_SP);
+
/* save return address and used callee saved registers */
p = parentargs_base;
- for (i = rd->savintregcnt - 1; i >= rd->maxsavintreguse; i--) {
- p--; i386_mov_reg_membase(cd, rd->savintregs[i], REG_SP, p * 8);
+ for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
+ p--; M_AST(rd->savintregs[i], REG_SP, p * 4);
}
- for (i = rd->savfltregcnt - 1; i >= rd->maxsavfltreguse; i--) {
- p--; i386_fld_reg(cd, rd->savfltregs[i]); i386_fstpl_membase(cd, REG_SP, p * 8);
+ for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
+ p-=2; i386_fld_reg(cd, rd->savfltregs[i]); i386_fstpl_membase(cd, REG_SP, p * 4);
}
- /* save monitorenter argument */
+ /* take arguments out of register or stack frame */
-#if defined(USE_THREADS)
- s4 func_enter = (m->flags & ACC_STATIC) ?
- (s4) builtin_staticmonitorenter : (s4) builtin_monitorenter;
+ md = m->parseddesc;
+
+ stack_off = 0;
+ for (p = 0, l = 0; p < md->paramcount; p++) {
+ t = md->paramtypes[p].type;
+ var = &(rd->locals[l][t]);
+ l++;
+ if (IS_2_WORD_TYPE(t)) /* increment local counter for 2 word types */
+ l++;
+ if (var->type < 0)
+ continue;
+ s1 = md->params[p].regoff;
+ if (IS_INT_LNG_TYPE(t)) { /* integer args */
+ if (!md->params[p].inmemory) { /* register arguments */
+ log_text("integer register argument");
+ assert(0);
+ if (!(var->flags & INMEMORY)) { /* reg arg -> register */
+ /* rd->argintregs[md->params[p].regoff -> var->regoff */
+ } else { /* reg arg -> spilled */
+ /* rd->argintregs[md->params[p].regoff -> var->regoff * 4 */
+ }
+ } else { /* stack arguments */
+ if (!(var->flags & INMEMORY)) { /* stack arg -> register */
+ i386_mov_membase_reg( /* + 4 for return address */
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4, var->regoff);
+ /* + 4 for return address */
+ } else { /* stack arg -> spilled */
+ if (!IS_2_WORD_TYPE(t)) {
+#if 0
+ i386_mov_membase_reg( /* + 4 for return address */
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4,
+ REG_ITMP1);
+ i386_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP, var->regoff * 4);
+#else
+ /* reuse Stackslotand avoid copying */
+ var->regoff = parentargs_base + s1 + 1;
+#endif
+
+ } else {
+#if 0
+ i386_mov_membase_reg( /* + 4 for return address */
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4,
+ REG_ITMP1);
+ i386_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP, var->regoff * 4);
+ i386_mov_membase_reg( /* + 4 for return address */
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4 + 4,
+ REG_ITMP1);
+ i386_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP, var->regoff * 4 + 4);
+#else
+ /* reuse Stackslotand avoid copying */
+ var->regoff = parentargs_base + s1 + 1;
+#endif
+ }
+ }
+ }
+
+ } else { /* floating args */
+ if (!md->params[p].inmemory) { /* register arguments */
+ log_text("There are no float argument registers!");
+ assert(0);
+ if (!(var->flags & INMEMORY)) { /* reg arg -> register */
+ /* rd->argfltregs[md->params[p].regoff -> var->regoff */
+ } else { /* reg arg -> spilled */
+ /* rd->argfltregs[md->params[p].regoff -> var->regoff * 4 */
+ }
+
+ } else { /* stack arguments */
+ if (!(var->flags & INMEMORY)) { /* stack-arg -> register */
+ if (t == TYPE_FLT) {
+ i386_flds_membase(
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4);
+ fpu_st_offset++;
+ i386_fstp_reg(cd, var->regoff + fpu_st_offset);
+ fpu_st_offset--;
+
+ } else {
+ i386_fldl_membase(
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4);
+ fpu_st_offset++;
+ i386_fstp_reg(cd, var->regoff + fpu_st_offset);
+ fpu_st_offset--;
+ }
+
+ } else { /* stack-arg -> spilled */
+#if 0
+ i386_mov_membase_reg(
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4, REG_ITMP1);
+ i386_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP, var->regoff * 4);
+ if (t == TYPE_FLT) {
+ i386_flds_membase(
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4);
+ i386_fstps_membase(cd, REG_SP, var->regoff * 4);
+ } else {
+ i386_fldl_membase(
+ cd, REG_SP, (parentargs_base + s1) * 4 + 4);
+ i386_fstpl_membase(cd, REG_SP, var->regoff * 4);
+ }
+#else
+ /* reuse Stackslotand avoid copying */
+ var->regoff = parentargs_base + s1 + 1;
+#endif
+ }
+ }
+ }
+ } /* end for */
+
+ /* call monitorenter function */
+#if defined(USE_THREADS)
if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
+ s1 = rd->memuse;
+
if (m->flags & ACC_STATIC) {
- i386_mov_imm_reg(cd, (s4) m->class, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, rd->maxmemuse * 8);
+ i386_mov_imm_reg(cd, (ptrint) m->class, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, s1 * 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 0);
+ i386_mov_imm_reg(cd, (ptrint) BUILTIN_staticmonitorenter, REG_ITMP1);
+ i386_call_reg(cd, REG_ITMP1);
} else {
- i386_mov_membase_reg(cd, REG_SP, parentargs_base * 8 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, rd->maxmemuse * 8);
+ i386_mov_membase_reg(cd, REG_SP, parentargs_base * 4 + 4, REG_ITMP1);
+ i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
+ i386_jcc(cd, I386_CC_Z, 0);
+ codegen_addxnullrefs(cd, cd->mcodeptr);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, s1 * 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 0);
+ i386_mov_imm_reg(cd, (ptrint) BUILTIN_monitorenter, REG_ITMP1);
+ i386_call_reg(cd, REG_ITMP1);
}
-
- /* call monitorenter function */
-
- i386_alu_imm_reg(cd, I386_SUB, 4, REG_SP);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 0);
- i386_mov_imm_reg(cd, func_enter, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADD, 4, REG_SP);
}
#endif
*/
if (runverbose) {
- i386_alu_imm_reg(cd, I386_SUB, TRACE_ARGS_NUM * 8 + 4, REG_SP);
+ stack_off = 0;
+ s1 = INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4 + 4 + parentargs_base * 4;
+
+ M_ISUB_IMM(INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4, REG_SP);
- for (p = 0; p < m->paramcount && p < TRACE_ARGS_NUM; p++) {
- t = m->paramtypes[p];
+ /* save temporary registers for leaf methods */
+
+ for (p = 0; p < INT_TMP_CNT; p++)
+ M_IST(rd->tmpintregs[p], REG_SP, TRACE_ARGS_NUM * 8 + 4 + p * 4);
+
+ for (p = 0, l = 0; p < md->paramcount && p < TRACE_ARGS_NUM; p++) {
+ t = md->paramtypes[p].type;
if (IS_INT_LNG_TYPE(t)) {
if (IS_2_WORD_TYPE(t)) {
- i386_mov_membase_reg(cd, REG_SP, 4 + (parentargs_base + TRACE_ARGS_NUM + p) * 8 + 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, REG_ITMP1);
i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
- i386_mov_membase_reg(cd, REG_SP, 4 + (parentargs_base + TRACE_ARGS_NUM + p) * 8 + 4 + 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, s1 + stack_off + 4, REG_ITMP1);
i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
-/* } else if (t == TYPE_ADR) { */
- } else {
- i386_mov_membase_reg(cd, REG_SP, 4 + (parentargs_base + TRACE_ARGS_NUM + p) * 8 + 4, REG_ITMP1);
+ } else if (t == TYPE_ADR) {
+/* } else { */
+ i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, REG_ITMP1);
i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP1, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
-/* } else { */
-/* i386_mov_membase_reg(cd, REG_SP, 4 + (parentargs_base + TRACE_ARGS_NUM + p) * 8 + 4, EAX); */
-/* i386_cltd(cd); */
-/* i386_mov_reg_membase(cd, EAX, REG_SP, p * 8); */
-/* i386_mov_reg_membase(cd, EDX, REG_SP, p * 8 + 4); */
+ } else {
+ i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, EAX);
+ i386_cltd(cd);
+ i386_mov_reg_membase(cd, EAX, REG_SP, p * 8);
+ i386_mov_reg_membase(cd, EDX, REG_SP, p * 8 + 4);
}
} else {
if (!IS_2_WORD_TYPE(t)) {
- i386_flds_membase(cd, REG_SP, 4 + (parentargs_base + TRACE_ARGS_NUM + p) * 8 + 4);
+ i386_flds_membase(cd, REG_SP, s1 + stack_off);
i386_fstps_membase(cd, REG_SP, p * 8);
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP1, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
} else {
- i386_fldl_membase(cd, REG_SP, 4 + (parentargs_base + TRACE_ARGS_NUM + p) * 8 + 4);
+ i386_fldl_membase(cd, REG_SP, s1 + stack_off);
i386_fstpl_membase(cd, REG_SP, p * 8);
}
}
+ stack_off += (IS_2_WORD_TYPE(t)) ? 8 : 4;
}
/* fill up the remaining arguments */
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP1, REG_ITMP1);
- for (p = m->paramcount; p < TRACE_ARGS_NUM; p++) {
+ i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
+ for (p = md->paramcount; p < TRACE_ARGS_NUM; p++) {
i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
}
- i386_mov_imm_membase(cd, (s4) m, REG_SP, TRACE_ARGS_NUM * 8);
- i386_mov_imm_reg(cd, (s4) builtin_trace_args, REG_ITMP1);
+ i386_mov_imm_membase(cd, (ptrint) m, REG_SP, TRACE_ARGS_NUM * 8);
+ i386_mov_imm_reg(cd, (ptrint) builtin_trace_args, REG_ITMP1);
i386_call_reg(cd, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADD, TRACE_ARGS_NUM * 8 + 4, REG_SP);
- }
-
- /* take arguments out of register or stack frame */
-
- for (p = 0, l = 0; p < m->paramcount; p++) {
- t = m->paramtypes[p];
- var = &(rd->locals[l][t]);
- l++;
- if (IS_2_WORD_TYPE(t)) /* increment local counter for 2 word types */
- l++;
- if (var->type < 0)
- continue;
- if (IS_INT_LNG_TYPE(t)) { /* integer args */
- if (p < rd->intreg_argnum) { /* register arguments */
- panic("integer register argument");
- if (!(var->flags & INMEMORY)) { /* reg arg -> register */
-/* M_INTMOVE (argintregs[p], r); */
-
- } else { /* reg arg -> spilled */
-/* M_LST (argintregs[p], REG_SP, 8 * r); */
- }
- } else { /* stack arguments */
- pa = p - rd->intreg_argnum;
- if (!(var->flags & INMEMORY)) { /* stack arg -> register */
- i386_mov_membase_reg(cd, REG_SP, (parentargs_base + pa) * 8 + 4, var->regoff); /* + 4 for return address */
- } else { /* stack arg -> spilled */
- if (!IS_2_WORD_TYPE(t)) {
- i386_mov_membase_reg(cd, REG_SP, (parentargs_base + pa) * 8 + 4, REG_ITMP1); /* + 4 for return address */
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, var->regoff * 8);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, (parentargs_base + pa) * 8 + 4, REG_ITMP1); /* + 4 for return address */
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, var->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, (parentargs_base + pa) * 8 + 4 + 4, REG_ITMP1); /* + 4 for return address */
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, var->regoff * 8 + 4);
- }
- }
- }
-
- } else { /* floating args */
- if (p < rd->fltreg_argnum) { /* register arguments */
- if (!(var->flags & INMEMORY)) { /* reg arg -> register */
- panic("There are no float argument registers!");
-
- } else { /* reg arg -> spilled */
- panic("There are no float argument registers!");
- }
-
- } else { /* stack arguments */
- pa = p - rd->fltreg_argnum;
- if (!(var->flags & INMEMORY)) { /* stack-arg -> register */
- if (t == TYPE_FLT) {
- i386_flds_membase(cd, REG_SP, (parentargs_base + pa) * 8 + 4);
- fpu_st_offset++;
- i386_fstp_reg(cd, var->regoff + fpu_st_offset);
- fpu_st_offset--;
-
- } else {
- i386_fldl_membase(cd, REG_SP, (parentargs_base + pa) * 8 + 4);
- fpu_st_offset++;
- i386_fstp_reg(cd, var->regoff + fpu_st_offset);
- fpu_st_offset--;
- }
+ /* restore temporary registers for leaf methods */
- } else { /* stack-arg -> spilled */
-/* i386_mov_membase_reg(cd, REG_SP, (parentargs_base + pa) * 8 + 4, REG_ITMP1); */
-/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, r * 8); */
- if (t == TYPE_FLT) {
- i386_flds_membase(cd, REG_SP, (parentargs_base + pa) * 8 + 4);
- i386_fstps_membase(cd, REG_SP, var->regoff * 8);
+ for (p = 0; p < INT_TMP_CNT; p++)
+ M_ILD(rd->tmpintregs[p], REG_SP, TRACE_ARGS_NUM * 8 + 4 + p * 4);
- } else {
- i386_fldl_membase(cd, REG_SP, (parentargs_base + pa) * 8 + 4);
- i386_fstpl_membase(cd, REG_SP, var->regoff * 8);
- }
- }
- }
- }
- } /* end for */
+ M_IADD_IMM(INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4, REG_SP);
+ }
}
src = bptr->instack;
len = bptr->indepth;
MCODECHECK(64+len);
- while (src != NULL) {
- len--;
- if ((len == 0) && (bptr->type != BBTYPE_STD)) {
- if (!IS_2_WORD_TYPE(src->type)) {
- if (bptr->type == BBTYPE_SBR) {
- d = reg_of_var(rd, src, REG_ITMP1);
- i386_pop_reg(cd, d);
- store_reg_to_var_int(src, d);
+#if defined(ENABLE_LSRA)
+ if (opt_lsra) {
+ while (src != NULL) {
+ len--;
+ if ((len == 0) && (bptr->type != BBTYPE_STD)) {
+ if (!IS_2_WORD_TYPE(src->type)) {
+ if (bptr->type == BBTYPE_SBR) {
+ /* d = reg_of_var(m, src, REG_ITMP1); */
+ if (!(src->flags & INMEMORY))
+ d = src->regoff;
+ else
+ d = REG_ITMP1;
+
+ i386_pop_reg(cd, d);
+ store_reg_to_var_int(src, d);
+
+ } else if (bptr->type == BBTYPE_EXH) {
+ /* d = reg_of_var(m, src, REG_ITMP1); */
+ if (!(src->flags & INMEMORY))
+ d = src->regoff;
+ else
+ d = REG_ITMP1;
+ M_INTMOVE(REG_ITMP1, d);
+ store_reg_to_var_int(src, d);
+ }
+
+ } else {
+ log_text("copy interface registers(EXH, SBR): longs have to be in memory (begin 1)");
+ assert(0);
+ }
+ }
+ src = src->prev;
+ }
+
+ } else {
+#endif
+ while (src != NULL) {
+ len--;
+ if ((len == 0) && (bptr->type != BBTYPE_STD)) {
+ if (!IS_2_WORD_TYPE(src->type)) {
+ if (bptr->type == BBTYPE_SBR) {
+ d = reg_of_var(rd, src, REG_ITMP1);
+ i386_pop_reg(cd, d);
+ store_reg_to_var_int(src, d);
} else if (bptr->type == BBTYPE_EXH) {
d = reg_of_var(rd, src, REG_ITMP1);
M_INTMOVE(REG_ITMP1, d);
}
} else {
- panic("copy interface registers: longs have to me in memory (begin 1)");
+ log_text("copy interface registers: longs have to be in memory (begin 1)");
+ assert(0);
}
} else {
} else {
if (s2 == TYPE_FLT) {
- i386_flds_membase(cd, REG_SP, s1 * 8);
+ i386_flds_membase(cd, REG_SP, s1 * 4);
} else {
- i386_fldl_membase(cd, REG_SP, s1 * 8);
+ i386_fldl_membase(cd, REG_SP, s1 * 4);
}
}
store_reg_to_var_flt(src, d);
M_INTMOVE(s1, d);
} else {
- i386_mov_membase_reg(cd, REG_SP, s1 * 8, d);
+ i386_mov_membase_reg(cd, REG_SP, s1 * 4, d);
}
store_reg_to_var_int(src, d);
M_LNGMEMMOVE(s1, src->regoff);
} else {
- panic("copy interface registers: longs have to be in memory (begin 2)");
+ log_text("copy interface registers: longs have to be in memory (begin 2)");
+ assert(0);
}
}
}
}
src = src->prev;
}
+#if defined(ENABLE_LSRA)
+ }
+#endif
/* walk through all instructions */
currentline = iptr->line;
}
- MCODECHECK(64); /* an instruction usually needs < 64 words */
+ MCODECHECK(100); /* XXX are 100 bytes enough? */
switch (iptr->opc) {
+ case ICMD_INLINE_START:
+ case ICMD_INLINE_END:
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: NO ECX: NO EDX: NO */
+ break;
+
case ICMD_NOP: /* ... ==> ... */
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: NO ECX: NO EDX: NO */
break;
- case ICMD_NULLCHECKPOP: /* ..., objectref ==> ... */
+ case ICMD_CHECKNULL: /* ..., objectref ==> ..., objectref */
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: NO ECX: NO EDX: NO */
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4);
} else {
i386_test_reg_reg(cd, src->regoff, src->regoff);
}
- i386_jcc(cd, I386_CC_E, 0);
+ i386_jcc(cd, I386_CC_Z, 0);
codegen_addxnullrefs(cd, cd->mcodeptr);
break;
case ICMD_ICONST: /* ... ==> ..., constant */
/* op1 = 0, val.i = constant */
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: NO ECX: NO EDX: NO */
+
d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->dst->flags & INMEMORY) {
- i386_mov_imm_membase(cd, iptr->val.i, REG_SP, iptr->dst->regoff * 8);
+ M_IST_IMM(iptr->val.i, REG_SP, iptr->dst->regoff * 4);
} else {
if (iptr->val.i == 0) {
- i386_alu_reg_reg(cd, I386_XOR, d, d);
+ M_CLR(d);
} else {
- i386_mov_imm_reg(cd, iptr->val.i, d);
+ M_MOV_IMM(iptr->val.i, d);
}
}
break;
case ICMD_LCONST: /* ... ==> ..., constant */
/* op1 = 0, val.l = constant */
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: NO ECX: NO EDX: NO */
+
d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->dst->flags & INMEMORY) {
- i386_mov_imm_membase(cd, iptr->val.l, REG_SP, iptr->dst->regoff * 8);
- i386_mov_imm_membase(cd, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 8 + 4);
+ M_IST_IMM(iptr->val.l, REG_SP, iptr->dst->regoff * 4);
+ M_IST_IMM(iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
- panic("LCONST: longs have to be in memory");
+ log_text("LCONST: longs have to be in memory");
+ assert(0);
}
break;
case ICMD_FCONST: /* ... ==> ..., constant */
/* op1 = 0, val.f = constant */
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: YES ECX: NO EDX: NO */
+
d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (iptr->val.f == 0.0) {
i386_fldz(cd);
fpu_st_offset++;
} else {
- a = dseg_addfloat(cd, iptr->val.f);
+ disp = dseg_addfloat(cd, iptr->val.f);
i386_mov_imm_reg(cd, 0, REG_ITMP1);
dseg_adddata(cd, cd->mcodeptr);
- i386_flds_membase(cd, REG_ITMP1, a);
+ i386_flds_membase(cd, REG_ITMP1, disp);
fpu_st_offset++;
}
store_reg_to_var_flt(iptr->dst, d);
case ICMD_DCONST: /* ... ==> ..., constant */
/* op1 = 0, val.d = constant */
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: YES ECX: NO EDX: NO */
+
d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (iptr->val.d == 0.0) {
i386_fldz(cd);
fpu_st_offset++;
} else {
- a = dseg_adddouble(cd, iptr->val.d);
+ disp = dseg_adddouble(cd, iptr->val.d);
i386_mov_imm_reg(cd, 0, REG_ITMP1);
dseg_adddata(cd, cd->mcodeptr);
- i386_fldl_membase(cd, REG_ITMP1, a);
+ i386_fldl_membase(cd, REG_ITMP1, disp);
fpu_st_offset++;
}
store_reg_to_var_flt(iptr->dst, d);
case ICMD_ACONST: /* ... ==> ..., constant */
/* op1 = 0, val.a = constant */
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: YES ECX: NO EDX: NO */
+
d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_imm_membase(cd, (s4) iptr->val.a, REG_SP, iptr->dst->regoff * 8);
+
+ if ((iptr->target != NULL) && (iptr->val.a == NULL)) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_aconst,
+ (unresolved_class *) iptr->target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ M_MOV_IMM((ptrint) iptr->val.a, d);
+ store_reg_to_var_int(iptr->dst, d);
} else {
- if ((s4) iptr->val.a == 0) {
- i386_alu_reg_reg(cd, I386_XOR, d, d);
+ if (iptr->dst->flags & INMEMORY) {
+ M_AST_IMM((ptrint) iptr->val.a, REG_SP, iptr->dst->regoff * 4);
} else {
- i386_mov_imm_reg(cd, (s4) iptr->val.a, d);
+ if ((ptrint) iptr->val.a == 0) {
+ M_CLR(d);
+ } else {
+ M_MOV_IMM((ptrint) iptr->val.a, d);
+ }
}
}
break;
case ICMD_ILOAD: /* ... ==> ..., content of local variable */
case ICMD_ALOAD: /* op1 = local variable */
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if ((iptr->dst->varkind == LOCALVAR) &&
var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
if (iptr->dst->flags & INMEMORY) {
if (var->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, var->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, var->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else {
- i386_mov_reg_membase(cd, var->regoff, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, var->regoff, REG_SP, iptr->dst->regoff * 4);
}
} else {
if (var->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, var->regoff * 8, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_SP, var->regoff * 4, iptr->dst->regoff);
} else {
M_INTMOVE(var->regoff, iptr->dst->regoff);
case ICMD_LLOAD: /* ... ==> ..., content of local variable */
/* op1 = local variable */
-
+ /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */
+ /* EAX: NO ECX: NO EDX: NO */
+
d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if ((iptr->dst->varkind == LOCALVAR) &&
(iptr->dst->varnum == iptr->op1)) {
M_LNGMEMMOVE(var->regoff, iptr->dst->regoff);
} else {
- panic("LLOAD: longs have to be in memory");
+ log_text("LLOAD: longs have to be in memory");
+ assert(0);
}
} else {
- panic("LLOAD: longs have to be in memory");
+ log_text("LLOAD: longs have to be in memory");
+ assert(0);
}
break;
case ICMD_FLOAD: /* ... ==> ..., content of local variable */
/* op1 = local variable */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if ((iptr->dst->varkind == LOCALVAR) &&
}
var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
if (var->flags & INMEMORY) {
- i386_flds_membase(cd, REG_SP, var->regoff * 8);
+ i386_flds_membase(cd, REG_SP, var->regoff * 4);
fpu_st_offset++;
} else {
i386_fld_reg(cd, var->regoff + fpu_st_offset);
case ICMD_DLOAD: /* ... ==> ..., content of local variable */
/* op1 = local variable */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if ((iptr->dst->varkind == LOCALVAR) &&
}
var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
if (var->flags & INMEMORY) {
- i386_fldl_membase(cd, REG_SP, var->regoff * 8);
+ i386_fldl_membase(cd, REG_SP, var->regoff * 4);
fpu_st_offset++;
} else {
i386_fld_reg(cd, var->regoff + fpu_st_offset);
case ICMD_ISTORE: /* ..., value ==> ... */
case ICMD_ASTORE: /* op1 = local variable */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
if ((src->varkind == LOCALVAR) &&
(src->varnum == iptr->op1)) {
var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
if (var->flags & INMEMORY) {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, var->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, var->regoff * 4);
} else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, var->regoff * 8);
+ i386_mov_reg_membase(cd, src->regoff, REG_SP, var->regoff * 4);
}
} else {
case ICMD_LSTORE: /* ..., value ==> ... */
/* op1 = local variable */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
if ((src->varkind == LOCALVAR) &&
(src->varnum == iptr->op1)) {
M_LNGMEMMOVE(src->regoff, var->regoff);
} else {
- panic("LSTORE: longs have to be in memory");
+ log_text("LSTORE: longs have to be in memory");
+ assert(0);
}
} else {
- panic("LSTORE: longs have to be in memory");
+ log_text("LSTORE: longs have to be in memory");
+ assert(0);
}
break;
case ICMD_FSTORE: /* ..., value ==> ... */
/* op1 = local variable */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
if ((src->varkind == LOCALVAR) &&
(src->varnum == iptr->op1)) {
var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
if (var->flags & INMEMORY) {
var_to_reg_flt(s1, src, REG_FTMP1);
- i386_fstps_membase(cd, REG_SP, var->regoff * 8);
+ i386_fstps_membase(cd, REG_SP, var->regoff * 4);
fpu_st_offset--;
} else {
var_to_reg_flt(s1, src, var->regoff);
case ICMD_DSTORE: /* ..., value ==> ... */
/* op1 = local variable */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
if ((src->varkind == LOCALVAR) &&
(src->varnum == iptr->op1)) {
var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
if (var->flags & INMEMORY) {
var_to_reg_flt(s1, src, REG_FTMP1);
- i386_fstpl_membase(cd, REG_SP, var->regoff * 8);
+ i386_fstpl_membase(cd, REG_SP, var->regoff * 4);
fpu_st_offset--;
} else {
var_to_reg_flt(s1, src, var->regoff);
case ICMD_POP: /* ..., value ==> ... */
case ICMD_POP2: /* ..., value, value ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
break;
case ICMD_DUP: /* ..., a ==> ..., a, a */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
M_COPY(src, iptr->dst);
break;
case ICMD_DUP2: /* ..., a, b ==> ..., a, b, a, b */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
M_COPY(src, iptr->dst);
M_COPY(src->prev, iptr->dst->prev);
break;
case ICMD_DUP_X1: /* ..., a, b ==> ..., b, a, b */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
M_COPY(src, iptr->dst);
M_COPY(src->prev, iptr->dst->prev);
break;
case ICMD_DUP2_X1: /* ..., a, b, c ==> ..., b, c, a, b, c */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
M_COPY(src, iptr->dst);
M_COPY(src->prev, iptr->dst->prev);
M_COPY(src->prev->prev, iptr->dst->prev->prev);
M_COPY(iptr->dst, iptr->dst->prev->prev->prev);
- M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev);
+ M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev);
break;
case ICMD_DUP2_X2: /* ..., a, b, c, d ==> ..., c, d, a, b, c, d */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
M_COPY(src, iptr->dst);
M_COPY(src->prev, iptr->dst->prev);
break;
case ICMD_SWAP: /* ..., a, b ==> ..., b, a */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
M_COPY(src, iptr->dst->prev);
M_COPY(src->prev, iptr->dst);
/* integer operations *************************************************/
case ICMD_INEG: /* ..., value ==> ..., - value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
- i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 8);
+ i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
i386_neg_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
}
} else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 8);
- i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4);
+ i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4);
}
} else {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
i386_neg_reg(cd, iptr->dst->regoff);
} else {
break;
case ICMD_LNEG: /* ..., value ==> ..., - value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
- i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 8);
- i386_alu_imm_membase(cd, I386_ADC, 0, REG_SP, iptr->dst->regoff * 8 + 4);
- i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4);
+ i386_alu_imm_membase(cd, ALU_ADC, 0, REG_SP, iptr->dst->regoff * 4 + 4);
+ i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
i386_neg_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADC, 0, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP1);
i386_neg_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
}
break;
case ICMD_I2L: /* ..., value ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: YES */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, EAX);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, EAX);
i386_cltd(cd);
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
M_INTMOVE(src->regoff, EAX);
i386_cltd(cd);
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
break;
case ICMD_L2I: /* ..., value ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
}
} else {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
}
}
break;
case ICMD_INT2BYTE: /* ..., value ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
i386_shift_imm_reg(cd, I386_SHL, 24, REG_ITMP1);
i386_shift_imm_reg(cd, I386_SAR, 24, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 8);
- i386_shift_imm_membase(cd, I386_SHL, 24, REG_SP, iptr->dst->regoff * 8);
- i386_shift_imm_membase(cd, I386_SAR, 24, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4);
+ i386_shift_imm_membase(cd, I386_SHL, 24, REG_SP, iptr->dst->regoff * 4);
+ i386_shift_imm_membase(cd, I386_SAR, 24, REG_SP, iptr->dst->regoff * 4);
}
} else {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
i386_shift_imm_reg(cd, I386_SHL, 24, iptr->dst->regoff);
i386_shift_imm_reg(cd, I386_SAR, 24, iptr->dst->regoff);
break;
case ICMD_INT2CHAR: /* ..., value ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
- i386_alu_imm_membase(cd, I386_AND, 0x0000ffff, REG_SP, iptr->dst->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_AND, 0x0000ffff, REG_SP, iptr->dst->regoff * 4);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_AND, 0x0000ffff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
}
} else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 8);
- i386_alu_imm_membase(cd, I386_AND, 0x0000ffff, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4);
+ i386_alu_imm_membase(cd, ALU_AND, 0x0000ffff, REG_SP, iptr->dst->regoff * 4);
}
} else {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
- i386_alu_imm_reg(cd, I386_AND, 0x0000ffff, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
+ i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, iptr->dst->regoff);
} else {
M_INTMOVE(src->regoff, iptr->dst->regoff);
- i386_alu_imm_reg(cd, I386_AND, 0x0000ffff, iptr->dst->regoff);
+ i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, iptr->dst->regoff);
}
}
break;
case ICMD_INT2SHORT: /* ..., value ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
i386_shift_imm_reg(cd, I386_SHL, 16, REG_ITMP1);
i386_shift_imm_reg(cd, I386_SAR, 16, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 8);
- i386_shift_imm_membase(cd, I386_SHL, 16, REG_SP, iptr->dst->regoff * 8);
- i386_shift_imm_membase(cd, I386_SAR, 16, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4);
+ i386_shift_imm_membase(cd, I386_SHL, 16, REG_SP, iptr->dst->regoff * 4);
+ i386_shift_imm_membase(cd, I386_SAR, 16, REG_SP, iptr->dst->regoff * 4);
}
} else {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
i386_shift_imm_reg(cd, I386_SHL, 16, iptr->dst->regoff);
i386_shift_imm_reg(cd, I386_SAR, 16, iptr->dst->regoff);
case ICMD_IADD: /* ..., val1, val2 ==> ..., val1 + val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialu(cd, I386_ADD, src, iptr);
+ i386_emit_ialu(cd, ALU_ADD, src, iptr);
break;
case ICMD_IADDCONST: /* ..., value ==> ..., value + constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
- /* should we use a inc optimization for smaller code size? */
- i386_emit_ialuconst(cd, I386_ADD, src, iptr);
+ i386_emit_ialuconst(cd, ALU_ADD, src, iptr);
break;
case ICMD_LADD: /* ..., val1, val2 ==> ..., val1 + val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
if (src->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_ADD, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_ADC, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_ADD, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_ADC, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
} else if (src->prev->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_ADD, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_ADC, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_ADD, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_ADC, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_ADD, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_ADC, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_ADD, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_ADC, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
case ICMD_LADDCONST: /* ..., value ==> ..., value + constant */
/* val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
+ /* else path can never happen? longs stay in memory! */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
- i386_alu_imm_membase(cd, I386_ADD, iptr->val.l, REG_SP, iptr->dst->regoff * 8);
- i386_alu_imm_membase(cd, I386_ADC, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_alu_imm_membase(cd, ALU_ADD, iptr->val.l, REG_SP, iptr->dst->regoff * 4);
+ i386_alu_imm_membase(cd, ALU_ADC, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADD, iptr->val.l, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADC, iptr->val.l >> 32, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_ADD, iptr->val.l, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_ADC, iptr->val.l >> 32, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
}
break;
case ICMD_ISUB: /* ..., val1, val2 ==> ..., val1 - val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
if (src->prev->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_SUB, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
}
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
M_INTMOVE(src->prev->regoff, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_SUB, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
if (src->prev->regoff == iptr->dst->regoff) {
- i386_alu_reg_membase(cd, I386_SUB, src->regoff, REG_SP, iptr->dst->regoff * 8);
+ i386_alu_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 4);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_reg_reg(cd, I386_SUB, src->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
}
} else {
- i386_mov_reg_membase(cd, src->prev->regoff, REG_SP, iptr->dst->regoff * 8);
- i386_alu_reg_membase(cd, I386_SUB, src->regoff, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, src->prev->regoff, REG_SP, iptr->dst->regoff * 4);
+ i386_alu_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 4);
}
} else {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, d);
- i386_alu_membase_reg(cd, I386_SUB, REG_SP, src->regoff * 8, d);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, d);
+ i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, d);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
M_INTMOVE(src->prev->regoff, d);
- i386_alu_membase_reg(cd, I386_SUB, REG_SP, src->regoff * 8, d);
+ i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, d);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
/* workaround for reg alloc */
if (src->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_reg_reg(cd, I386_SUB, src->regoff, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
M_INTMOVE(REG_ITMP1, d);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, d);
- i386_alu_reg_reg(cd, I386_SUB, src->regoff, d);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, d);
+ i386_alu_reg_reg(cd, ALU_SUB, src->regoff, d);
}
} else {
/* workaround for reg alloc */
if (src->regoff == iptr->dst->regoff) {
M_INTMOVE(src->prev->regoff, REG_ITMP1);
- i386_alu_reg_reg(cd, I386_SUB, src->regoff, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
M_INTMOVE(REG_ITMP1, d);
} else {
M_INTMOVE(src->prev->regoff, d);
- i386_alu_reg_reg(cd, I386_SUB, src->regoff, d);
+ i386_alu_reg_reg(cd, ALU_SUB, src->regoff, d);
}
}
}
case ICMD_ISUBCONST: /* ..., value ==> ..., value + constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, I386_SUB, src, iptr);
+ i386_emit_ialuconst(cd, ALU_SUB, src, iptr);
break;
case ICMD_LSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
if (src->prev->regoff == iptr->dst->regoff) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_SBB, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_SBB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_SUB, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_SBB, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_SBB, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
}
case ICMD_LSUBCONST: /* ..., value ==> ..., value - constant */
/* val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO */
+ /* else path can never happen? longs stay in memory! */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
- i386_alu_imm_membase(cd, I386_SUB, iptr->val.l, REG_SP, iptr->dst->regoff * 8);
- i386_alu_imm_membase(cd, I386_SBB, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_alu_imm_membase(cd, ALU_SUB, iptr->val.l, REG_SP, iptr->dst->regoff * 4);
+ i386_alu_imm_membase(cd, ALU_SBB, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
/* TODO: could be size optimized with lea -- see gcc output */
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_SUB, iptr->val.l, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_SBB, iptr->val.l >> 32, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_SUB, iptr->val.l, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_SBB, iptr->val.l >> 32, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
}
break;
case ICMD_IMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO OUTPUT: EAX*/ /* EDX really not destroyed by IMUL? */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
i386_imul_reg_reg(cd, src->prev->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
i386_imul_reg_reg(cd, src->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else {
i386_mov_reg_reg(cd, src->prev->regoff, REG_ITMP1);
i386_imul_reg_reg(cd, src->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
}
} else {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, iptr->dst->regoff);
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, iptr->dst->regoff);
+ i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
M_INTMOVE(src->prev->regoff, iptr->dst->regoff);
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
+ i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
M_INTMOVE(src->regoff, iptr->dst->regoff);
- i386_imul_membase_reg(cd, REG_SP, src->prev->regoff * 8, iptr->dst->regoff);
+ i386_imul_membase_reg(cd, REG_SP, src->prev->regoff * 4, iptr->dst->regoff);
} else {
if (src->regoff == iptr->dst->regoff) {
case ICMD_IMULCONST: /* ..., value ==> ..., value * constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: EAX*/ /* EDX really not destroyed by IMUL? */
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
- i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
} else {
i386_imul_imm_reg_reg(cd, iptr->val.i, src->regoff, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
}
} else {
if (src->flags & INMEMORY) {
- i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 8, iptr->dst->regoff);
+ i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 4, iptr->dst->regoff);
} else {
i386_imul_imm_reg_reg(cd, iptr->val.i, src->regoff, iptr->dst->regoff);
break;
case ICMD_LMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, EAX); /* mem -> EAX */
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX); /* mem -> EAX */
/* optimize move EAX -> REG_ITMP3 is slower??? */
/* i386_mov_reg_reg(cd, EAX, REG_ITMP3); */
- i386_mul_membase(cd, REG_SP, src->regoff * 8); /* mem * EAX -> EDX:EAX */
+ i386_mul_membase(cd, REG_SP, src->regoff * 4); /* mem * EAX -> EDX:EAX */
/* TODO: optimize move EAX -> REG_ITMP3 */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP2); /* mem -> ITMP3 */
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); /* mem -> ITMP3 */
+ i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
+ i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP2); /* mem -> ITMP3 */
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP2); /* mem -> ITMP3 */
+ i386_imul_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
+ i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
break;
case ICMD_LMULCONST: /* ..., value ==> ..., value * constant */
/* val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
i386_mov_imm_reg(cd, iptr->val.l, EAX); /* imm -> EAX */
- i386_mul_membase(cd, REG_SP, src->regoff * 8); /* mem * EAX -> EDX:EAX */
+ i386_mul_membase(cd, REG_SP, src->regoff * 4); /* mem * EAX -> EDX:EAX */
/* TODO: optimize move EAX -> REG_ITMP3 */
i386_mov_imm_reg(cd, iptr->val.l >> 32, REG_ITMP2); /* imm -> ITMP3 */
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
+ i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
+ i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
i386_mov_imm_reg(cd, iptr->val.l, REG_ITMP2); /* imm -> ITMP3 */
- i386_imul_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
+ i386_imul_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */
+ i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
break;
case ICMD_IDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EAX */
d = reg_of_var(rd, iptr->dst, REG_NULL);
var_to_reg_int(s1, src, REG_ITMP2);
gen_div_check(src);
if (src->prev->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, EAX);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX);
} else {
M_INTMOVE(src->prev->regoff, EAX);
}
-
- i386_alu_imm_reg(cd, I386_CMP, 0x80000000, EAX); /* check as described in jvm spec */
+
+ /* check as described in jvm spec */
+
+ i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, EAX);
i386_jcc(cd, I386_CC_NE, 3 + 6);
- i386_alu_imm_reg(cd, I386_CMP, -1, s1);
+ i386_alu_imm_reg(cd, ALU_CMP, -1, s1);
i386_jcc(cd, I386_CC_E, 1 + 2);
i386_cltd(cd);
i386_idiv_reg(cd, s1);
if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4);
} else {
M_INTMOVE(EAX, iptr->dst->regoff);
break;
case ICMD_IREM: /* ..., val1, val2 ==> ..., val1 % val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EDX */
+
d = reg_of_var(rd, iptr->dst, REG_NULL);
var_to_reg_int(s1, src, REG_ITMP2);
gen_div_check(src);
if (src->prev->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, EAX);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX);
} else {
M_INTMOVE(src->prev->regoff, EAX);
}
-
- i386_alu_imm_reg(cd, I386_CMP, 0x80000000, EAX); /* check as described in jvm spec */
+
+ /* check as described in jvm spec */
+
+ i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, EAX);
i386_jcc(cd, I386_CC_NE, 2 + 3 + 6);
- i386_alu_reg_reg(cd, I386_XOR, EDX, EDX);
- i386_alu_imm_reg(cd, I386_CMP, -1, s1);
+ i386_alu_reg_reg(cd, ALU_XOR, EDX, EDX);
+ i386_alu_imm_reg(cd, ALU_CMP, -1, s1);
i386_jcc(cd, I386_CC_E, 1 + 2);
i386_cltd(cd);
i386_idiv_reg(cd, s1);
if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4);
} else {
M_INTMOVE(EDX, iptr->dst->regoff);
case ICMD_IDIVPOW2: /* ..., value ==> ..., value >> constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL */
/* TODO: optimize for `/ 2' */
var_to_reg_int(s1, src, REG_ITMP1);
M_INTMOVE(s1, d);
i386_test_reg_reg(cd, d, d);
- a = 2;
- CALCIMMEDIATEBYTES(a, (1 << iptr->val.i) - 1);
- i386_jcc(cd, I386_CC_NS, a);
- i386_alu_imm_reg(cd, I386_ADD, (1 << iptr->val.i) - 1, d);
+ disp = 2;
+ CALCIMMEDIATEBYTES(disp, (1 << iptr->val.i) - 1);
+ i386_jcc(cd, I386_CC_NS, disp);
+ i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.i) - 1, d);
i386_shift_imm_reg(cd, I386_SAR, iptr->val.i, d);
store_reg_to_var_int(iptr->dst, d);
break;
- case ICMD_LDIVPOW2: /* ..., value ==> ..., value >> constant */
- /* val.i = constant */
-
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- a = 2;
- CALCIMMEDIATEBYTES(a, (1 << iptr->val.i) - 1);
- a += 3;
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
-
- i386_test_reg_reg(cd, REG_ITMP2, REG_ITMP2);
- i386_jcc(cd, I386_CC_NS, a);
- i386_alu_imm_reg(cd, I386_ADD, (1 << iptr->val.i) - 1, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADC, 0, REG_ITMP2);
- i386_shrd_imm_reg_reg(cd, iptr->val.i, REG_ITMP2, REG_ITMP1);
- i386_shift_imm_reg(cd, I386_SAR, iptr->val.i, REG_ITMP2);
-
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
- }
- }
- break;
-
case ICMD_IREMPOW2: /* ..., value ==> ..., value % constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */
var_to_reg_int(s1, src, REG_ITMP1);
d = reg_of_var(rd, iptr->dst, REG_ITMP2);
s1 = REG_ITMP1;
}
- a = 2;
- a += 2;
- a += 2;
- CALCIMMEDIATEBYTES(a, iptr->val.i);
- a += 2;
+ disp = 2;
+ disp += 2;
+ disp += 2;
+ CALCIMMEDIATEBYTES(disp, iptr->val.i);
+ disp += 2;
/* TODO: optimize */
M_INTMOVE(s1, d);
- i386_alu_imm_reg(cd, I386_AND, iptr->val.i, d);
+ i386_alu_imm_reg(cd, ALU_AND, iptr->val.i, d);
i386_test_reg_reg(cd, s1, s1);
- i386_jcc(cd, I386_CC_GE, a);
+ i386_jcc(cd, I386_CC_GE, disp);
i386_mov_reg_reg(cd, s1, d);
i386_neg_reg(cd, d);
- i386_alu_imm_reg(cd, I386_AND, iptr->val.i, d);
+ i386_alu_imm_reg(cd, ALU_AND, iptr->val.i, d);
i386_neg_reg(cd, d);
/* M_INTMOVE(s1, EAX); */
/* i386_cltd(cd); */
-/* i386_alu_reg_reg(cd, I386_XOR, EDX, EAX); */
-/* i386_alu_reg_reg(cd, I386_SUB, EDX, EAX); */
-/* i386_alu_reg_reg(cd, I386_AND, iptr->val.i, EAX); */
-/* i386_alu_reg_reg(cd, I386_XOR, EDX, EAX); */
-/* i386_alu_reg_reg(cd, I386_SUB, EDX, EAX); */
+/* i386_alu_reg_reg(cd, ALU_XOR, EDX, EAX); */
+/* i386_alu_reg_reg(cd, ALU_SUB, EDX, EAX); */
+/* i386_alu_reg_reg(cd, ALU_AND, iptr->val.i, EAX); */
+/* i386_alu_reg_reg(cd, ALU_XOR, EDX, EAX); */
+/* i386_alu_reg_reg(cd, ALU_SUB, EDX, EAX); */
/* M_INTMOVE(EAX, d); */
-/* i386_alu_reg_reg(cd, I386_XOR, d, d); */
+/* i386_alu_reg_reg(cd, ALU_XOR, d, d); */
/* i386_mov_imm_reg(cd, iptr->val.i, ECX); */
/* i386_shrd_reg_reg(cd, s1, d); */
/* i386_shift_imm_reg(cd, I386_SHR, 32 - iptr->val.i, d); */
store_reg_to_var_int(iptr->dst, d);
break;
- case ICMD_LREMPOW2: /* ..., value ==> ..., value % constant */
- /* val.l = constant */
+ case ICMD_LDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
+ case ICMD_LREM: /* ..., val1, val2 ==> ..., val1 % val2 */
d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- if (src->flags & INMEMORY) {
- /* Intel algorithm -- does not work, because constant is wrong */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1); */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP3); */
+ M_ILD(REG_ITMP2, REG_SP, src->regoff * 4);
+ M_OR_MEMBASE(REG_SP, src->regoff * 4 + 4, REG_ITMP2);
+ M_TEST(REG_ITMP2);
+ M_BEQ(0);
+ codegen_addxdivrefs(cd, cd->mcodeptr);
-/* M_INTMOVE(REG_ITMP1, REG_ITMP2); */
-/* i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3); */
-/* i386_jcc(cd, I386_CC_NS, offset); */
-/* i386_alu_imm_reg(cd, I386_ADD, (1 << iptr->val.l) - 1, REG_ITMP2); */
-/* i386_alu_imm_reg(cd, I386_ADC, 0, REG_ITMP3); */
-
-/* i386_shrd_imm_reg_reg(cd, iptr->val.l, REG_ITMP3, REG_ITMP2); */
-/* i386_shift_imm_reg(cd, I386_SAR, iptr->val.l, REG_ITMP3); */
-/* i386_shld_imm_reg_reg(cd, iptr->val.l, REG_ITMP2, REG_ITMP3); */
+ bte = iptr->val.a;
+ md = bte->md;
-/* i386_shift_imm_reg(cd, I386_SHL, iptr->val.l, REG_ITMP2); */
+ M_ILD(REG_ITMP1, REG_SP, src->prev->regoff * 4);
+ M_ILD(REG_ITMP2, REG_SP, src->prev->regoff * 4 + 4);
+ M_IST(REG_ITMP1, REG_SP, 0 * 4);
+ M_IST(REG_ITMP2, REG_SP, 0 * 4 + 4);
-/* i386_alu_reg_reg(cd, I386_SUB, REG_ITMP2, REG_ITMP1); */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2); */
-/* i386_alu_reg_reg(cd, I386_SBB, REG_ITMP3, REG_ITMP2); */
+ M_ILD(REG_ITMP1, REG_SP, src->regoff * 4);
+ M_ILD(REG_ITMP2, REG_SP, src->regoff * 4 + 4);
+ M_IST(REG_ITMP1, REG_SP, 2 * 4);
+ M_IST(REG_ITMP2, REG_SP, 2 * 4 + 4);
-/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8); */
-/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4); */
+ M_MOV_IMM((ptrint) bte->fp, REG_ITMP3);
+ M_CALL(REG_ITMP3);
- /* Alpha algorithm */
- a = 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8 + 4);
+ M_IST(REG_RESULT, REG_SP, iptr->dst->regoff * 4);
+ M_IST(REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4);
+ break;
- a += 2;
- a += 3;
- a += 2;
+ case ICMD_LDIVPOW2: /* ..., value ==> ..., value >> constant */
+ /* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */
- /* TODO: hmm, don't know if this is always correct */
- a += 2;
- CALCIMMEDIATEBYTES(a, iptr->val.l & 0x00000000ffffffff);
- a += 2;
- CALCIMMEDIATEBYTES(a, iptr->val.l >> 32);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
+ if (iptr->dst->flags & INMEMORY) {
+ if (src->flags & INMEMORY) {
+ disp = 2;
+ CALCIMMEDIATEBYTES(disp, (1 << iptr->val.i) - 1);
+ disp += 3;
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
- a += 2;
- a += 3;
- a += 2;
+ i386_test_reg_reg(cd, REG_ITMP2, REG_ITMP2);
+ i386_jcc(cd, I386_CC_NS, disp);
+ i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.i) - 1, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2);
+ i386_shrd_imm_reg_reg(cd, iptr->val.i, REG_ITMP2, REG_ITMP1);
+ i386_shift_imm_reg(cd, I386_SAR, iptr->val.i, REG_ITMP2);
+
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
+ }
+ }
+ break;
+
+ case ICMD_LREMPOW2: /* ..., value ==> ..., value % constant */
+ /* val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */
+
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
+ if (iptr->dst->flags & INMEMORY) {
+ if (src->flags & INMEMORY) {
+ /* Intel algorithm -- does not work, because constant is wrong */
+/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); */
+/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP3); */
+
+/* M_INTMOVE(REG_ITMP1, REG_ITMP2); */
+/* i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3); */
+/* i386_jcc(cd, I386_CC_NS, offset); */
+/* i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.l) - 1, REG_ITMP2); */
+/* i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP3); */
+
+/* i386_shrd_imm_reg_reg(cd, iptr->val.l, REG_ITMP3, REG_ITMP2); */
+/* i386_shift_imm_reg(cd, I386_SAR, iptr->val.l, REG_ITMP3); */
+/* i386_shld_imm_reg_reg(cd, iptr->val.l, REG_ITMP2, REG_ITMP3); */
+
+/* i386_shift_imm_reg(cd, I386_SHL, iptr->val.l, REG_ITMP2); */
+
+/* i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP2, REG_ITMP1); */
+/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); */
+/* i386_alu_reg_reg(cd, ALU_SBB, REG_ITMP3, REG_ITMP2); */
+
+/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */
+/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
+ /* Alpha algorithm */
+ disp = 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4 + 4);
+
+ disp += 2;
+ disp += 3;
+ disp += 2;
+
+ /* TODO: hmm, don't know if this is always correct */
+ disp += 2;
+ CALCIMMEDIATEBYTES(disp, iptr->val.l & 0x00000000ffffffff);
+ disp += 2;
+ CALCIMMEDIATEBYTES(disp, iptr->val.l >> 32);
+
+ disp += 2;
+ disp += 3;
+ disp += 2;
+
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
- i386_alu_imm_reg(cd, I386_AND, iptr->val.l, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_AND, iptr->val.l >> 32, REG_ITMP2);
- i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, src->regoff * 8 + 4);
- i386_jcc(cd, I386_CC_GE, a);
+ i386_alu_imm_reg(cd, ALU_AND, iptr->val.l, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_AND, iptr->val.l >> 32, REG_ITMP2);
+ i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4 + 4);
+ i386_jcc(cd, I386_CC_GE, disp);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
i386_neg_reg(cd, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADC, 0, REG_ITMP2);
+ i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2);
i386_neg_reg(cd, REG_ITMP2);
- i386_alu_imm_reg(cd, I386_AND, iptr->val.l, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_AND, iptr->val.l >> 32, REG_ITMP2);
+ i386_alu_imm_reg(cd, ALU_AND, iptr->val.l, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_AND, iptr->val.l >> 32, REG_ITMP2);
i386_neg_reg(cd, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADC, 0, REG_ITMP2);
+ i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2);
i386_neg_reg(cd, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
}
}
break;
case ICMD_ISHL: /* ..., val1, val2 ==> ..., val1 << val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishift(cd, I386_SHL, src, iptr);
case ICMD_ISHLCONST: /* ..., value ==> ..., value << constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishiftconst(cd, I386_SHL, src, iptr);
break;
case ICMD_ISHR: /* ..., val1, val2 ==> ..., val1 >> val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishift(cd, I386_SAR, src, iptr);
case ICMD_ISHRCONST: /* ..., value ==> ..., value >> constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishiftconst(cd, I386_SAR, src, iptr);
break;
case ICMD_IUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishift(cd, I386_SHR, src, iptr);
case ICMD_IUSHRCONST: /* ..., value ==> ..., value >>> constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishiftconst(cd, I386_SHR, src, iptr);
break;
case ICMD_LSHL: /* ..., val1, val2 ==> ..., val1 << val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: YES EDX: S|YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ){
if (src->prev->flags & INMEMORY) {
/* if (src->prev->regoff == iptr->dst->regoff) { */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1); */
+/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */
/* if (src->flags & INMEMORY) { */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, ECX); */
+/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */
/* } else { */
/* M_INTMOVE(src->regoff, ECX); */
/* } */
/* i386_test_imm_reg(cd, 32, ECX); */
/* i386_jcc(cd, I386_CC_E, 2 + 2); */
/* i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP2); */
-/* i386_alu_reg_reg(cd, I386_XOR, REG_ITMP1, REG_ITMP1); */
+/* i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1); */
-/* i386_shld_reg_membase(cd, REG_ITMP1, REG_SP, src->prev->regoff * 8 + 4); */
-/* i386_shift_membase(cd, I386_SHL, REG_SP, iptr->dst->regoff * 8); */
+/* i386_shld_reg_membase(cd, REG_ITMP1, REG_SP, src->prev->regoff * 4 + 4); */
+/* i386_shift_membase(cd, I386_SHL, REG_SP, iptr->dst->regoff * 4); */
/* } else { */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP3);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3);
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, ECX);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX);
} else {
M_INTMOVE(src->regoff, ECX);
}
i386_test_imm_reg(cd, 32, ECX);
i386_jcc(cd, I386_CC_E, 2 + 2);
i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP3);
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP1, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
i386_shld_reg_reg(cd, REG_ITMP1, REG_ITMP3);
i386_shift_reg(cd, I386_SHL, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
/* } */
}
}
case ICMD_LSHLCONST: /* ..., value ==> ..., value << constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
if (iptr->val.i & 0x20) {
i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP2);
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP1, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1);
i386_shld_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP1, REG_ITMP2);
} else {
i386_shift_imm_reg(cd, I386_SHL, iptr->val.i & 0x3f, REG_ITMP1);
}
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
}
break;
case ICMD_LSHR: /* ..., val1, val2 ==> ..., val1 >> val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: YES S|EDX: YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ){
if (src->prev->flags & INMEMORY) {
/* if (src->prev->regoff == iptr->dst->regoff) { */
/* TODO: optimize */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1); */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP2); */
+/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */
+/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); */
/* if (src->flags & INMEMORY) { */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, ECX); */
+/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */
/* } else { */
/* M_INTMOVE(src->regoff, ECX); */
/* } */
/* i386_shrd_reg_reg(cd, REG_ITMP2, REG_ITMP1); */
/* i386_shift_reg(cd, I386_SAR, REG_ITMP2); */
-/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8); */
-/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4); */
+/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */
+/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */
/* } else { */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP3);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3);
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, ECX);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX);
} else {
M_INTMOVE(src->regoff, ECX);
}
i386_shrd_reg_reg(cd, REG_ITMP3, REG_ITMP1);
i386_shift_reg(cd, I386_SAR, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
/* } */
}
}
case ICMD_LSHRCONST: /* ..., value ==> ..., value >> constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
if (iptr->val.i & 0x20) {
i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1);
i386_shift_imm_reg(cd, I386_SAR, iptr->val.i & 0x3f, REG_ITMP2);
}
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
}
break;
case ICMD_LUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: YES EDX: S|YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ){
if (src->prev->flags & INMEMORY) {
/* if (src->prev->regoff == iptr->dst->regoff) { */
/* TODO: optimize */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1); */
-/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP2); */
+/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */
+/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); */
/* if (src->flags & INMEMORY) { */
-/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, ECX); */
+/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */
/* } else { */
/* M_INTMOVE(src->regoff, ECX); */
/* } */
/* i386_test_imm_reg(cd, 32, ECX); */
/* i386_jcc(cd, I386_CC_E, 2 + 2); */
/* i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1); */
-/* i386_alu_reg_reg(cd, I386_XOR, REG_ITMP2, REG_ITMP2); */
+/* i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2); */
/* i386_shrd_reg_reg(cd, REG_ITMP2, REG_ITMP1); */
/* i386_shift_reg(cd, I386_SHR, REG_ITMP2); */
-/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8); */
-/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4); */
+/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */
+/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */
/* } else { */
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP3);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3);
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, ECX);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX);
} else {
M_INTMOVE(src->regoff, ECX);
}
i386_test_imm_reg(cd, 32, ECX);
i386_jcc(cd, I386_CC_E, 2 + 2);
i386_mov_reg_reg(cd, REG_ITMP3, REG_ITMP1);
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP3, REG_ITMP3);
+ i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP3, REG_ITMP3);
i386_shrd_reg_reg(cd, REG_ITMP3, REG_ITMP1);
i386_shift_reg(cd, I386_SHR, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
/* } */
}
}
case ICMD_LUSHRCONST: /* ..., value ==> ..., value >>> constant */
/* val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
if (iptr->val.i & 0x20) {
i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1);
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP2, REG_ITMP2);
+ i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2);
i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1);
} else {
i386_shift_imm_reg(cd, I386_SHR, iptr->val.i & 0x3f, REG_ITMP2);
}
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4);
}
break;
case ICMD_IAND: /* ..., val1, val2 ==> ..., val1 & val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialu(cd, I386_AND, src, iptr);
+ i386_emit_ialu(cd, ALU_AND, src, iptr);
break;
case ICMD_IANDCONST: /* ..., value ==> ..., value & constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, I386_AND, src, iptr);
+ i386_emit_ialuconst(cd, ALU_AND, src, iptr);
break;
case ICMD_LAND: /* ..., val1, val2 ==> ..., val1 & val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_lalu(cd, I386_AND, src, iptr);
+ i386_emit_lalu(cd, ALU_AND, src, iptr);
break;
case ICMD_LANDCONST: /* ..., value ==> ..., value & constant */
/* val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_laluconst(cd, I386_AND, src, iptr);
+ i386_emit_laluconst(cd, ALU_AND, src, iptr);
break;
case ICMD_IOR: /* ..., val1, val2 ==> ..., val1 | val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialu(cd, I386_OR, src, iptr);
+ i386_emit_ialu(cd, ALU_OR, src, iptr);
break;
case ICMD_IORCONST: /* ..., value ==> ..., value | constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, I386_OR, src, iptr);
+ i386_emit_ialuconst(cd, ALU_OR, src, iptr);
break;
case ICMD_LOR: /* ..., val1, val2 ==> ..., val1 | val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_lalu(cd, I386_OR, src, iptr);
+ i386_emit_lalu(cd, ALU_OR, src, iptr);
break;
case ICMD_LORCONST: /* ..., value ==> ..., value | constant */
/* val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_laluconst(cd, I386_OR, src, iptr);
+ i386_emit_laluconst(cd, ALU_OR, src, iptr);
break;
case ICMD_IXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialu(cd, I386_XOR, src, iptr);
+ i386_emit_ialu(cd, ALU_XOR, src, iptr);
break;
case ICMD_IXORCONST: /* ..., value ==> ..., value ^ constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_ialuconst(cd, I386_XOR, src, iptr);
+ i386_emit_ialuconst(cd, ALU_XOR, src, iptr);
break;
case ICMD_LXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_lalu(cd, I386_XOR, src, iptr);
+ i386_emit_lalu(cd, ALU_XOR, src, iptr);
break;
case ICMD_LXORCONST: /* ..., value ==> ..., value ^ constant */
/* val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
- i386_emit_laluconst(cd, I386_XOR, src, iptr);
+ i386_emit_laluconst(cd, ALU_XOR, src, iptr);
break;
case ICMD_IINC: /* ..., value ==> ..., value + constant */
/* op1 = variable, val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL */
var = &(rd->locals[iptr->op1][TYPE_INT]);
- if (var->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_ADD, iptr->val.i, REG_SP, var->regoff * 8);
-
- } else {
- i386_alu_imm_reg(cd, I386_ADD, iptr->val.i, var->regoff);
+ if (var->flags & INMEMORY)
+ M_IADD_IMM_MEMBASE(iptr->val.i, REG_SP, var->regoff * 4);
+ else {
+ /* `inc reg' is slower on p4's (regarding to ia32
+ optimization reference manual and benchmarks) and
+ as fast on athlon's. */
+ M_IADD_IMM(iptr->val.i, var->regoff);
}
break;
#define FPU_SET_53BIT_MODE
#endif
case ICMD_FNEG: /* ..., value ==> ..., - value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_24BIT_MODE;
var_to_reg_flt(s1, src, REG_FTMP1);
break;
case ICMD_DNEG: /* ..., value ==> ..., - value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_53BIT_MODE;
var_to_reg_flt(s1, src, REG_FTMP1);
break;
case ICMD_FADD: /* ..., val1, val2 ==> ..., val1 + val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_24BIT_MODE;
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_DADD: /* ..., val1, val2 ==> ..., val1 + val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_53BIT_MODE;
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_FSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_24BIT_MODE;
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_DSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_53BIT_MODE;
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_FMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_24BIT_MODE;
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_DMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_53BIT_MODE;
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_FDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_24BIT_MODE;
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_DDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_53BIT_MODE;
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_FREM: /* ..., val1, val2 ==> ..., val1 % val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_24BIT_MODE;
/* exchanged to skip fxch */
break;
case ICMD_DREM: /* ..., val1, val2 ==> ..., val1 % val2 */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
FPU_SET_53BIT_MODE;
/* exchanged to skip fxch */
case ICMD_I2F: /* ..., value ==> ..., (float) value */
case ICMD_I2D: /* ..., value ==> ..., (double) value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (src->flags & INMEMORY) {
- i386_fildl_membase(cd, REG_SP, src->regoff * 8);
+ i386_fildl_membase(cd, REG_SP, src->regoff * 4);
fpu_st_offset++;
} else {
- a = dseg_adds4(cd, 0);
+ disp = dseg_adds4(cd, 0);
i386_mov_imm_reg(cd, 0, REG_ITMP1);
dseg_adddata(cd, cd->mcodeptr);
- i386_mov_reg_membase(cd, src->regoff, REG_ITMP1, a);
- i386_fildl_membase(cd, REG_ITMP1, a);
+ i386_mov_reg_membase(cd, src->regoff, REG_ITMP1, disp);
+ i386_fildl_membase(cd, REG_ITMP1, disp);
fpu_st_offset++;
}
store_reg_to_var_flt(iptr->dst, d);
case ICMD_L2F: /* ..., value ==> ..., (float) value */
case ICMD_L2D: /* ..., value ==> ..., (double) value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (src->flags & INMEMORY) {
- i386_fildll_membase(cd, REG_SP, src->regoff * 8);
+ i386_fildll_membase(cd, REG_SP, src->regoff * 4);
fpu_st_offset++;
} else {
- panic("L2F: longs have to be in memory");
+ log_text("L2F: longs have to be in memory");
+ assert(0);
}
store_reg_to_var_flt(iptr->dst, d);
break;
case ICMD_F2I: /* ..., value ==> ..., (int) value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: D|YES ECX: NO EDX: NO OUTPUT: EAX*/
var_to_reg_flt(s1, src, REG_FTMP1);
d = reg_of_var(rd, iptr->dst, REG_NULL);
- a = dseg_adds4(cd, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
i386_mov_imm_reg(cd, 0, REG_ITMP1);
dseg_adddata(cd, cd->mcodeptr);
- i386_fldcw_membase(cd, REG_ITMP1, a);
+
+ /* Round to zero, 53-bit mode, exception masked */
+ disp = dseg_adds4(cd, 0x0e7f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
if (iptr->dst->flags & INMEMORY) {
- i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 8);
+ i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 4);
fpu_st_offset--;
- a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
- i386_fldcw_membase(cd, REG_ITMP1, a);
+ /* Round to nearest, 53-bit mode, exceptions masked */
+ disp = dseg_adds4(cd, 0x027f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_membase(cd, I386_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4);
- a = 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 5 + 2 + 3;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
+ disp = 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 5 + 2 + 3;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
} else {
- a = dseg_adds4(cd, 0);
- i386_fistpl_membase(cd, REG_ITMP1, a);
+ disp = dseg_adds4(cd, 0);
+ i386_fistpl_membase(cd, REG_ITMP1, disp);
fpu_st_offset--;
- i386_mov_membase_reg(cd, REG_ITMP1, a, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_ITMP1, disp, iptr->dst->regoff);
- a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
- i386_fldcw_membase(cd, REG_ITMP1, a);
+ /* Round to nearest, 53-bit mode, exceptions masked */
+ disp = dseg_adds4(cd, 0x027f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_reg(cd, I386_CMP, 0x80000000, iptr->dst->regoff);
+ i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, iptr->dst->regoff);
- a = 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 5 + 2 + ((REG_RESULT == iptr->dst->regoff) ? 0 : 2);
+ disp = 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 5 + 2 + ((REG_RESULT == iptr->dst->regoff) ? 0 : 2);
}
- i386_jcc(cd, I386_CC_NE, a);
+ i386_jcc(cd, I386_CC_NE, disp);
/* XXX: change this when we use registers */
- i386_flds_membase(cd, REG_SP, src->regoff * 8);
- i386_mov_imm_reg(cd, (s4) asm_builtin_f2i, REG_ITMP1);
+ i386_flds_membase(cd, REG_SP, src->regoff * 4);
+ i386_mov_imm_reg(cd, (ptrint) asm_builtin_f2i, REG_ITMP1);
i386_call_reg(cd, REG_ITMP1);
if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
} else {
M_INTMOVE(REG_RESULT, iptr->dst->regoff);
break;
case ICMD_D2I: /* ..., value ==> ..., (int) value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: D|YES ECX: NO EDX: NO OUTPUT: EAX*/
var_to_reg_flt(s1, src, REG_FTMP1);
d = reg_of_var(rd, iptr->dst, REG_NULL);
- a = dseg_adds4(cd, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
i386_mov_imm_reg(cd, 0, REG_ITMP1);
dseg_adddata(cd, cd->mcodeptr);
- i386_fldcw_membase(cd, REG_ITMP1, a);
+
+ /* Round to zero, 53-bit mode, exception masked */
+ disp = dseg_adds4(cd, 0x0e7f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
if (iptr->dst->flags & INMEMORY) {
- i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 8);
+ i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 4);
fpu_st_offset--;
- a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
- i386_fldcw_membase(cd, REG_ITMP1, a);
+ /* Round to nearest, 53-bit mode, exceptions masked */
+ disp = dseg_adds4(cd, 0x027f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_membase(cd, I386_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4);
- a = 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 5 + 2 + 3;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
+ disp = 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 5 + 2 + 3;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
} else {
- a = dseg_adds4(cd, 0);
- i386_fistpl_membase(cd, REG_ITMP1, a);
+ disp = dseg_adds4(cd, 0);
+ i386_fistpl_membase(cd, REG_ITMP1, disp);
fpu_st_offset--;
- i386_mov_membase_reg(cd, REG_ITMP1, a, iptr->dst->regoff);
+ i386_mov_membase_reg(cd, REG_ITMP1, disp, iptr->dst->regoff);
- a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
- i386_fldcw_membase(cd, REG_ITMP1, a);
+ /* Round to nearest, 53-bit mode, exceptions masked */
+ disp = dseg_adds4(cd, 0x027f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_reg(cd, I386_CMP, 0x80000000, iptr->dst->regoff);
+ i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, iptr->dst->regoff);
- a = 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 5 + 2 + ((REG_RESULT == iptr->dst->regoff) ? 0 : 2);
+ disp = 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 5 + 2 + ((REG_RESULT == iptr->dst->regoff) ? 0 : 2);
}
- i386_jcc(cd, I386_CC_NE, a);
+ i386_jcc(cd, I386_CC_NE, disp);
/* XXX: change this when we use registers */
- i386_fldl_membase(cd, REG_SP, src->regoff * 8);
- i386_mov_imm_reg(cd, (s4) asm_builtin_d2i, REG_ITMP1);
+ i386_fldl_membase(cd, REG_SP, src->regoff * 4);
+ i386_mov_imm_reg(cd, (ptrint) asm_builtin_d2i, REG_ITMP1);
i386_call_reg(cd, REG_ITMP1);
if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
} else {
M_INTMOVE(REG_RESULT, iptr->dst->regoff);
}
break;
case ICMD_F2L: /* ..., value ==> ..., (long) value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: YES OUTPUT: REG_NULL*/
var_to_reg_flt(s1, src, REG_FTMP1);
d = reg_of_var(rd, iptr->dst, REG_NULL);
- a = dseg_adds4(cd, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
i386_mov_imm_reg(cd, 0, REG_ITMP1);
dseg_adddata(cd, cd->mcodeptr);
- i386_fldcw_membase(cd, REG_ITMP1, a);
+
+ /* Round to zero, 53-bit mode, exception masked */
+ disp = dseg_adds4(cd, 0x0e7f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
if (iptr->dst->flags & INMEMORY) {
- i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 8);
+ i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 4);
fpu_st_offset--;
- a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
- i386_fldcw_membase(cd, REG_ITMP1, a);
+ /* Round to nearest, 53-bit mode, exceptions masked */
+ disp = dseg_adds4(cd, 0x027f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_membase(cd, I386_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4 + 4);
- a = 6 + 4;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
- a += 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 5 + 2;
- a += 3;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
- a += 3;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8 + 4);
+ disp = 6 + 4;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ disp += 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 5 + 2;
+ disp += 3;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ disp += 3;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4 + 4);
- i386_jcc(cd, I386_CC_NE, a);
+ i386_jcc(cd, I386_CC_NE, disp);
- i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, iptr->dst->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->dst->regoff * 4);
- a = 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 5 + 2 + 3;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
+ disp = 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 5 + 2 + 3;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
- i386_jcc(cd, I386_CC_NE, a);
+ i386_jcc(cd, I386_CC_NE, disp);
/* XXX: change this when we use registers */
- i386_flds_membase(cd, REG_SP, src->regoff * 8);
- i386_mov_imm_reg(cd, (s4) asm_builtin_f2l, REG_ITMP1);
+ i386_flds_membase(cd, REG_SP, src->regoff * 4);
+ i386_mov_imm_reg(cd, (ptrint) asm_builtin_f2l, REG_ITMP1);
i386_call_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
- panic("F2L: longs have to be in memory");
+ log_text("F2L: longs have to be in memory");
+ assert(0);
}
break;
case ICMD_D2L: /* ..., value ==> ..., (long) value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: YES OUTPUT: REG_NULL*/
var_to_reg_flt(s1, src, REG_FTMP1);
d = reg_of_var(rd, iptr->dst, REG_NULL);
- a = dseg_adds4(cd, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
i386_mov_imm_reg(cd, 0, REG_ITMP1);
dseg_adddata(cd, cd->mcodeptr);
- i386_fldcw_membase(cd, REG_ITMP1, a);
+
+ /* Round to zero, 53-bit mode, exception masked */
+ disp = dseg_adds4(cd, 0x0e7f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
if (iptr->dst->flags & INMEMORY) {
- i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 8);
+ i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 4);
fpu_st_offset--;
- a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
- i386_fldcw_membase(cd, REG_ITMP1, a);
+ /* Round to nearest, 53-bit mode, exceptions masked */
+ disp = dseg_adds4(cd, 0x027f);
+ i386_fldcw_membase(cd, REG_ITMP1, disp);
- i386_alu_imm_membase(cd, I386_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4 + 4);
- a = 6 + 4;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
- a += 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 5 + 2;
- a += 3;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
- a += 3;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8 + 4);
+ disp = 6 + 4;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ disp += 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 5 + 2;
+ disp += 3;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
+ disp += 3;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4 + 4);
- i386_jcc(cd, I386_CC_NE, a);
+ i386_jcc(cd, I386_CC_NE, disp);
- i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, iptr->dst->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->dst->regoff * 4);
- a = 3;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- a += 5 + 2 + 3;
- CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
+ disp = 3;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ disp += 5 + 2 + 3;
+ CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4);
- i386_jcc(cd, I386_CC_NE, a);
+ i386_jcc(cd, I386_CC_NE, disp);
/* XXX: change this when we use registers */
- i386_fldl_membase(cd, REG_SP, src->regoff * 8);
- i386_mov_imm_reg(cd, (s4) asm_builtin_d2l, REG_ITMP1);
+ i386_fldl_membase(cd, REG_SP, src->regoff * 4);
+ i386_mov_imm_reg(cd, (ptrint) asm_builtin_d2l, REG_ITMP1);
i386_call_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4);
} else {
- panic("D2L: longs have to be in memory");
+ log_text("D2L: longs have to be in memory");
+ assert(0);
}
break;
case ICMD_F2D: /* ..., value ==> ..., (double) value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
var_to_reg_flt(s1, src, REG_FTMP1);
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
break;
case ICMD_D2F: /* ..., value ==> ..., (float) value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/
var_to_reg_flt(s1, src, REG_FTMP1);
d = reg_of_var(rd, iptr->dst, REG_FTMP3);
case ICMD_FCMPL: /* ..., val1, val2 ==> ..., val1 fcmpl val2 */
case ICMD_DCMPL:
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
/* exchanged to skip fxch */
var_to_reg_flt(s2, src->prev, REG_FTMP1);
i386_fnstsw(cd);
i386_test_imm_reg(cd, 0x400, EAX); /* unordered treat as GT */
i386_jcc(cd, I386_CC_E, 6);
- i386_alu_imm_reg(cd, I386_AND, 0x000000ff, EAX);
+ i386_alu_imm_reg(cd, ALU_AND, 0x000000ff, EAX);
i386_sahf(cd);
i386_mov_imm_reg(cd, 0, d); /* does not affect flags */
i386_jcc(cd, I386_CC_E, 6 + 3 + 5 + 3);
i386_jcc(cd, I386_CC_B, 3 + 5);
- i386_alu_imm_reg(cd, I386_SUB, 1, d);
+ i386_alu_imm_reg(cd, ALU_SUB, 1, d);
i386_jmp_imm(cd, 3);
- i386_alu_imm_reg(cd, I386_ADD, 1, d);
+ i386_alu_imm_reg(cd, ALU_ADD, 1, d);
store_reg_to_var_int(iptr->dst, d);
break;
case ICMD_FCMPG: /* ..., val1, val2 ==> ..., val1 fcmpg val2 */
case ICMD_DCMPG:
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
/* exchanged to skip fxch */
var_to_reg_flt(s2, src->prev, REG_FTMP1);
i386_fnstsw(cd);
i386_test_imm_reg(cd, 0x400, EAX); /* unordered treat as LT */
i386_jcc(cd, I386_CC_E, 3);
- i386_movb_imm_reg(cd, 1, I386_AH);
+ i386_movb_imm_reg(cd, 1, REG_AH);
i386_sahf(cd);
i386_mov_imm_reg(cd, 0, d); /* does not affect flags */
i386_jcc(cd, I386_CC_E, 6 + 3 + 5 + 3);
i386_jcc(cd, I386_CC_B, 3 + 5);
- i386_alu_imm_reg(cd, I386_SUB, 1, d);
+ i386_alu_imm_reg(cd, ALU_SUB, 1, d);
i386_jmp_imm(cd, 3);
- i386_alu_imm_reg(cd, I386_ADD, 1, d);
+ i386_alu_imm_reg(cd, ALU_ADD, 1, d);
store_reg_to_var_int(iptr->dst, d);
break;
/* memory operations **************************************************/
case ICMD_ARRAYLENGTH: /* ..., arrayref ==> ..., length */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src, REG_ITMP1);
d = reg_of_var(rd, iptr->dst, REG_ITMP1);
break;
case ICMD_AALOAD: /* ..., arrayref, index ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_LALOAD: /* ..., arrayref, index ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
if (iptr->dst->flags & INMEMORY) {
i386_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]), s1, s2, 3, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4);
i386_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3, REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
}
break;
case ICMD_IALOAD: /* ..., arrayref, index ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_FALOAD: /* ..., arrayref, index ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_DALOAD: /* ..., arrayref, index ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_CALOAD: /* ..., arrayref, index ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_SALOAD: /* ..., arrayref, index ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_BALOAD: /* ..., arrayref, index ==> ..., value */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
- case ICMD_AASTORE: /* ..., arrayref, index, value ==> ... */
-
- var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
- var_to_reg_int(s2, src->prev, REG_ITMP2);
- if (iptr->op1 == 0) {
- gen_nullptr_check(s1);
- gen_bound_check;
- }
- var_to_reg_int(s3, src, REG_ITMP3);
- i386_mov_reg_memindex(cd, s3, OFFSET(java_objectarray, data[0]), s1, s2, 2);
- break;
-
case ICMD_LASTORE: /* ..., arrayref, index, value ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */
var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
var_to_reg_int(s2, src->prev, REG_ITMP2);
}
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP3);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP3);
i386_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0]), s1, s2, 3);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP3);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP3);
i386_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3);
}
break;
case ICMD_IASTORE: /* ..., arrayref, index, value ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
var_to_reg_int(s2, src->prev, REG_ITMP2);
break;
case ICMD_FASTORE: /* ..., arrayref, index, value ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
var_to_reg_int(s2, src->prev, REG_ITMP2);
break;
case ICMD_DASTORE: /* ..., arrayref, index, value ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
var_to_reg_int(s2, src->prev, REG_ITMP2);
break;
case ICMD_CASTORE: /* ..., arrayref, index, value ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
var_to_reg_int(s2, src->prev, REG_ITMP2);
break;
case ICMD_SASTORE: /* ..., arrayref, index, value ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
var_to_reg_int(s2, src->prev, REG_ITMP2);
break;
case ICMD_BASTORE: /* ..., arrayref, index, value ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
var_to_reg_int(s2, src->prev, REG_ITMP2);
i386_movb_reg_memindex(cd, s3, OFFSET(java_bytearray, data[0]), s1, s2, 0);
break;
+ case ICMD_AASTORE: /* ..., arrayref, index, value ==> ... */
+
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */
+
+ var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
+ var_to_reg_int(s2, src->prev, REG_ITMP2);
+ if (iptr->op1 == 0) {
+ gen_nullptr_check(s1);
+ gen_bound_check;
+ }
+ var_to_reg_int(s3, src, REG_ITMP3);
+
+ M_AST(s1, REG_SP, 0 * 4);
+ M_AST(s3, REG_SP, 1 * 4);
+ M_MOV_IMM((ptrint) BUILTIN_canstore, REG_ITMP1);
+ M_CALL(REG_ITMP1);
+ M_TEST(REG_RESULT);
+ M_BEQ(0);
+ codegen_addxstorerefs(cd, cd->mcodeptr);
+
+ var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
+ var_to_reg_int(s2, src->prev, REG_ITMP2);
+ var_to_reg_int(s3, src, REG_ITMP3);
+ i386_mov_reg_memindex(cd, s3, OFFSET(java_objectarray, data[0]), s1, s2, 2);
+ break;
+
case ICMD_IASTORECONST: /* ..., arrayref, index ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_LASTORECONST: /* ..., arrayref, index ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_AASTORECONST: /* ..., arrayref, index ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_BASTORECONST: /* ..., arrayref, index ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_CASTORECONST: /* ..., arrayref, index ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
case ICMD_SASTORECONST: /* ..., arrayref, index ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
break;
+ case ICMD_GETSTATIC: /* ... ==> ..., value */
+ /* op1 = type, val.a = field address */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EAX*/
+
+ if (iptr->val.a == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_get_putstatic,
+ (unresolved_field *) iptr->target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ disp = 0;
+
+ } else {
+ fieldinfo *fi = iptr->val.a;
+
+ if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_clinit, fi->class, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
+
+ disp = (ptrint) &(fi->value);
+ }
+
+ M_MOV_IMM(disp, REG_ITMP1);
+ switch (iptr->op1) {
+ case TYPE_INT:
+ case TYPE_ADR:
+ d = reg_of_var(rd, iptr->dst, REG_ITMP2);
+ M_ILD(d, REG_ITMP1, 0);
+ store_reg_to_var_int(iptr->dst, d);
+ break;
+ case TYPE_LNG:
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
+ if (iptr->dst->flags & INMEMORY) {
+ /* Using both REG_ITMP2 and REG_ITMP3 is faster
+ than only using REG_ITMP2 alternating. */
+ i386_mov_membase_reg(cd, REG_ITMP1, 0, REG_ITMP2);
+ i386_mov_membase_reg(cd, REG_ITMP1, 4, REG_ITMP3);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
+ } else {
+ log_text("GETSTATIC: longs have to be in memory");
+ assert(0);
+ }
+ break;
+ case TYPE_FLT:
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
+ i386_flds_membase(cd, REG_ITMP1, 0);
+ fpu_st_offset++;
+ store_reg_to_var_flt(iptr->dst, d);
+ break;
+ case TYPE_DBL:
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
+ i386_fldl_membase(cd, REG_ITMP1, 0);
+ fpu_st_offset++;
+ store_reg_to_var_flt(iptr->dst, d);
+ break;
+ }
+ break;
+
case ICMD_PUTSTATIC: /* ..., value ==> ... */
/* op1 = type, val.a = field address */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
+
+ if (iptr->val.a == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_get_putstatic,
+ (unresolved_field *) iptr->target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ disp = 0;
+
+ } else {
+ fieldinfo *fi = iptr->val.a;
- /* if class isn't yet initialized, do it */
- if (!((fieldinfo *) iptr->val.a)->class->initialized) {
- /* call helper function which patches this code */
- i386_mov_imm_reg(cd, (s4) ((fieldinfo *) iptr->val.a)->class, REG_ITMP1);
- i386_mov_imm_reg(cd, (s4) asm_check_clinit, REG_ITMP2);
- i386_call_reg(cd, REG_ITMP2);
+ if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_clinit, fi->class, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
+
+ disp = (ptrint) &(fi->value);
}
- a = dseg_addaddress(cd, &(((fieldinfo *) iptr->val.a)->value));
- /* here it's slightly slower */
- i386_mov_imm_reg(cd, 0, REG_ITMP2);
- dseg_adddata(cd, cd->mcodeptr);
- i386_mov_membase_reg(cd, REG_ITMP2, a, REG_ITMP2);
+ M_MOV_IMM(disp, REG_ITMP1);
switch (iptr->op1) {
case TYPE_INT:
case TYPE_ADR:
- var_to_reg_int(s2, src, REG_ITMP1);
- i386_mov_reg_membase(cd, s2, REG_ITMP2, 0);
+ var_to_reg_int(s2, src, REG_ITMP2);
+ M_IST(s2, REG_ITMP1, 0);
break;
case TYPE_LNG:
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_ITMP2, 0);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_ITMP2, 0 + 4);
+ /* Using both REG_ITMP2 and REG_ITMP3 is faster
+ than only using REG_ITMP2 alternating. */
+ s2 = src->regoff;
+
+ i386_mov_membase_reg(cd, REG_SP, s2 * 4, REG_ITMP2);
+ i386_mov_membase_reg(cd, REG_SP, s2 * 4 + 4, REG_ITMP3);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_ITMP1, 0);
+ i386_mov_reg_membase(cd, REG_ITMP3, REG_ITMP1, 4);
} else {
- panic("PUTSTATIC: longs have to be in memory");
+ log_text("PUTSTATIC: longs have to be in memory");
+ assert(0);
}
break;
case TYPE_FLT:
var_to_reg_flt(s2, src, REG_FTMP1);
- i386_fstps_membase(cd, REG_ITMP2, 0);
+ i386_fstps_membase(cd, REG_ITMP1, 0);
fpu_st_offset--;
break;
case TYPE_DBL:
var_to_reg_flt(s2, src, REG_FTMP1);
- i386_fstpl_membase(cd, REG_ITMP2, 0);
+ i386_fstpl_membase(cd, REG_ITMP1, 0);
fpu_st_offset--;
break;
- default: panic ("internal error");
}
break;
- case ICMD_GETSTATIC: /* ... ==> ..., value */
- /* op1 = type, val.a = field address */
+ case ICMD_PUTSTATICCONST: /* ... ==> ... */
+ /* val = value (in current instruction) */
+ /* op1 = type, val.a = field address (in */
+ /* following NOP) */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
+
+ if (iptr[1].val.a == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_get_putstatic,
+ (unresolved_field *) iptr[1].target, 0);
- /* if class isn't yet initialized, do it */
- if (!((fieldinfo *) iptr->val.a)->class->initialized) {
- /* call helper function which patches this code */
- i386_mov_imm_reg(cd, (s4) ((fieldinfo *) iptr->val.a)->class, REG_ITMP1);
- i386_mov_imm_reg(cd, (s4) asm_check_clinit, REG_ITMP2);
- i386_call_reg(cd, REG_ITMP2);
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ disp = 0;
+
+ } else {
+ fieldinfo *fi = iptr[1].val.a;
+
+ if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_clinit, fi->class, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
+
+ disp = (ptrint) &(fi->value);
+ }
+
+ M_MOV_IMM(disp, REG_ITMP1);
+ switch (iptr[1].op1) {
+ case TYPE_INT:
+ case TYPE_FLT:
+ case TYPE_ADR:
+ i386_mov_imm_membase(cd, iptr->val.i, REG_ITMP1, 0);
+ break;
+ case TYPE_LNG:
+ case TYPE_DBL:
+ i386_mov_imm_membase(cd, iptr->val.l, REG_ITMP1, 0);
+ i386_mov_imm_membase(cd, iptr->val.l >> 32, REG_ITMP1, 4);
+ break;
+ }
+ break;
+
+ case ICMD_GETFIELD: /* .., objectref. ==> ..., value */
+ /* op1 = type, val.i = field offset */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */
+
+ var_to_reg_int(s1, src, REG_ITMP1);
+ gen_nullptr_check(s1);
+
+ if (iptr->val.a == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_getfield,
+ (unresolved_field *) iptr->target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ disp = 0;
+
+ } else {
+ disp = ((fieldinfo *) (iptr->val.a))->offset;
}
- a = dseg_addaddress(cd, &(((fieldinfo *) iptr->val.a)->value));
- i386_mov_imm_reg(cd, 0, REG_ITMP2);
- dseg_adddata(cd, cd->mcodeptr);
- i386_mov_membase_reg(cd, REG_ITMP2, a, REG_ITMP2);
switch (iptr->op1) {
case TYPE_INT:
case TYPE_ADR:
- d = reg_of_var(rd, iptr->dst, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP2, 0, d);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP2);
+ i386_mov_membase32_reg(cd, s1, disp, d);
store_reg_to_var_int(iptr->dst, d);
break;
case TYPE_LNG:
d = reg_of_var(rd, iptr->dst, REG_NULL);
- if (iptr->dst->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_ITMP2, 0, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_ITMP2, 0 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
- } else {
- panic("GETSTATIC: longs have to be in memory");
- }
+ i386_mov_membase32_reg(cd, s1, disp, REG_ITMP2);
+ i386_mov_membase32_reg(cd, s1, disp + 4, REG_ITMP3);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4);
break;
case TYPE_FLT:
d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- i386_flds_membase(cd, REG_ITMP2, 0);
+ i386_flds_membase32(cd, s1, disp);
fpu_st_offset++;
store_reg_to_var_flt(iptr->dst, d);
break;
case TYPE_DBL:
d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- i386_fldl_membase(cd, REG_ITMP2, 0);
+ i386_fldl_membase32(cd, s1, disp);
fpu_st_offset++;
store_reg_to_var_flt(iptr->dst, d);
break;
- default: panic ("internal error");
}
break;
- case ICMD_PUTFIELD: /* ..., value ==> ... */
- /* op1 = type, val.i = field offset */
+ case ICMD_PUTFIELD: /* ..., objectref, value ==> ... */
+ /* op1 = type, val.a = field address */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
+
+ var_to_reg_int(s1, src->prev, REG_ITMP1);
+ gen_nullptr_check(s1);
+
+ if ((iptr->op1 == TYPE_INT) || IS_ADR_TYPE(iptr->op1)) {
+ var_to_reg_int(s2, src, REG_ITMP2);
+ } else if (IS_FLT_DBL_TYPE(iptr->op1)) {
+ var_to_reg_flt(s2, src, REG_FTMP2);
+ }
+
+ if (iptr->val.a == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_putfield,
+ (unresolved_field *) iptr->target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ disp = 0;
+
+ } else {
+ disp = ((fieldinfo *) (iptr->val.a))->offset;
+ }
- a = ((fieldinfo *)(iptr->val.a))->offset;
switch (iptr->op1) {
- case TYPE_INT:
- case TYPE_ADR:
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- gen_nullptr_check(s1);
- i386_mov_reg_membase(cd, s2, s1, a);
- break;
- case TYPE_LNG:
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- gen_nullptr_check(s1);
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, s1, a);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, s1, a + 4);
- } else {
- panic("PUTFIELD: longs have to be in memory");
- }
- break;
- case TYPE_FLT:
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_flt(s2, src, REG_FTMP1);
- gen_nullptr_check(s1);
- i386_fstps_membase(cd, s1, a);
- fpu_st_offset--;
- break;
- case TYPE_DBL:
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_flt(s2, src, REG_FTMP1);
- gen_nullptr_check(s1);
- i386_fstpl_membase(cd, s1, a);
- fpu_st_offset--;
- break;
- default: panic ("internal error");
+ case TYPE_INT:
+ case TYPE_ADR:
+ i386_mov_reg_membase32(cd, s2, s1, disp);
+ break;
+ case TYPE_LNG:
+ if (src->flags & INMEMORY) {
+ i386_mov_membase32_reg(cd, REG_SP, src->regoff * 4, REG_ITMP2);
+ i386_mov_membase32_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP3);
+ i386_mov_reg_membase32(cd, REG_ITMP2, s1, disp);
+ i386_mov_reg_membase32(cd, REG_ITMP3, s1, disp + 4);
+ } else {
+ log_text("PUTFIELD: longs have to be in memory");
+ assert(0);
}
+ break;
+ case TYPE_FLT:
+ i386_fstps_membase32(cd, s1, disp);
+ fpu_st_offset--;
+ break;
+ case TYPE_DBL:
+ i386_fstpl_membase32(cd, s1, disp);
+ fpu_st_offset--;
+ break;
+ }
break;
- case ICMD_GETFIELD: /* ... ==> ..., value */
- /* op1 = type, val.i = field offset */
+ case ICMD_PUTFIELDCONST: /* ..., objectref ==> ... */
+ /* val = value (in current instruction) */
+ /* op1 = type, val.a = field address (in */
+ /* following NOP) */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/
- a = ((fieldinfo *)(iptr->val.a))->offset;
- switch (iptr->op1) {
- case TYPE_INT:
- case TYPE_ADR:
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_ITMP2);
- gen_nullptr_check(s1);
- i386_mov_membase_reg(cd, s1, a, d);
- store_reg_to_var_int(iptr->dst, d);
- break;
- case TYPE_LNG:
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_NULL);
- gen_nullptr_check(s1);
- i386_mov_membase_reg(cd, s1, a, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, s1, a + 4, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
- break;
- case TYPE_FLT:
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- gen_nullptr_check(s1);
- i386_flds_membase(cd, s1, a);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
- break;
- case TYPE_DBL:
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_FTMP1);
- gen_nullptr_check(s1);
- i386_fldl_membase(cd, s1, a);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
- break;
- default: panic ("internal error");
+ var_to_reg_int(s1, src, REG_ITMP1);
+ gen_nullptr_check(s1);
+
+ if (iptr[1].val.a == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_putfieldconst,
+ (unresolved_field *) iptr[1].target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
+
+ disp = 0;
+
+ } else {
+ disp = ((fieldinfo *) (iptr[1].val.a))->offset;
+ }
+
+ switch (iptr[1].op1) {
+ case TYPE_INT:
+ case TYPE_FLT:
+ case TYPE_ADR:
+ i386_mov_imm_membase32(cd, iptr->val.i, s1, disp);
+ break;
+ case TYPE_LNG:
+ case TYPE_DBL:
+ i386_mov_imm_membase32(cd, iptr->val.l, s1, disp);
+ i386_mov_imm_membase32(cd, iptr->val.l >> 32, s1, disp + 4);
+ break;
+ }
break;
/* branch operations **************************************************/
- /* TWISTI */
-/* #define ALIGNCODENOP {if((int)((long)cd->mcodeptr&7)){M_NOP;}} */
-#define ALIGNCODENOP do {} while (0)
-
case ICMD_ATHROW: /* ..., objectref ==> ... (, objectref) */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */
var_to_reg_int(s1, src, REG_ITMP1);
M_INTMOVE(s1, REG_ITMP1_XPTR);
- i386_call_imm(cd, 0); /* passing exception pointer */
- i386_pop_reg(cd, REG_ITMP2_XPC);
+#ifdef ENABLE_VERIFIER
+ if (iptr->val.a) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_athrow_areturn,
+ (unresolved_class *) iptr->val.a, 0);
- i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3);
- ALIGNCODENOP;
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
+#endif /* ENABLE_VERIFIER */
+
+ M_CALL_IMM(0); /* passing exception pc */
+ M_POP(REG_ITMP2_XPC);
+
+ M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
break;
case ICMD_GOTO: /* ... ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
i386_jmp_imm(cd, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
- ALIGNCODENOP;
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_JSR: /* ... ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
i386_call_imm(cd, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_RET: /* ... ==> ... */
/* op1 = local variable */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
var = &(rd->locals[iptr->op1][TYPE_ADR]);
var_to_reg_int(s1, var, REG_ITMP1);
case ICMD_IFNULL: /* ..., value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4);
} else {
i386_test_reg_reg(cd, src->regoff, src->regoff);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IFNONNULL: /* ..., value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4);
} else {
i386_test_reg_reg(cd, src->regoff, src->regoff);
}
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IFEQ: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.i, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
} else {
- i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
+ i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IFLT: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.i, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
} else {
- i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
+ i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IFLE: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.i, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
} else {
- i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
+ i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_LE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IFNE: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.i, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
} else {
- i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
+ i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IFGT: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.i, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
} else {
- i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
+ i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IFGE: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.i, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4);
} else {
- i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
+ i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_GE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LEQ: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
if (iptr->val.l == 0) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_OR, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_OR, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
} else {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
- i386_alu_imm_reg(cd, I386_XOR, iptr->val.l >> 32, REG_ITMP2);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_XOR, iptr->val.l, REG_ITMP1);
- i386_alu_reg_reg(cd, I386_OR, REG_ITMP2, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
+ i386_alu_imm_reg(cd, ALU_XOR, iptr->val.l >> 32, REG_ITMP2);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_XOR, iptr->val.l, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1);
}
}
i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LLT: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 8 + 4);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4);
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- a = 3 + 6;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- CALCIMMEDIATEBYTES(a, iptr->val.l);
+ disp = 3 + 6;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCIMMEDIATEBYTES(disp, iptr->val.l);
- i386_jcc(cd, I386_CC_G, a);
+ i386_jcc(cd, I386_CC_G, disp);
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.l, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4);
i386_jcc(cd, I386_CC_B, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
}
break;
case ICMD_IF_LLE: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 8 + 4);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4);
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- a = 3 + 6;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- CALCIMMEDIATEBYTES(a, iptr->val.l);
+ disp = 3 + 6;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCIMMEDIATEBYTES(disp, iptr->val.l);
- i386_jcc(cd, I386_CC_G, a);
+ i386_jcc(cd, I386_CC_G, disp);
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.l, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4);
i386_jcc(cd, I386_CC_BE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
}
break;
case ICMD_IF_LNE: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
if (iptr->val.l == 0) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_OR, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_OR, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
} else {
i386_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_XOR, REG_SP, src->regoff * 8, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1);
i386_mov_imm_reg(cd, iptr->val.l >> 32, REG_ITMP2);
- i386_alu_membase_reg(cd, I386_XOR, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
- i386_alu_reg_reg(cd, I386_OR, REG_ITMP2, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
+ i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1);
}
}
i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LGT: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 8 + 4);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4);
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- a = 3 + 6;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- CALCIMMEDIATEBYTES(a, iptr->val.l);
+ disp = 3 + 6;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCIMMEDIATEBYTES(disp, iptr->val.l);
- i386_jcc(cd, I386_CC_L, a);
+ i386_jcc(cd, I386_CC_L, disp);
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.l, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4);
i386_jcc(cd, I386_CC_A, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
}
break;
case ICMD_IF_LGE: /* ..., value ==> ... */
/* op1 = target JavaVM pc, val.l = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 8 + 4);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4);
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- a = 3 + 6;
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
- CALCIMMEDIATEBYTES(a, iptr->val.l);
+ disp = 3 + 6;
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
+ CALCIMMEDIATEBYTES(disp, iptr->val.l);
- i386_jcc(cd, I386_CC_L, a);
+ i386_jcc(cd, I386_CC_L, disp);
- i386_alu_imm_membase(cd, I386_CMP, iptr->val.l, REG_SP, src->regoff * 8);
+ i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4);
i386_jcc(cd, I386_CC_AE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
}
break;
case ICMD_IF_ICMPEQ: /* ..., value, value ==> ... */
case ICMD_IF_ACMPEQ: /* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, src->prev->regoff);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, I386_CMP, src->regoff, REG_SP, src->prev->regoff * 8);
+ i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
} else {
- i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
+ i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LCMPEQ: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP2);
- i386_alu_membase_reg(cd, I386_XOR, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_XOR, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
- i386_alu_reg_reg(cd, I386_OR, REG_ITMP2, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2);
+ i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
+ i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1);
i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_ICMPNE: /* ..., value, value ==> ... */
case ICMD_IF_ACMPNE: /* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, src->prev->regoff);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, I386_CMP, src->regoff, REG_SP, src->prev->regoff * 8);
+ i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
} else {
- i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
+ i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LCMPNE: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP2);
- i386_alu_membase_reg(cd, I386_XOR, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_XOR, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
- i386_alu_reg_reg(cd, I386_OR, REG_ITMP2, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2);
+ i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2);
+ i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1);
i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
}
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_ICMPLT: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, src->prev->regoff);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, I386_CMP, src->regoff, REG_SP, src->prev->regoff * 8);
+ i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
} else {
- i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
+ i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LCMPLT: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ M_BLT(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- a = 3 + 3 + 6;
- CALCOFFSETBYTES(a, REG_SP, src->prev->regoff * 8);
- CALCOFFSETBYTES(a, REG_SP, src->regoff);
+ disp = 3 + 3 + 6;
+ CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- i386_jcc(cd, I386_CC_G, a);
+ M_BGT(disp);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1);
i386_jcc(cd, I386_CC_B, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
}
break;
case ICMD_IF_ICMPGT: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, src->prev->regoff);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, I386_CMP, src->regoff, REG_SP, src->prev->regoff * 8);
+ i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
} else {
- i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
+ i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
}
- i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ M_BGT(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LCMPGT: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ M_BGT(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- a = 3 + 3 + 6;
- CALCOFFSETBYTES(a, REG_SP, src->prev->regoff * 8);
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
+ disp = 3 + 3 + 6;
+ CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- i386_jcc(cd, I386_CC_L, a);
+ M_BLT(disp);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1);
i386_jcc(cd, I386_CC_A, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
}
break;
case ICMD_IF_ICMPLE: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, src->prev->regoff);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, I386_CMP, src->regoff, REG_SP, src->prev->regoff * 8);
+ i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
} else {
- i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
+ i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
}
- i386_jcc(cd, I386_CC_LE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ M_BLE(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LCMPLE: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ M_BLT(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- a = 3 + 3 + 6;
- CALCOFFSETBYTES(a, REG_SP, src->prev->regoff * 8);
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
+ disp = 3 + 3 + 6;
+ CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- i386_jcc(cd, I386_CC_G, a);
+ M_BGT(disp);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_jcc(cd, I386_CC_BE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1);
+ M_BBE(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
}
break;
case ICMD_IF_ICMPGE: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_alu_reg_membase(cd, I386_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 8);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4);
} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, src->prev->regoff);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff);
} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_alu_reg_membase(cd, I386_CMP, src->regoff, REG_SP, src->prev->regoff * 8);
+ i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4);
} else {
- i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
+ i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff);
}
- i386_jcc(cd, I386_CC_GE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ M_BGE(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
break;
case ICMD_IF_LCMPGE: /* ..., value, value ==> ... */
/* op1 = target JavaVM pc */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1);
+ M_BGT(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
- a = 3 + 3 + 6;
- CALCOFFSETBYTES(a, REG_SP, src->prev->regoff * 8);
- CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
+ disp = 3 + 3 + 6;
+ CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4);
+ CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4);
- i386_jcc(cd, I386_CC_L, a);
+ M_BLT(disp);
- i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
- i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_jcc(cd, I386_CC_AE, 0);
- codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1);
+ i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1);
+ M_BAE(0);
+ codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr);
}
break;
/* (value xx 0) ? IFxx_ICONST : ELSE_ICONST */
case ICMD_ELSE_ICONST: /* handled by IFxx_ICONST */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
break;
case ICMD_IFEQ_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_NE, src, iptr);
case ICMD_IFNE_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_E, src, iptr);
case ICMD_IFLT_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_GE, src, iptr);
case ICMD_IFGE_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_L, src, iptr);
case ICMD_IFGT_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_LE, src, iptr);
case ICMD_IFLE_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_G, src, iptr);
case ICMD_IRETURN: /* ..., retvalue ==> ... */
- case ICMD_ARETURN:
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */
var_to_reg_int(s1, src, REG_RESULT);
M_INTMOVE(s1, REG_RESULT);
-
goto nowperformreturn;
case ICMD_LRETURN: /* ..., retvalue ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_RESULT);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_RESULT2);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_RESULT);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_RESULT2);
} else {
- panic("LRETURN: longs have to be in memory");
+ log_text("LRETURN: longs have to be in memory");
+ assert(0);
}
+ goto nowperformreturn;
+
+ case ICMD_ARETURN: /* ..., retvalue ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */
+ var_to_reg_int(s1, src, REG_RESULT);
+ M_INTMOVE(s1, REG_RESULT);
+
+#ifdef ENABLE_VERIFIER
+ if (iptr->val.a) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_athrow_areturn,
+ (unresolved_class *) iptr->val.a, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
+#endif /* ENABLE_VERIFIER */
goto nowperformreturn;
case ICMD_FRETURN: /* ..., retvalue ==> ... */
- case ICMD_DRETURN: /* ..., retvalue ==> ... */
+ case ICMD_DRETURN:
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */
var_to_reg_flt(s1, src, REG_FRESULT);
/* this may be an early return -- keep the offset correct for the
remaining code */
fpu_st_offset--;
-
goto nowperformreturn;
case ICMD_RETURN: /* ... ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
nowperformreturn:
{
/* call trace function */
if (runverbose) {
- i386_alu_imm_reg(cd, I386_SUB, 4 + 8 + 8 + 4, REG_SP);
+ i386_alu_imm_reg(cd, ALU_SUB, 4 + 8 + 8 + 4, REG_SP);
i386_mov_imm_membase(cd, (s4) m, REG_SP, 0);
i386_mov_membase_reg(cd, REG_SP, 4, REG_RESULT);
i386_mov_membase_reg(cd, REG_SP, 4 + 4, REG_RESULT2);
- i386_alu_imm_reg(cd, I386_ADD, 4 + 8 + 8 + 4, REG_SP);
+ i386_alu_imm_reg(cd, ALU_ADD, 4 + 8 + 8 + 4, REG_SP);
}
#if defined(USE_THREADS)
if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
- i386_mov_membase_reg(cd, REG_SP, 8 * rd->maxmemuse, REG_ITMP2);
+ M_ALD(REG_ITMP2, REG_SP, rd->memuse * 4);
/* we need to save the proper return value */
switch (iptr->opc) {
case ICMD_IRETURN:
case ICMD_ARETURN:
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, rd->maxmemuse * 8);
+ M_IST(REG_RESULT, REG_SP, rd->memuse * 4);
break;
case ICMD_LRETURN:
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, rd->maxmemuse * 8);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, rd->maxmemuse * 8 + 4);
+ M_IST(REG_RESULT, REG_SP, rd->memuse * 4);
+ M_IST(REG_RESULT2, REG_SP, rd->memuse * 4 + 4);
break;
case ICMD_FRETURN:
- i386_fsts_membase(cd, REG_SP, rd->maxmemuse * 8);
+ i386_fstps_membase(cd, REG_SP, rd->memuse * 4);
break;
case ICMD_DRETURN:
- i386_fstl_membase(cd, REG_SP, rd->maxmemuse * 8);
+ i386_fstpl_membase(cd, REG_SP, rd->memuse * 4);
break;
}
- i386_alu_imm_reg(cd, I386_SUB, 4, REG_SP);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, 0);
- i386_mov_imm_reg(cd, (s4) builtin_monitorexit, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADD, 4, REG_SP);
+ M_AST(REG_ITMP2, REG_SP, 0);
+ M_MOV_IMM((ptrint) BUILTIN_monitorexit, REG_ITMP1);
+ M_CALL(REG_ITMP1);
/* and now restore the proper return value */
switch (iptr->opc) {
case ICMD_IRETURN:
case ICMD_ARETURN:
- i386_mov_membase_reg(cd, REG_SP, rd->maxmemuse * 8, REG_RESULT);
+ M_ILD(REG_RESULT, REG_SP, rd->memuse * 4);
break;
case ICMD_LRETURN:
- i386_mov_membase_reg(cd, REG_SP, rd->maxmemuse * 8, REG_RESULT);
- i386_mov_membase_reg(cd, REG_SP, rd->maxmemuse * 8 + 4, REG_RESULT2);
+ M_ILD(REG_RESULT, REG_SP, rd->memuse * 4);
+ M_ILD(REG_RESULT2, REG_SP, rd->memuse * 4 + 4);
break;
case ICMD_FRETURN:
- i386_flds_membase(cd, REG_SP, rd->maxmemuse * 8);
+ i386_flds_membase(cd, REG_SP, rd->memuse * 4);
break;
case ICMD_DRETURN:
- i386_fldl_membase(cd, REG_SP, rd->maxmemuse * 8);
+ i386_fldl_membase(cd, REG_SP, rd->memuse * 4);
break;
}
}
#endif
/* restore saved registers */
- for (i = rd->savintregcnt - 1; i >= rd->maxsavintreguse; i--) {
- p--;
- i386_mov_membase_reg(cd, REG_SP, p * 8, rd->savintregs[i]);
+
+ for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
+ p--; M_ALD(rd->savintregs[i], REG_SP, p * 4);
}
- for (i = rd->savfltregcnt - 1; i >= rd->maxsavfltreguse; i--) {
+
+ for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
p--;
- i386_fldl_membase(cd, REG_SP, p * 8);
+ i386_fldl_membase(cd, REG_SP, p * 4);
fpu_st_offset++;
if (iptr->opc == ICMD_FRETURN || iptr->opc == ICMD_DRETURN) {
i386_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset + 1);
fpu_st_offset--;
}
- /* deallocate stack */
- if (parentargs_base) {
- i386_alu_imm_reg(cd, I386_ADD, parentargs_base * 8, REG_SP);
- }
+ /* deallocate stack */
+
+ if (parentargs_base)
+ M_AADD_IMM(parentargs_base * 4, REG_SP);
i386_ret(cd);
- ALIGNCODENOP;
}
break;
case ICMD_TABLESWITCH: /* ..., index ==> ... */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
{
s4 i, l, *s4ptr;
void **tptr;
var_to_reg_int(s1, src, REG_ITMP1);
M_INTMOVE(s1, REG_ITMP1);
if (l != 0) {
- i386_alu_imm_reg(cd, I386_SUB, l, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_SUB, l, REG_ITMP1);
}
i = i - l + 1;
/* range check */
- i386_alu_imm_reg(cd, I386_CMP, i - 1, REG_ITMP1);
+ i386_alu_imm_reg(cd, ALU_CMP, i - 1, REG_ITMP1);
i386_jcc(cd, I386_CC_A, 0);
- /* codegen_addreference(cd, BlockPtrOfPC(s4ptr[0]), cd->mcodeptr); */
codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
/* build jump table top down and use address of lowest entry */
- /* s4ptr += 3 + i; */
tptr += i;
while (--i >= 0) {
- /* dseg_addtarget(cd, BlockPtrOfPC(*--s4ptr)); */
dseg_addtarget(cd, (basicblock *) tptr[0]);
--tptr;
}
dseg_adddata(cd, cd->mcodeptr);
i386_mov_memindex_reg(cd, -(cd->dseglen), REG_ITMP2, REG_ITMP1, 2, REG_ITMP1);
i386_jmp_reg(cd, REG_ITMP1);
- ALIGNCODENOP;
}
break;
case ICMD_LOOKUPSWITCH: /* ..., key ==> ... */
- {
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/
+ {
s4 i, l, val, *s4ptr;
void **tptr;
++tptr;
val = s4ptr[0];
- i386_alu_imm_reg(cd, I386_CMP, val, s1);
+ i386_alu_imm_reg(cd, ALU_CMP, val, s1);
i386_jcc(cd, I386_CC_E, 0);
- /* codegen_addreference(cd, BlockPtrOfPC(s4ptr[1]), cd->mcodeptr); */
codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
}
i386_jmp_imm(cd, 0);
- /* codegen_addreference(cd, BlockPtrOfPC(l), cd->mcodeptr); */
tptr = (void **) iptr->target;
codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
-
- ALIGNCODENOP;
}
break;
+ case ICMD_BUILTIN: /* ..., [arg1, [arg2 ...]] ==> ... */
+ /* op1 = arg count val.a = builtintable entry */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX*/
- case ICMD_BUILTIN3: /* ..., arg1, arg2, arg3 ==> ... */
- /* op1 = return type, val.a = function pointer*/
- s3 = 3;
- goto gen_method;
-
- case ICMD_BUILTIN2: /* ..., arg1, arg2 ==> ... */
- /* op1 = return type, val.a = function pointer*/
- s3 = 2;
- goto gen_method;
-
- case ICMD_BUILTIN1: /* ..., arg1 ==> ... */
- /* op1 = return type, val.a = function pointer*/
- s3 = 1;
+ bte = iptr->val.a;
+ md = bte->md;
goto gen_method;
case ICMD_INVOKESTATIC: /* ..., [arg1, [arg2 ...]] ==> ... */
/* op1 = arg count, val.a = method pointer */
case ICMD_INVOKESPECIAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */
- /* op1 = arg count, val.a = method pointer */
+ case ICMD_INVOKEVIRTUAL:/* op1 = arg count, val.a = method pointer */
+ case ICMD_INVOKEINTERFACE:
- case ICMD_INVOKEVIRTUAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */
- /* op1 = arg count, val.a = method pointer */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX */
- case ICMD_INVOKEINTERFACE:/*.., objectref, [arg1, [arg2 ...]] ==> ... */
- /* op1 = arg count, val.a = method pointer */
+ lm = iptr->val.a;
- s3 = iptr->op1;
+ if (lm == NULL) {
+ unresolved_method *um = iptr->target;
+ md = um->methodref->parseddesc.md;
+ } else {
+ md = lm->parseddesc;
+ }
-gen_method: {
- methodinfo *lm;
+gen_method:
+ s3 = md->paramcount;
MCODECHECK((s3 << 1) + 64);
/* copy arguments to registers or stack location */
- for (; --s3 >= 0; src = src->prev) {
- if (src->varkind == ARGVAR) {
+ for (s3 = s3 - 1; s3 >= 0; s3--, src = src->prev) {
+ if (src->varkind == ARGVAR)
continue;
- }
-
if (IS_INT_LNG_TYPE(src->type)) {
- if (s3 < rd->intreg_argnum) {
- panic("No integer argument registers available!");
-
+ if (!md->params[s3].inmemory) {
+ log_text("No integer argument registers available!");
+ assert(0);
} else {
if (!IS_2_WORD_TYPE(src->type)) {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, s3 * 8);
-
+ i386_mov_membase_reg(
+ cd, REG_SP, src->regoff * 4, REG_ITMP1);
+ i386_mov_reg_membase(
+ cd, REG_ITMP1, REG_SP,
+ md->params[s3].regoff * 4);
} else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, s3 * 8);
+ i386_mov_reg_membase(
+ cd, src->regoff, REG_SP,
+ md->params[s3].regoff * 4);
}
} else {
if (src->flags & INMEMORY) {
- M_LNGMEMMOVE(src->regoff, s3);
-
+ M_LNGMEMMOVE(
+ src->regoff, md->params[s3].regoff);
} else {
- panic("copy arguments: longs have to be in memory");
+ log_text("copy arguments: longs have to be in memory");
+ assert(0);
}
}
}
-
} else {
- if (s3 < rd->fltreg_argnum) {
- panic("No float argument registers available!");
-
+ if (!md->params[s3].inmemory) {
+ log_text("No float argument registers available!");
+ assert(0);
} else {
var_to_reg_flt(d, src, REG_FTMP1);
if (src->type == TYPE_FLT) {
- i386_fstps_membase(cd, REG_SP, s3 * 8);
+ i386_fstps_membase(
+ cd, REG_SP, md->params[s3].regoff * 4);
} else {
- i386_fstpl_membase(cd, REG_SP, s3 * 8);
+ i386_fstpl_membase(
+ cd, REG_SP, md->params[s3].regoff * 4);
}
}
}
} /* end of for */
- lm = iptr->val.a;
switch (iptr->opc) {
- case ICMD_BUILTIN3:
- case ICMD_BUILTIN2:
- case ICMD_BUILTIN1:
- a = (u4) lm;
- d = iptr->op1;
+ case ICMD_BUILTIN:
+ disp = (ptrint) bte->fp;
+ d = md->returntype.type;
- i386_mov_imm_reg(cd, a, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- break;
+ M_MOV_IMM(disp, REG_ITMP1);
+ M_CALL(REG_ITMP1);
- case ICMD_INVOKESTATIC:
- a = (u4) lm->stubroutine;
- d = lm->returntype;
+ /* if op1 == true, we need to check for an exception */
- i386_mov_imm_reg(cd, a, REG_ITMP2);
- i386_call_reg(cd, REG_ITMP2);
+ if (iptr->op1 == true) {
+ M_TEST(REG_RESULT);
+ M_BEQ(0);
+ codegen_addxexceptionrefs(cd, cd->mcodeptr);
+ }
break;
case ICMD_INVOKESPECIAL:
- a = (u4) lm->stubroutine;
- d = lm->returntype;
-
i386_mov_membase_reg(cd, REG_SP, 0, REG_ITMP1);
gen_nullptr_check(REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP1, 0, REG_ITMP1); /* access memory for hardware nullptr */
- i386_mov_imm_reg(cd, a, REG_ITMP2);
- i386_call_reg(cd, REG_ITMP2);
+ /* access memory for hardware nullptr */
+ i386_mov_membase_reg(cd, REG_ITMP1, 0, REG_ITMP1);
+
+ /* fall through */
+
+ case ICMD_INVOKESTATIC:
+ if (lm == NULL) {
+ unresolved_method *um = iptr->target;
+
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_invokestatic_special, um, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ disp = 0;
+ d = md->returntype.type;
+
+ } else {
+ disp = (ptrint) lm->stubroutine;
+ d = lm->parseddesc->returntype.type;
+ }
+
+ M_MOV_IMM(disp, REG_ITMP2);
+ M_CALL(REG_ITMP2);
break;
case ICMD_INVOKEVIRTUAL:
- d = lm->returntype;
-
- i386_mov_membase_reg(cd, REG_SP, 0, REG_ITMP1);
+ M_ALD(REG_ITMP1, REG_SP, 0 * 4);
gen_nullptr_check(REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(java_objectheader, vftbl), REG_ITMP2);
- i386_mov_membase32_reg(cd, REG_ITMP2, OFFSET(vftbl_t, table[0]) + sizeof(methodptr) * lm->vftblindex, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
+ if (lm == NULL) {
+ unresolved_method *um = iptr->target;
+
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_invokevirtual, um, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ s1 = 0;
+ d = md->returntype.type;
+
+ } else {
+ s1 = OFFSET(vftbl_t, table[0]) +
+ sizeof(methodptr) * lm->vftblindex;
+ d = md->returntype.type;
+ }
+
+ M_ALD(REG_ITMP2, REG_ITMP1, OFFSET(java_objectheader, vftbl));
+ i386_mov_membase32_reg(cd, REG_ITMP2, s1, REG_ITMP1);
+ M_CALL(REG_ITMP1);
break;
case ICMD_INVOKEINTERFACE:
- d = lm->returntype;
-
- i386_mov_membase_reg(cd, REG_SP, 0, REG_ITMP1);
+ M_ALD(REG_ITMP1, REG_SP, 0 * 4);
gen_nullptr_check(REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(java_objectheader, vftbl), REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, interfacetable[0]) - sizeof(methodptr) * lm->class->index, REG_ITMP2);
- i386_mov_membase32_reg(cd, REG_ITMP2, sizeof(methodptr) * (lm - lm->class->methods), REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
+ if (lm == NULL) {
+ unresolved_method *um = iptr->target;
+
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_invokeinterface, um, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ s1 = 0;
+ s2 = 0;
+ d = md->returntype.type;
+
+ } else {
+ s1 = OFFSET(vftbl_t, interfacetable[0]) -
+ sizeof(methodptr) * lm->class->index;
+
+ s2 = sizeof(methodptr) * (lm - lm->class->methods);
+
+ d = md->returntype.type;
+ }
+
+ M_ALD(REG_ITMP1, REG_ITMP1, OFFSET(java_objectheader, vftbl));
+ i386_mov_membase32_reg(cd, REG_ITMP1, s1, REG_ITMP2);
+ i386_mov_membase32_reg(cd, REG_ITMP2, s2, REG_ITMP1);
+ M_CALL(REG_ITMP1);
break;
}
if (IS_INT_LNG_TYPE(iptr->dst->type)) {
if (IS_2_WORD_TYPE(iptr->dst->type)) {
if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 8);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 8 + 4);
-
+ i386_mov_reg_membase(
+ cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
+ i386_mov_reg_membase(
+ cd, REG_RESULT2, REG_SP,
+ iptr->dst->regoff * 4 + 4);
} else {
- panic("RETURN: longs have to be in memory");
+ log_text("RETURN: longs have to be in memory");
+ assert(0);
}
} else {
if (iptr->dst->flags & INMEMORY) {
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4);
} else {
M_INTMOVE(REG_RESULT, iptr->dst->regoff);
store_reg_to_var_flt(iptr->dst, d);
}
}
- }
break;
- case ICMD_INSTANCEOF: /* ..., objectref ==> ..., intresult */
-
+ case ICMD_CHECKCAST: /* ..., objectref ==> ..., objectref */
/* op1: 0 == array, 1 == class */
/* val.a: (classinfo*) superclass */
-/* superclass is an interface:
- *
- * return (sub != NULL) &&
- * (sub->vftbl->interfacetablelength > super->index) &&
- * (sub->vftbl->interfacetable[-super->index] != NULL);
- *
- * superclass is a class:
- *
- * return ((sub != NULL) && (0
- * <= (sub->vftbl->baseval - super->vftbl->baseval) <=
- * super->vftbl->diffvall));
- */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: YES ECX: I|YES EDX: I|YES OUTPUT: REG_NULL */
- {
- classinfo *super = (classinfo*) iptr->val.a;
+ /* superclass is an interface:
+ *
+ * OK if ((sub == NULL) ||
+ * (sub->vftbl->interfacetablelength > super->index) &&
+ * (sub->vftbl->interfacetable[-super->index] != NULL));
+ *
+ * superclass is a class:
+ *
+ * OK if ((sub == NULL) || (0
+ * <= (sub->vftbl->baseval - super->vftbl->baseval) <=
+ * super->vftbl->diffval));
+ */
+
+ if (iptr->op1 == 1) {
+ /* object type cast-check */
+
+ classinfo *super;
+ vftbl_t *supervftbl;
+ s4 superindex;
+
+ super = (classinfo *) iptr->val.a;
+
+ if (!super) {
+ superindex = 0;
+ supervftbl = NULL;
+
+ } else {
+ superindex = super->index;
+ supervftbl = super->vftbl;
+ }
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase);
+ codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase);
#endif
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(rd, iptr->dst, REG_ITMP3);
- if (s1 == d) {
- M_INTMOVE(s1, REG_ITMP1);
- s1 = REG_ITMP1;
- }
- i386_alu_reg_reg(cd, I386_XOR, d, d);
- if (iptr->op1) { /* class/interface */
- if (super->flags & ACC_INTERFACE) { /* interface */
- i386_test_reg_reg(cd, s1, s1);
+ var_to_reg_int(s1, src, REG_ITMP1);
- /* TODO: clean up this calculation */
- a = 2;
- CALCOFFSETBYTES(a, s1, OFFSET(java_objectheader, vftbl));
+ /* calculate interface checkcast code size */
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP1, OFFSET(vftbl_t, interfacetablelength));
-
- a += 2;
-/* CALCOFFSETBYTES(a, super->index); */
- CALCIMMEDIATEBYTES(a, super->index);
-
- a += 3;
- a += 6;
+ s2 = 2; /* mov_membase_reg */
+ CALCOFFSETBYTES(s2, s1, OFFSET(java_objectheader, vftbl));
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP1, OFFSET(vftbl_t, interfacetable[0]) - super->index * sizeof(methodptr*));
+ s2 += (2 + 4 /* mov_membase32_reg */ + 2 + 4 /* sub imm32 */ +
+ 2 /* test */ + 6 /* jcc */ + 2 + 4 /* mov_membase32_reg */ +
+ 2 /* test */ + 6 /* jcc */);
- a += 3;
+ if (!super)
+ s2 += (opt_showdisassemble ? 5 : 0);
- a += 6; /* jcc */
- a += 5;
+ /* calculate class checkcast code size */
- i386_jcc(cd, I386_CC_E, a);
+ s3 = 2; /* mov_membase_reg */
+ CALCOFFSETBYTES(s3, s1, OFFSET(java_objectheader, vftbl));
- i386_mov_membase_reg(cd, s1, OFFSET(java_objectheader, vftbl), REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, interfacetablelength), REG_ITMP2);
- i386_alu_imm_reg(cd, I386_SUB, super->index, REG_ITMP2);
- /* TODO: test */
- i386_alu_imm_reg(cd, I386_CMP, 0, REG_ITMP2);
+ s3 += 5 /* mov_imm_reg */ + 2 + 4 /* mov_membase32_reg */;
- /* TODO: clean up this calculation */
- a = 0;
+#if 0
+ if (s1 != REG_ITMP1) {
+ a += 2;
+ CALCOFFSETBYTES(a, REG_ITMP3, OFFSET(vftbl_t, baseval));
+
+ a += 2;
+ CALCOFFSETBYTES(a, REG_ITMP3, OFFSET(vftbl_t, diffval));
+
a += 2;
- CALCOFFSETBYTES(a, REG_ITMP1, OFFSET(vftbl_t, interfacetable[0]) - super->index * sizeof(methodptr*));
+
+ } else
+#endif
+ {
+ s3 += (2 + 4 /* mov_membase32_reg */ + 2 /* sub */ +
+ 5 /* mov_imm_reg */ + 2 /* mov_membase_reg */);
+ CALCOFFSETBYTES(s3, REG_ITMP3, OFFSET(vftbl_t, diffval));
+ }
- a += 3;
+ s3 += 2 /* cmp */ + 6 /* jcc */;
- a += 6; /* jcc */
- a += 5;
+ if (!super)
+ s3 += (opt_showdisassemble ? 5 : 0);
- i386_jcc(cd, I386_CC_LE, a);
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, interfacetable[0]) - super->index * sizeof(methodptr*), REG_ITMP1);
- /* TODO: test */
- i386_alu_imm_reg(cd, I386_CMP, 0, REG_ITMP1);
-/* i386_setcc_reg(cd, I386_CC_A, d); */
-/* i386_jcc(cd, I386_CC_BE, 5); */
- i386_jcc(cd, I386_CC_E, 5);
- i386_mov_imm_reg(cd, 1, d);
-
+ /* if class is not resolved, check which code to call */
- } else { /* class */
+ if (!super) {
i386_test_reg_reg(cd, s1, s1);
+ i386_jcc(cd, I386_CC_Z, 5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3);
- /* TODO: clean up this calculation */
- a = 2;
- CALCOFFSETBYTES(a, s1, OFFSET(java_objectheader, vftbl));
- a += 5;
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP1, OFFSET(vftbl_t, baseval));
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP2, OFFSET(vftbl_t, baseval));
-
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP2, OFFSET(vftbl_t, diffval));
-
- a += 2;
- a += 2; /* xor */
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_checkcast_instanceof_flags,
+ (constant_classref *) iptr->target, 0);
- a += 2;
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ i386_mov_imm_reg(cd, 0, REG_ITMP2); /* super->flags */
+ i386_alu_imm_reg(cd, ALU_AND, ACC_INTERFACE, REG_ITMP2);
+ i386_jcc(cd, I386_CC_Z, s2 + 5);
+ }
+
+ /* interface checkcast code */
+
+ if (!super || (super->flags & ACC_INTERFACE)) {
+ if (super) {
+ i386_test_reg_reg(cd, s1, s1);
+ i386_jcc(cd, I386_CC_Z, s2);
+ }
+
+ i386_mov_membase_reg(cd, s1,
+ OFFSET(java_objectheader, vftbl),
+ REG_ITMP2);
+
+ if (!super) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_checkcast_instanceof_interface,
+ (constant_classref *) iptr->target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
+
+ i386_mov_membase32_reg(cd, REG_ITMP2,
+ OFFSET(vftbl_t, interfacetablelength),
+ REG_ITMP3);
+ i386_alu_imm32_reg(cd, ALU_SUB, superindex, REG_ITMP3);
+ i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3);
+ i386_jcc(cd, I386_CC_LE, 0);
+ codegen_addxcastrefs(cd, cd->mcodeptr);
+ i386_mov_membase32_reg(cd, REG_ITMP2,
+ OFFSET(vftbl_t, interfacetable[0]) -
+ superindex * sizeof(methodptr*),
+ REG_ITMP3);
+ i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3);
+ i386_jcc(cd, I386_CC_E, 0);
+ codegen_addxcastrefs(cd, cd->mcodeptr);
- a += 6; /* jcc */
- a += 5;
+ if (!super)
+ i386_jmp_imm(cd, s3);
+ }
+
+ /* class checkcast code */
+
+ if (!super || !(super->flags & ACC_INTERFACE)) {
+ if (super) {
+ i386_test_reg_reg(cd, s1, s1);
+ i386_jcc(cd, I386_CC_Z, s3);
+ }
- i386_jcc(cd, I386_CC_E, a);
+ i386_mov_membase_reg(cd, s1,
+ OFFSET(java_objectheader, vftbl),
+ REG_ITMP2);
+
+ if (!super) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_checkcast_class,
+ (constant_classref *) iptr->target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
- i386_mov_membase_reg(cd, s1, OFFSET(java_objectheader, vftbl), REG_ITMP1);
- i386_mov_imm_reg(cd, (s4) super->vftbl, REG_ITMP2);
+ i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP3);
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase);
#endif
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, baseval), REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, baseval), REG_ITMP3);
- i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, diffval), REG_ITMP2);
+ i386_mov_membase32_reg(cd, REG_ITMP2,
+ OFFSET(vftbl_t, baseval),
+ REG_ITMP2);
+
+ /* if (s1 != REG_ITMP1) { */
+ /* i386_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, baseval), REG_ITMP1); */
+ /* i386_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, diffval), REG_ITMP3); */
+ /* #if defined(USE_THREADS) && defined(NATIVE_THREADS) */
+ /* codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase); */
+ /* #endif */
+ /* i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP1, REG_ITMP2); */
+
+ /* } else { */
+ i386_mov_membase32_reg(cd, REG_ITMP3,
+ OFFSET(vftbl_t, baseval),
+ REG_ITMP3);
+ i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP3, REG_ITMP2);
+ i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP3);
+ i386_mov_membase_reg(cd, REG_ITMP3,
+ OFFSET(vftbl_t, diffval),
+ REG_ITMP3);
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
#endif
- i386_alu_reg_reg(cd, I386_SUB, REG_ITMP3, REG_ITMP1);
- i386_alu_reg_reg(cd, I386_XOR, d, d);
+ /* } */
- i386_alu_reg_reg(cd, I386_CMP, REG_ITMP2, REG_ITMP1);
- i386_jcc(cd, I386_CC_A, 5);
- i386_mov_imm_reg(cd, 1, d);
+ i386_alu_reg_reg(cd, ALU_CMP, REG_ITMP3, REG_ITMP2);
+ i386_jcc(cd, I386_CC_A, 0); /* (u) REG_ITMP2 > (u) REG_ITMP3 -> jump */
+ codegen_addxcastrefs(cd, cd->mcodeptr);
}
+ d = reg_of_var(rd, iptr->dst, REG_ITMP3);
+
+ } else {
+ /* array type cast-check */
+
+ var_to_reg_int(s1, src, REG_ITMP1);
+ M_AST(s1, REG_SP, 0 * 4);
+
+ if (iptr->val.a == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_builtin_arraycheckcast,
+ iptr->target, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
+
+ M_AST_IMM((ptrint) iptr->val.a, REG_SP, 1 * 4);
+ M_MOV_IMM((ptrint) BUILTIN_arraycheckcast, REG_ITMP3);
+ M_CALL(REG_ITMP3);
+ M_TEST(REG_RESULT);
+ M_BEQ(0);
+ codegen_addxcastrefs(cd, cd->mcodeptr);
+
+ var_to_reg_int(s1, src, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, s1);
}
- else
- panic ("internal error: no inlined array instanceof");
- }
- store_reg_to_var_int(iptr->dst, d);
+ M_INTMOVE(s1, d);
+ store_reg_to_var_int(iptr->dst, d);
break;
- case ICMD_CHECKCAST: /* ..., objectref ==> ..., objectref */
+ case ICMD_INSTANCEOF: /* ..., objectref ==> ..., intresult */
/* op1: 0 == array, 1 == class */
/* val.a: (classinfo*) superclass */
-
-/* superclass is an interface:
- *
- * OK if ((sub == NULL) ||
- * (sub->vftbl->interfacetablelength > super->index) &&
- * (sub->vftbl->interfacetable[-super->index] != NULL));
- *
- * superclass is a class:
- *
- * OK if ((sub == NULL) || (0
- * <= (sub->vftbl->baseval - super->vftbl->baseval) <=
- * super->vftbl->diffvall));
- */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|D|YES ECX: YES S|D|EDX: S|D|YES OUTPUT: REG_NULL*/
+ /* ????? Really necessary to block all ????? */
+
+ /* superclass is an interface:
+ *
+ * return (sub != NULL) &&
+ * (sub->vftbl->interfacetablelength > super->index) &&
+ * (sub->vftbl->interfacetable[-super->index] != NULL);
+ *
+ * superclass is a class:
+ *
+ * return ((sub != NULL) && (0
+ * <= (sub->vftbl->baseval - super->vftbl->baseval) <=
+ * super->vftbl->diffvall));
+ */
{
- classinfo *super = (classinfo*) iptr->val.a;
+ classinfo *super;
+ vftbl_t *supervftbl;
+ s4 superindex;
+
+ super = (classinfo *) iptr->val.a;
+
+ if (!super) {
+ superindex = 0;
+ supervftbl = NULL;
+
+ } else {
+ superindex = super->index;
+ supervftbl = super->vftbl;
+ }
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase);
#endif
- d = reg_of_var(rd, iptr->dst, REG_ITMP3);
- var_to_reg_int(s1, src, d);
- if (iptr->op1) { /* class/interface */
- if (super->flags & ACC_INTERFACE) { /* interface */
- i386_test_reg_reg(cd, s1, s1);
- /* TODO: clean up this calculation */
- a = 2;
- CALCOFFSETBYTES(a, s1, OFFSET(java_objectheader, vftbl));
+ var_to_reg_int(s1, src, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP2);
+ if (s1 == d) {
+ M_INTMOVE(s1, REG_ITMP1);
+ s1 = REG_ITMP1;
+ }
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP1, OFFSET(vftbl_t, interfacetablelength));
+ /* calculate interface instanceof code size */
- a += 2;
-/* CALCOFFSETBYTES(a, super->index); */
- CALCIMMEDIATEBYTES(a, super->index);
+ s2 = 2; /* mov_membase_reg */
+ CALCOFFSETBYTES(s2, s1, OFFSET(java_objectheader, vftbl));
- a += 3;
- a += 6;
+ s2 += (2 + 4 /* mov_membase32_reg */ + 2 + 4 /* alu_imm32_reg */ +
+ 2 /* test */ + 6 /* jcc */ + 2 + 4 /* mov_membase32_reg */ +
+ 2 /* test */ + 6 /* jcc */ + 5 /* mov_imm_reg */);
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP1, OFFSET(vftbl_t, interfacetable[0]) - super->index * sizeof(methodptr*));
+ if (!super)
+ s2 += (opt_showdisassemble ? 5 : 0);
- a += 3;
- a += 6;
+ /* calculate class instanceof code size */
- i386_jcc(cd, I386_CC_E, a);
+ s3 = 2; /* mov_membase_reg */
+ CALCOFFSETBYTES(s3, s1, OFFSET(java_objectheader, vftbl));
+ s3 += 5; /* mov_imm_reg */
+ s3 += 2;
+ CALCOFFSETBYTES(s3, REG_ITMP1, OFFSET(vftbl_t, baseval));
+ s3 += 2;
+ CALCOFFSETBYTES(s3, REG_ITMP2, OFFSET(vftbl_t, diffval));
+ s3 += 2;
+ CALCOFFSETBYTES(s3, REG_ITMP2, OFFSET(vftbl_t, baseval));
- i386_mov_membase_reg(cd, s1, OFFSET(java_objectheader, vftbl), REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, interfacetablelength), REG_ITMP2);
- i386_alu_imm_reg(cd, I386_SUB, super->index, REG_ITMP2);
- /* TODO: test */
- i386_alu_imm_reg(cd, I386_CMP, 0, REG_ITMP2);
- i386_jcc(cd, I386_CC_LE, 0);
- codegen_addxcastrefs(cd, cd->mcodeptr);
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, interfacetable[0]) - super->index * sizeof(methodptr*), REG_ITMP2);
- /* TODO: test */
- i386_alu_imm_reg(cd, I386_CMP, 0, REG_ITMP2);
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addxcastrefs(cd, cd->mcodeptr);
+ s3 += (2 /* alu_reg_reg */ + 2 /* alu_reg_reg */ +
+ 2 /* alu_reg_reg */ + 6 /* jcc */ + 5 /* mov_imm_reg */);
- } else { /* class */
- i386_test_reg_reg(cd, s1, s1);
+ if (!super)
+ s3 += (opt_showdisassemble ? 5 : 0);
- /* TODO: clean up this calculation */
- a = 2;
- CALCOFFSETBYTES(a, s1, OFFSET(java_objectheader, vftbl));
+ i386_alu_reg_reg(cd, ALU_XOR, d, d);
- a += 5;
+ /* if class is not resolved, check which code to call */
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP1, OFFSET(vftbl_t, baseval));
+ if (!super) {
+ i386_test_reg_reg(cd, s1, s1);
+ i386_jcc(cd, I386_CC_Z, 5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3);
- if (d != REG_ITMP3) {
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP2, OFFSET(vftbl_t, baseval));
-
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP2, OFFSET(vftbl_t, diffval));
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_checkcast_instanceof_flags,
+ (constant_classref *) iptr->target, 0);
- a += 2;
-
- } else {
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP2, OFFSET(vftbl_t, baseval));
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
- a += 2;
+ i386_mov_imm_reg(cd, 0, REG_ITMP3); /* super->flags */
+ i386_alu_imm32_reg(cd, ALU_AND, ACC_INTERFACE, REG_ITMP3);
+ i386_jcc(cd, I386_CC_Z, s2 + 5);
+ }
- a += 5;
+ /* interface instanceof code */
- a += 2;
- CALCOFFSETBYTES(a, REG_ITMP2, OFFSET(vftbl_t, diffval));
- }
+ if (!super || (super->flags & ACC_INTERFACE)) {
+ if (super) {
+ M_TEST(s1);
+ M_BEQ(s2);
+ }
- a += 2;
+ i386_mov_membase_reg(cd, s1,
+ OFFSET(java_objectheader, vftbl),
+ REG_ITMP1);
- a += 6;
+ if (!super) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_checkcast_instanceof_interface,
+ (constant_classref *) iptr->target, 0);
- i386_jcc(cd, I386_CC_E, a);
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
- i386_mov_membase_reg(cd, s1, OFFSET(java_objectheader, vftbl), REG_ITMP1);
- i386_mov_imm_reg(cd, (s4) super->vftbl, REG_ITMP2);
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase);
-#endif
- i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, baseval), REG_ITMP1);
- if (d != REG_ITMP3) {
- i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, baseval), REG_ITMP3);
- i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, diffval), REG_ITMP2);
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
-#endif
- i386_alu_reg_reg(cd, I386_SUB, REG_ITMP3, REG_ITMP1);
+ i386_mov_membase32_reg(cd, REG_ITMP1,
+ OFFSET(vftbl_t, interfacetablelength),
+ REG_ITMP3);
+ i386_alu_imm32_reg(cd, ALU_SUB, superindex, REG_ITMP3);
+ i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3);
+
+ disp = (2 + 4 /* mov_membase32_reg */ + 2 /* test */ +
+ 6 /* jcc */ + 5 /* mov_imm_reg */);
+
+ M_BLE(disp);
+ i386_mov_membase32_reg(cd, REG_ITMP1,
+ OFFSET(vftbl_t, interfacetable[0]) -
+ superindex * sizeof(methodptr*),
+ REG_ITMP1);
+ M_TEST(REG_ITMP1);
+/* i386_setcc_reg(cd, I386_CC_A, d); */
+/* i386_jcc(cd, I386_CC_BE, 5); */
+ M_BEQ(5);
+ M_MOV_IMM(1, d);
- } else {
- i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, baseval), REG_ITMP2);
- i386_alu_reg_reg(cd, I386_SUB, REG_ITMP2, REG_ITMP1);
- i386_mov_imm_reg(cd, (s4) super->vftbl, REG_ITMP2);
- i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, diffval), REG_ITMP2);
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
-#endif
- }
+ if (!super)
+ M_JMP_IMM(s3);
+ }
- i386_alu_reg_reg(cd, I386_CMP, REG_ITMP2, REG_ITMP1);
- i386_jcc(cd, I386_CC_A, 0); /* (u) REG_ITMP1 > (u) REG_ITMP2 -> jump */
- codegen_addxcastrefs(cd, cd->mcodeptr);
+ /* class instanceof code */
+
+ if (!super || !(super->flags & ACC_INTERFACE)) {
+ if (super) {
+ M_TEST(s1);
+ M_BEQ(s3);
}
- } else
- panic ("internal error: no inlined array checkcast");
- }
- M_INTMOVE(s1, d);
- store_reg_to_var_int(iptr->dst, d);
- break;
+ i386_mov_membase_reg(cd, s1,
+ OFFSET(java_objectheader, vftbl),
+ REG_ITMP1);
- case ICMD_CHECKASIZE: /* ..., size ==> ..., size */
+ if (!super) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_instanceof_class,
+ (constant_classref *) iptr->target, 0);
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, src->regoff * 8);
-
- } else {
- i386_test_reg_reg(cd, src->regoff, src->regoff);
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+ }
+
+ i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP2);
+#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+ codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase);
+#endif
+ i386_mov_membase_reg(cd, REG_ITMP1,
+ OFFSET(vftbl_t, baseval),
+ REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_ITMP2,
+ OFFSET(vftbl_t, diffval),
+ REG_ITMP3);
+ i386_mov_membase_reg(cd, REG_ITMP2,
+ OFFSET(vftbl_t, baseval),
+ REG_ITMP2);
+#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+ codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
+#endif
+ i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP2, REG_ITMP1);
+ i386_alu_reg_reg(cd, ALU_XOR, d, d); /* may be REG_ITMP2 */
+ i386_alu_reg_reg(cd, ALU_CMP, REG_ITMP3, REG_ITMP1);
+ i386_jcc(cd, I386_CC_A, 5);
+ i386_mov_imm_reg(cd, 1, d);
+ }
+ store_reg_to_var_int(iptr->dst, d);
}
- i386_jcc(cd, I386_CC_L, 0);
- codegen_addxcheckarefs(cd, cd->mcodeptr);
break;
- case ICMD_CHECKEXCEPTION: /* ... ==> ... */
-
- i386_test_reg_reg(cd, REG_RESULT, REG_RESULT);
- i386_jcc(cd, I386_CC_E, 0);
- codegen_addxexceptionrefs(cd, cd->mcodeptr);
break;
case ICMD_MULTIANEWARRAY:/* ..., cnt1, [cnt2, ...] ==> ..., arrayref */
- /* op1 = dimension, val.a = array descriptor */
+ /* op1 = dimension, val.a = class */
+ /* REG_RES Register usage: see icmd_uses_reg_res.inc */
+ /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX */
/* check for negative sizes and copy sizes to stack if necessary */
MCODECHECK((iptr->op1 << 1) + 64);
for (s1 = iptr->op1; --s1 >= 0; src = src->prev) {
- if (src->flags & INMEMORY) {
- i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, src->regoff * 8);
-
- } else {
- i386_test_reg_reg(cd, src->regoff, src->regoff);
- }
- i386_jcc(cd, I386_CC_L, 0);
- codegen_addxcheckarefs(cd, cd->mcodeptr);
-
- /*
- * copy sizes to new stack location, be cause native function
- * builtin_nmultianewarray access them as (int *)
- */
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, -(iptr->op1 - s1) * 4);
-
- /* copy sizes to stack (argument numbers >= INT_ARG_CNT) */
+ /* copy SAVEDVAR sizes to stack */
if (src->varkind != ARGVAR) {
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, (src->regoff + INT_ARG_CNT) * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (s1 + INT_ARG_CNT) * 8);
+ M_ILD(REG_ITMP1, REG_SP, src->regoff * 4);
+ M_IST(REG_ITMP1, REG_SP, (s1 + 3) * 4);
} else {
- i386_mov_reg_membase(cd, src->regoff, REG_SP, (s1 + INT_ARG_CNT) * 8);
+ M_IST(src->regoff, REG_SP, (s1 + 3) * 4);
}
}
}
- i386_alu_imm_reg(cd, I386_SUB, iptr->op1 * 4, REG_SP);
- /* a0 = dimension count */
+ /* is a patcher function set? */
- /* save stack pointer */
- M_INTMOVE(REG_SP, REG_ITMP1);
+ if (iptr->val.a == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr,
+ PATCHER_builtin_multianewarray,
+ (constant_classref *) iptr->target, 0);
- i386_alu_imm_reg(cd, I386_SUB, 12, REG_SP);
- i386_mov_imm_membase(cd, iptr->op1, REG_SP, 0);
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
+ }
+
+ disp = 0;
+
+ } else {
+ disp = (ptrint) iptr->val.a;
+ }
+
+ /* a0 = dimension count */
+
+ M_IST_IMM(iptr->op1, REG_SP, 0 * 4);
/* a1 = arraydescriptor */
- i386_mov_imm_membase(cd, (s4) iptr->val.a, REG_SP, 4);
+ M_IST_IMM(disp, REG_SP, 1 * 4);
/* a2 = pointer to dimensions = stack pointer */
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 8);
+ M_MOV(REG_SP, REG_ITMP1);
+ M_AADD_IMM(3 * 4, REG_ITMP1);
+ M_AST(REG_ITMP1, REG_SP, 2 * 4);
- i386_mov_imm_reg(cd, (s4) (builtin_nmultianewarray), REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- i386_alu_imm_reg(cd, I386_ADD, 12 + iptr->op1 * 4, REG_SP);
+ M_MOV_IMM((ptrint) BUILTIN_multianewarray, REG_ITMP1);
+ M_CALL(REG_ITMP1);
+
+ /* check for exception before result assignment */
+
+ M_TEST(REG_RESULT);
+ M_BEQ(0);
+ codegen_addxexceptionrefs(cd, cd->mcodeptr);
s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
M_INTMOVE(REG_RESULT, s1);
store_reg_to_var_int(iptr->dst, s1);
break;
- case ICMD_INLINE_START:
- case ICMD_INLINE_END:
- break;
default:
- error ("Unknown pseudo command: %d", iptr->opc);
+ *exceptionptr =
+ new_internalerror("Unknown ICMD %d", iptr->opc);
+ return false;
} /* switch */
} /* for instruction */
src = bptr->outstack;
len = bptr->outdepth;
MCODECHECK(64+len);
+#if defined(ENABLE_LSRA)
+ if (!opt_lsra)
+#endif
while (src) {
len--;
if ((src->varkind != STACKVAR)) {
M_FLTMOVE(s1, rd->interfaces[len][s2].regoff);
} else {
- panic("double store");
-/* M_DST(s1, REG_SP, 8 * interfaces[len][s2].regoff); */
+ log_text("double store");
+ assert(0);
+/* M_DST(s1, REG_SP, 4 * interfaces[len][s2].regoff); */
}
} else {
M_INTMOVE(s1, rd->interfaces[len][s2].regoff);
} else {
- i386_mov_reg_membase(cd, s1, REG_SP, rd->interfaces[len][s2].regoff * 8);
+ i386_mov_reg_membase(cd, s1, REG_SP, rd->interfaces[len][s2].regoff * 4);
}
} else {
M_LNGMEMMOVE(s1, rd->interfaces[len][s2].regoff);
} else {
- panic("copy interface registers: longs have to be in memory (end)");
+ log_text("copy interface registers: longs have to be in memory (end)");
+ assert(0);
}
}
}
}
src = src->prev;
}
+
+ /* At the end of a basic block we may have to append some nops,
+ because the patcher stub calling code might be longer than the
+ actual instruction. So codepatching does not change the
+ following block unintentionally. */
+
+ if (cd->mcodeptr < cd->lastmcodeptr) {
+ while (cd->mcodeptr < cd->lastmcodeptr) {
+ M_NOP;
+ }
+ }
+
} /* if (bptr -> flags >= BBREACHED) */
} /* for basic block */
- codegen_createlinenumbertable(cd);
+ dseg_createlinenumbertable(cd);
{
- /* generate bound check stubs */
-
- u1 *xcodeptr = NULL;
+ u1 *xcodeptr;
branchref *bref;
+ /* generate ArithmeticException stubs */
+
+ xcodeptr = NULL;
+
+ for (bref = cd->xdivrefs; bref != NULL; bref = bref->next) {
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
+ cd->mcodeptr - cd->mcodebase);
+
+ MCODECHECK(512);
+
+ M_MOV_IMM(0, REG_ITMP2_XPC);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
+
+ if (xcodeptr != NULL) {
+ M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
+
+ } else {
+ xcodeptr = cd->mcodeptr;
+
+ M_ASUB_IMM(4 * 4, REG_SP);
+
+ M_AST_IMM(0, REG_SP, 0 * 4);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_MOV(REG_SP, REG_ITMP3);
+ M_AADD_IMM(4 * 4, REG_ITMP3);
+ M_AST(REG_ITMP3, REG_SP, 1 * 4);
+ M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
+ M_AST(REG_ITMP3, REG_SP, 2 * 4);
+ M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
+
+ M_MOV_IMM((ptrint) stacktrace_inline_arithmeticexception,
+ REG_ITMP3);
+ M_CALL(REG_ITMP3);
+
+ M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ M_AADD_IMM(4 * 4, REG_SP);
+
+ M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
+ }
+ }
+
+ /* generate ArrayIndexOutOfBoundsException stubs */
+
+ xcodeptr = NULL;
+
for (bref = cd->xboundrefs; bref != NULL; bref = bref->next) {
gen_resolvebranch(cd->mcodebase + bref->branchpos,
bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(100);
+ MCODECHECK(512);
/* move index register into REG_ITMP1 */
- i386_mov_reg_reg(cd, bref->reg, REG_ITMP1); /* 2 bytes */
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ M_INTMOVE(bref->reg, REG_ITMP1);
+
+ M_MOV_IMM(0, REG_ITMP2_XPC);
dseg_adddata(cd, cd->mcodeptr);
- i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP3); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP3, REG_ITMP2_XPC); /* 2 bytes */
+ M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
if (xcodeptr != NULL) {
- i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
+ M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
} else {
xcodeptr = cd->mcodeptr;
- i386_push_reg(cd, REG_ITMP2_XPC);
-
- PREPARE_NATIVE_STACKINFO;
+ M_ASUB_IMM(5 * 4, REG_SP);
- i386_alu_imm_reg(cd, I386_SUB, 1 * 4, REG_SP);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 0 * 4);
- i386_mov_imm_reg(cd, (u4) new_arrayindexoutofboundsexception, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
- i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);
-
- REMOVE_NATIVE_STACKINFO;
-
- i386_pop_reg(cd, REG_ITMP2_XPC);
-
- i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3);
+ M_AST_IMM(0, REG_SP, 0 * 4);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_MOV(REG_SP, REG_ITMP3);
+ M_AADD_IMM(5 * 4, REG_ITMP3);
+ M_AST(REG_ITMP3, REG_SP, 1 * 4);
+ M_ALD(REG_ITMP3, REG_SP, (5 + parentargs_base) * 4);
+ M_AST(REG_ITMP3, REG_SP, 2 * 4);
+ M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ M_AST(REG_ITMP1, REG_SP, 4 * 4); /* don't use REG_ITMP1 till here */
+
+ M_MOV_IMM((ptrint) stacktrace_inline_arrayindexoutofboundsexception,
+ REG_ITMP3);
+ M_CALL(REG_ITMP3);
+
+ M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ M_AADD_IMM(5 * 4, REG_SP);
+
+ M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
}
}
- /* generate negative array size check stubs */
+ /* generate ArrayStoreException stubs */
xcodeptr = NULL;
- for (bref = cd->xcheckarefs; bref != NULL; bref = bref->next) {
- if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- xcodeptr - cd->mcodebase - (5 + 5 + 2));
- continue;
- }
-
+ for (bref = cd->xstorerefs; bref != NULL; bref = bref->next) {
gen_resolvebranch(cd->mcodebase + bref->branchpos,
bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(100);
+ MCODECHECK(512);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ M_MOV_IMM(0, REG_ITMP2_XPC);
dseg_adddata(cd, cd->mcodeptr);
- i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
+ M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
if (xcodeptr != NULL) {
- i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
+ M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
} else {
xcodeptr = cd->mcodeptr;
- i386_push_reg(cd, REG_ITMP2_XPC);
-
- PREPARE_NATIVE_STACKINFO;
-
- i386_mov_imm_reg(cd, (u4) new_negativearraysizeexception, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
- /*i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);*/
-
-
- REMOVE_NATIVE_STACKINFO;
+ M_ASUB_IMM(4 * 4, REG_SP);
- i386_pop_reg(cd, REG_ITMP2_XPC);
-
- i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3);
+ M_AST_IMM(0, REG_SP, 0 * 4);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_MOV(REG_SP, REG_ITMP3);
+ M_AADD_IMM(4 * 4, REG_ITMP3);
+ M_AST(REG_ITMP3, REG_SP, 1 * 4);
+ M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
+ M_AST(REG_ITMP3, REG_SP, 2 * 4);
+ M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
+
+ M_MOV_IMM((ptrint) stacktrace_inline_arraystoreexception,
+ REG_ITMP3);
+ M_CALL(REG_ITMP3);
+
+ M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ M_AADD_IMM(4 * 4, REG_SP);
+
+ M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
}
}
- /* generate cast check stubs */
+ /* generate ClassCastException stubs */
xcodeptr = NULL;
for (bref = cd->xcastrefs; bref != NULL; bref = bref->next) {
- if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- xcodeptr - cd->mcodebase - (5 + 5 + 2));
- continue;
- }
-
gen_resolvebranch(cd->mcodebase + bref->branchpos,
bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(100);
+ MCODECHECK(512);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ M_MOV_IMM(0, REG_ITMP2_XPC);
dseg_adddata(cd, cd->mcodeptr);
- i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
+ M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
if (xcodeptr != NULL) {
- i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
+ M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
} else {
xcodeptr = cd->mcodeptr;
- i386_push_reg(cd, REG_ITMP2_XPC);
-
- PREPARE_NATIVE_STACKINFO;
-
- i386_mov_imm_reg(cd, (u4) new_classcastexception, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
- /*i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);*/
+ M_ASUB_IMM(4 * 4, REG_SP);
+ M_AST_IMM(0, REG_SP, 0 * 4);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_MOV(REG_SP, REG_ITMP3);
+ M_AADD_IMM(4 * 4, REG_ITMP3);
+ M_AST(REG_ITMP3, REG_SP, 1 * 4);
+ M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
+ M_AST(REG_ITMP3, REG_SP, 2 * 4);
+ M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
- REMOVE_NATIVE_STACKINFO;
+ M_MOV_IMM((ptrint) stacktrace_inline_classcastexception, REG_ITMP3);
+ M_CALL(REG_ITMP3);
- i386_pop_reg(cd, REG_ITMP2_XPC);
+ M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ M_AADD_IMM(4 * 4, REG_SP);
- i386_mov_imm_reg(cd, (u4) asm_handle_exception, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3);
+ M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
}
}
- /* generate divide by zero check stubs */
+ /* generate NullPointerException stubs */
xcodeptr = NULL;
- for (bref = cd->xdivrefs; bref != NULL; bref = bref->next) {
- if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- xcodeptr - cd->mcodebase - (5 + 5 + 2));
- continue;
- }
-
+ for (bref = cd->xnullrefs; bref != NULL; bref = bref->next) {
gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
+ bref->branchpos,
cd->mcodeptr - cd->mcodebase);
+
+ MCODECHECK(512);
- MCODECHECK(100);
-
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ M_MOV_IMM(0, REG_ITMP2_XPC);
dseg_adddata(cd, cd->mcodeptr);
- i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
-
- if (xcodeptr != NULL) {
- i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
+ M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
+ if (xcodeptr != NULL) {
+ M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
+
} else {
xcodeptr = cd->mcodeptr;
+
+ M_ASUB_IMM(4 * 4, REG_SP);
- i386_push_reg(cd, REG_ITMP2_XPC);
-
- PREPARE_NATIVE_STACKINFO;
-
- i386_mov_imm_reg(cd, (u4) new_arithmeticexception, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
-
- REMOVE_NATIVE_STACKINFO;
-
- i386_pop_reg(cd, REG_ITMP2_XPC);
-
- i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3);
+ M_AST_IMM(0, REG_SP, 0 * 4);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_MOV(REG_SP, REG_ITMP3);
+ M_AADD_IMM(4 * 4, REG_ITMP3);
+ M_AST(REG_ITMP3, REG_SP, 1 * 4);
+ M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
+ M_AST(REG_ITMP3, REG_SP, 2 * 4);
+ M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
+
+ M_MOV_IMM((ptrint) stacktrace_inline_nullpointerexception,
+ REG_ITMP3);
+ M_CALL(REG_ITMP3);
+
+ M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ M_AADD_IMM(4 * 4, REG_SP);
+
+ M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
}
}
xcodeptr = NULL;
for (bref = cd->xexceptionrefs; bref != NULL; bref = bref->next) {
- if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- xcodeptr - cd->mcodebase - (5 + 5 + 2));
- continue;
- }
-
gen_resolvebranch(cd->mcodebase + bref->branchpos,
bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(200);
+ MCODECHECK(512);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ M_MOV_IMM(0, REG_ITMP2_XPC);
dseg_adddata(cd, cd->mcodeptr);
- i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
+ M_AADD_IMM32(bref->branchpos - 6, REG_ITMP2_XPC);
if (xcodeptr != NULL) {
- i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
+ M_JMP_IMM((xcodeptr - cd->mcodeptr) - 5);
} else {
xcodeptr = cd->mcodeptr;
- i386_push_reg(cd, REG_ITMP2_XPC);
-
- PREPARE_NATIVE_STACKINFO;
-
- i386_mov_imm_reg(cd, (s4) codegen_general_stubcalled, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
+ M_ASUB_IMM(4 * 4, REG_SP);
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- i386_mov_imm_reg(cd, (s4) &builtin_get_exceptionptrptr, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_RESULT, 0, REG_ITMP3);
- i386_mov_imm_membase(cd, 0, REG_RESULT, 0);
- i386_mov_reg_reg(cd, REG_ITMP3, REG_ITMP1_XPTR);
-#else
- i386_mov_imm_reg(cd, (s4) &_exceptionptr, REG_ITMP3);
- i386_mov_membase_reg(cd, REG_ITMP3, 0, REG_ITMP1_XPTR);
- i386_mov_imm_membase(cd, 0, REG_ITMP3, 0);
-#endif
- i386_push_imm(cd, 0);
- i386_push_reg(cd, REG_ITMP1_XPTR);
-
-/*get the fillInStackTrace Method ID. I simulate a native call here, because I do not want to mess around with the
-java stack at this point*/
- i386_mov_membase_reg(cd, REG_ITMP1_XPTR, OFFSET(java_objectheader, vftbl), REG_ITMP3);
- i386_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, class), REG_ITMP1);
- i386_push_imm(cd, (u4) utf_fillInStackTrace_desc);
- i386_push_imm(cd, (u4) utf_fillInStackTrace_name);
- i386_push_reg(cd, REG_ITMP1);
- i386_mov_imm_reg(cd, (s4) class_resolvemethod, REG_ITMP3);
- i386_call_reg(cd, REG_ITMP3);
-/*cleanup parameters of class_resolvemethod*/
- i386_alu_imm_reg(cd, I386_ADD,3*4 /*class reference + 2x string reference*/,REG_SP);
-/*prepare call to asm_calljavafunction2 */
- i386_push_imm(cd, 0);
- i386_push_imm(cd, TYPE_ADR); /* --> call block (TYPE,Exceptionptr), each 8 byte (make this dynamic) (JOWENN)*/
- i386_push_reg(cd, REG_SP);
- i386_push_imm(cd, sizeof(jni_callblock));
- i386_push_imm(cd, 1);
- i386_push_reg(cd, REG_RESULT);
-
- i386_mov_imm_reg(cd, (s4) asm_calljavafunction2, REG_ITMP3);
- i386_call_reg(cd, REG_ITMP3);
-
- /* check exceptionptr + fail (JOWENN)*/
-
- i386_alu_imm_reg(cd, I386_ADD,6*4,REG_SP);
-
- i386_pop_reg(cd, REG_ITMP1_XPTR);
- i386_pop_reg(cd, REG_ITMP3); /* just remove the no longer needed 0 from the stack*/
+ M_AST_IMM(0, REG_SP, 0 * 4);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_MOV(REG_SP, REG_ITMP3);
+ M_AADD_IMM(4 * 4, REG_ITMP3);
+ M_AST(REG_ITMP3, REG_SP, 1 * 4);
+ M_ALD(REG_ITMP3, REG_SP, (4 + parentargs_base) * 4);
+ M_AST(REG_ITMP3, REG_SP, 2 * 4);
+ M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
- REMOVE_NATIVE_STACKINFO;
+ M_MOV_IMM((ptrint) stacktrace_inline_fillInStackTrace, REG_ITMP3);
+ M_CALL(REG_ITMP3);
- i386_pop_reg(cd, REG_ITMP2_XPC);
+ M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ M_AADD_IMM(4 * 4, REG_SP);
- i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3);
+ M_MOV_IMM((ptrint) asm_handle_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
}
}
- /* generate null pointer check stubs */
+ /* generate code patching stub call code */
- xcodeptr = NULL;
-
- for (bref = cd->xnullrefs; bref != NULL; bref = bref->next) {
- if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- xcodeptr - cd->mcodebase - (5 + 5 + 2));
- continue;
- }
+ {
+ patchref *pref;
+ codegendata *tmpcd;
+ u8 mcode;
- gen_resolvebranch(cd->mcodebase + bref->branchpos,
- bref->branchpos,
- cd->mcodeptr - cd->mcodebase);
-
- MCODECHECK(100);
+ tmpcd = DNEW(codegendata);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
- dseg_adddata(cd, cd->mcodeptr);
- i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
-
- if (xcodeptr != NULL) {
- i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
-
- } else {
- xcodeptr = cd->mcodeptr;
-
- i386_push_reg(cd, REG_ITMP2_XPC);
+ for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
+ /* check code segment size */
- PREPARE_NATIVE_STACKINFO;
+ MCODECHECK(512);
-#if 0
- /* create native call block*/
- i386_alu_imm_reg(cd, I386_SUB, 3*4, REG_SP); /* build stack frame (4 * 4 bytes) */
+ /* Get machine code which is patched back in later. A */
+ /* `call rel32' is 5 bytes long. */
+ xcodeptr = cd->mcodebase + pref->branchpos;
+ mcode = *((u8 *) xcodeptr);
- i386_mov_imm_reg(cd, (s4) codegen_stubcalled,REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /*call codegen_stubcalled*/
+ /* patch in `call rel32' to call the following code */
- i386_mov_imm_reg(cd, (s4) builtin_asm_get_stackframeinfo,REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /*call builtin_asm_get_stackframeinfo*/
- i386_mov_imm_membase(cd, 0,REG_SP, 2*4); /* builtin */
- i386_mov_reg_membase(cd, REG_RESULT,REG_SP,1*4); /* save thread pointer to native call stack*/
- i386_mov_membase_reg(cd, REG_RESULT,0,REG_ITMP2); /* get old value of thread specific native call stack */
- i386_mov_reg_membase(cd, REG_ITMP2,REG_SP,0*4); /* store value on stack */
- i386_mov_reg_membase(cd, REG_SP,REG_RESULT,0); /* store pointer to new stack frame information */
-#endif
+ tmpcd->mcodeptr = xcodeptr; /* set dummy mcode pointer */
+ i386_call_imm(tmpcd, cd->mcodeptr - (xcodeptr + 5));
- i386_mov_imm_reg(cd, (u4) new_nullpointerexception, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
+ /* move pointer to java_objectheader onto stack */
- REMOVE_NATIVE_STACKINFO;
+#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+ (void) dseg_addaddress(cd, get_dummyLR()); /* monitorPtr */
+ off = dseg_addaddress(cd, NULL); /* vftbl */
-#if 0
- /* restore native call stack */
- i386_mov_membase_reg(cd, REG_SP,0,REG_ITMP2);
- i386_mov_membase_reg(cd, REG_SP,4,REG_ITMP3);
- i386_mov_reg_membase(cd, REG_ITMP2,REG_ITMP3,0);
- i386_alu_imm_reg(cd, I386_ADD,3*4,REG_SP);
+ M_MOV_IMM(0, REG_ITMP3);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_AADD_IMM(off, REG_ITMP3);
+ M_PUSH(REG_ITMP3);
+#else
+ M_PUSH_IMM(0);
#endif
- i386_pop_reg(cd, REG_ITMP2_XPC);
+ /* move machine code bytes and classinfo pointer into registers */
+
+ M_PUSH_IMM((ptrint) (mcode >> 32));
+ M_PUSH_IMM((ptrint) mcode);
+ M_PUSH_IMM((ptrint) pref->ref);
+ M_PUSH_IMM((ptrint) pref->patcher);
- i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3);
+ M_MOV_IMM((ptrint) asm_wrapper_patcher, REG_ITMP3);
+ M_JMP(REG_ITMP3);
}
}
}
- codegen_finish(m, cd, (u4) (cd->mcodeptr - cd->mcodebase));
+ codegen_finish(m, cd, (ptrint) (cd->mcodeptr - cd->mcodebase));
+
+ /* everything's ok */
+
+ return true;
}
-/* function createcompilerstub *************************************************
+/* createcompilerstub **********************************************************
- creates a stub routine which calls the compiler
+ Creates a stub routine which calls the compiler.
*******************************************************************************/
-#define COMPSTUBSIZE 12
+#define COMPILERSTUB_SIZE 12
u1 *createcompilerstub(methodinfo *m)
{
- u1 *s = CNEW(u1, COMPSTUBSIZE); /* memory to hold the stub */
- codegendata *cd = NEW(codegendata);
+ u1 *s; /* memory to hold the stub */
+ codegendata *cd;
+ s4 dumpsize;
+
+ s = CNEW(u1, COMPILERSTUB_SIZE);
+ /* mark start of dump memory area */
+
+ dumpsize = dump_size();
+
+ cd = DNEW(codegendata);
cd->mcodeptr = s;
- /* code for the stub */
- i386_mov_imm_reg(cd, (u4) m, REG_ITMP1);/* pass method pointer to compiler*/
+ i386_mov_imm_reg(cd, (ptrint) m, REG_ITMP1);
/* we use REG_ITMP3 cause ECX (REG_ITMP2) is used for patching */
- i386_mov_imm_reg(cd, (u4) asm_call_jit_compiler, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3); /* jump to compiler */
+ i386_mov_imm_reg(cd, (ptrint) asm_call_jit_compiler, REG_ITMP3);
+ i386_jmp_reg(cd, REG_ITMP3);
- /* free codegendata memory */
- codegen_close(m);
-
-#if defined(STATISTICS)
+#if defined(ENABLE_STATISTICS)
if (opt_stat)
- count_cstub_len += COMPSTUBSIZE;
+ count_cstub_len += COMPILERSTUB_SIZE;
#endif
- FREE(cd, codegendata);
+ /* release dump area */
+ dump_release(dumpsize);
+
return s;
}
-/* function removecompilerstub *************************************************
+/* createnativestub ************************************************************
- deletes a compilerstub from memory (simply by freeing it)
+ Creates a stub routine which calls a native method.
*******************************************************************************/
-void removecompilerstub(u1 *stub)
-{
- CFREE(stub, COMPSTUBSIZE);
-}
+#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+/* this way we can call the function directly with a memory call */
+static java_objectheader **(*callgetexceptionptrptr)() = builtin_get_exceptionptrptr;
+#endif
-/* function: createnativestub **************************************************
+u1 *createnativestub(functionptr f, methodinfo *m, codegendata *cd,
+ registerdata *rd, methoddesc *nmd)
+{
+ methoddesc *md;
+ s4 nativeparams;
+ s4 stackframesize;
+ s4 i, j; /* count variables */
+ s4 t;
+ s4 s1, s2, disp;
- creates a stub routine which calls a native method
+ /* set some variables */
-*******************************************************************************/
+ md = m->parseddesc;
+ nativeparams = (m->flags & ACC_STATIC) ? 2 : 1;
-#define NATIVESTUBSIZE 350
+ /* calculate stackframe size */
-#if defined(USE_THREADS) && defined(NATIVE_THREADS)
-static java_objectheader **(*callgetexceptionptrptr)() = builtin_get_exceptionptrptr;
-#endif
+ stackframesize =
+ sizeof(stackframeinfo) / SIZEOF_VOID_P +
+ sizeof(localref_table) / SIZEOF_VOID_P +
+ 1 + /* function pointer */
+ 4 * 4 + /* 4 arguments (start_native_call) */
+ nmd->memuse;
-void i386_native_stub_debug(void **p) {
- printf("Pos on stack: %p\n",p);
- printf("Return adress should be: %p\n",*p);
-}
+ /* create method header */
-void i386_native_stub_debug2(void **p) {
- printf("Pos on stack: %p\n",p);
- printf("Return for lookup is: %p\n",*p);
-}
+ (void) dseg_addaddress(cd, m); /* MethodPointer */
+ (void) dseg_adds4(cd, stackframesize * 4); /* FrameSize */
+ (void) dseg_adds4(cd, 0); /* IsSync */
+ (void) dseg_adds4(cd, 0); /* IsLeaf */
+ (void) dseg_adds4(cd, 0); /* IntSave */
+ (void) dseg_adds4(cd, 0); /* FltSave */
+ (void) dseg_addlinenumbertablesize(cd);
+ (void) dseg_adds4(cd, 0); /* ExTableSize */
-void traverseStackInfo() {
- void **p=builtin_asm_get_stackframeinfo();
+ /* initialize mcode variables */
- while ((*p)!=0) {
- methodinfo *m;
- printf("base addr:%p, methodinfo:%p\n",*p,(methodinfo*)((*p)+8));
- m=*((methodinfo**)((*p)+8));
- utf_display(m->name);
- printf("\n");
- p=*p;
+ cd->mcodeptr = (u1 *) cd->mcodebase;
+ cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize);
+
+ /* generate profiling code */
+
+ if (opt_prof) {
+ M_MOV_IMM((ptrint) m, REG_ITMP1);
+ M_IADD_IMM_MEMBASE(1, REG_ITMP1, OFFSET(methodinfo, executioncount));
}
-
-}
+ /* calculate stackframe size for native function */
-u1 *createnativestub(functionptr f, methodinfo *m)
-{
- u1 *s = CNEW(u1, NATIVESTUBSIZE); /* memory to hold the stub */
- int addmethod=0;
- u1 *tptr;
- int i;
- int stackframesize = 4+12; /* initial 4 bytes is space for jni env,
- + 4 byte thread pointer + 4 byte previous pointer + method info*/
- int stackframeoffset = 4;
+ M_ASUB_IMM(stackframesize * 4, REG_SP);
- int p, t;
+ if (runverbose) {
+ s4 p, t;
- void** callAddrPatchPos=0;
- u1* jmpInstrPos=0;
- void** jmpInstrPatchPos=0;
+ disp = stackframesize * 4;
- codegendata *cd = NEW(codegendata);
- registerdata *rd = NEW(registerdata);
- t_inlining_globals *id = NEW(t_inlining_globals);
+ M_ASUB_IMM(TRACE_ARGS_NUM * 8 + 4, REG_SP);
+
+ for (p = 0; p < md->paramcount && p < TRACE_ARGS_NUM; p++) {
+ t = md->paramtypes[p].type;
+ if (IS_INT_LNG_TYPE(t)) {
+ if (IS_2_WORD_TYPE(t)) {
+ M_ILD(REG_ITMP1, REG_SP,
+ 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
+ M_ILD(REG_ITMP2, REG_SP,
+ 4 + TRACE_ARGS_NUM * 8 + 4 + disp + 4);
+ M_IST(REG_ITMP1, REG_SP, p * 8);
+ M_IST(REG_ITMP2, REG_SP, p * 8 + 4);
+
+ } else if (t == TYPE_ADR) {
+ M_ALD(REG_ITMP1, REG_SP,
+ 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
+ M_CLR(REG_ITMP2);
+ M_AST(REG_ITMP1, REG_SP, p * 8);
+ M_AST(REG_ITMP2, REG_SP, p * 8 + 4);
- /* setup registers before using it */
- inlining_setup(m, id);
- reg_setup(m, rd, id);
+ } else {
+ M_ILD(EAX, REG_SP, 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
+ i386_cltd(cd);
+ M_IST(EAX, REG_SP, p * 8);
+ M_IST(EDX, REG_SP, p * 8 + 4);
+ }
- cd->mcodeptr = s;
+ } else {
+ if (!IS_2_WORD_TYPE(t)) {
+ i386_flds_membase(cd, REG_SP,
+ 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
+ i386_fstps_membase(cd, REG_SP, p * 8);
+ i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2);
+ M_IST(REG_ITMP2, REG_SP, p * 8 + 4);
- if (m->flags & ACC_STATIC) {
- stackframesize += 4;
- stackframeoffset += 4;
+ } else {
+ i386_fldl_membase(cd, REG_SP,
+ 4 + TRACE_ARGS_NUM * 8 + 4 + disp);
+ i386_fstpl_membase(cd, REG_SP, p * 8);
+ }
+ }
+ disp += (IS_2_WORD_TYPE(t)) ? 8 : 4;
+ }
+
+ M_CLR(REG_ITMP1);
+ for (p = md->paramcount; p < TRACE_ARGS_NUM; p++) {
+ M_IST(REG_ITMP1, REG_SP, p * 8);
+ M_IST(REG_ITMP1, REG_SP, p * 8 + 4);
+ }
+
+ M_AST_IMM((ptrint) m, REG_SP, TRACE_ARGS_NUM * 8);
+
+ M_MOV_IMM((ptrint) builtin_trace_args, REG_ITMP1);
+ M_CALL(REG_ITMP1);
+
+ M_AADD_IMM(TRACE_ARGS_NUM * 8 + 4, REG_SP);
}
- reg_init(m);
- descriptor2types(m); /* set paramcount and paramtypes */
-
-/*DEBUG*/
-/* i386_push_reg(cd, REG_SP);
- i386_mov_imm_reg(cd, (s4) i386_native_stub_debug, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- i386_pop_reg(cd, REG_ITMP1);*/
-
-
- /* if function is static, check for initialized */
-
- if (m->flags & ACC_STATIC) {
- /* if class isn't yet initialized, do it */
- if (!m->class->initialized) {
- s4 *header = (s4 *) s;
- *header = 0;/*extablesize*/
- header;
- *header = 0;/*line number table start*/
- header++;
- *header = 0;/*line number table size*/
- header++;
- *header = 0;/*fltsave*/
- header++;
- *header = 0;/*intsave*/
- header++;
- *header = 0;/*isleaf*/
- header++;
- *header = 0;/*issync*/
- header++;
- *header = 0;/*framesize*/
- header++;
- *header = (u4) m;/*methodpointer*/
- *header++;
- cd->mcodeptr = s = (u1 *) header;
- addmethod = 1;
-
- /* call helper function which patches this code */
- i386_mov_imm_reg(cd, (u4) m->class, REG_ITMP1);
- i386_mov_imm_reg(cd, (u4) asm_check_clinit, REG_ITMP2);
- i386_call_reg(cd, REG_ITMP2);
+ /* get function address (this must happen before the stackframeinfo) */
+
+#if !defined(ENABLE_STATICVM)
+ if (f == NULL) {
+ codegen_addpatchref(cd, cd->mcodeptr, PATCHER_resolve_native, m, 0);
+
+ if (opt_showdisassemble) {
+ M_NOP; M_NOP; M_NOP; M_NOP; M_NOP;
}
}
+#endif
- if (runverbose) {
- i386_alu_imm_reg(cd, I386_SUB, TRACE_ARGS_NUM * 8 + 4, REG_SP);
-
- for (p = 0; p < m->paramcount && p < TRACE_ARGS_NUM; p++) {
- t = m->paramtypes[p];
- if (IS_INT_LNG_TYPE(t)) {
- if (IS_2_WORD_TYPE(t)) {
- i386_mov_membase_reg(cd, REG_SP, 4 + (TRACE_ARGS_NUM + p) * 8 + 4, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, 4 + (TRACE_ARGS_NUM + p) * 8 + 4 + 4, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, p * 8 + 4);
+ M_AST_IMM((ptrint) f, REG_SP, 4 * 4);
- } else if (t == TYPE_ADR) {
- i386_mov_membase_reg(cd, REG_SP, 4 + (TRACE_ARGS_NUM + p) * 8 + 4, REG_ITMP1);
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP2, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, p * 8 + 4);
-
- } else {
- i386_mov_membase_reg(cd, REG_SP, 4 + (TRACE_ARGS_NUM + p) * 8 + 4, EAX);
- i386_cltd(cd);
- i386_mov_reg_membase(cd, EAX, REG_SP, p * 8);
- i386_mov_reg_membase(cd, EDX, REG_SP, p * 8 + 4);
- }
-
- } else {
- if (!IS_2_WORD_TYPE(t)) {
- i386_flds_membase(cd, REG_SP, 4 + (TRACE_ARGS_NUM + p) * 8 + 4);
- i386_fstps_membase(cd, REG_SP, p * 8);
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP2, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, p * 8 + 4);
-
- } else {
- i386_fldl_membase(cd, REG_SP, 4 + (TRACE_ARGS_NUM + p) * 8 + 4);
- i386_fstpl_membase(cd, REG_SP, p * 8);
- }
- }
- }
-
- i386_alu_reg_reg(cd, I386_XOR, REG_ITMP1, REG_ITMP1);
- for (p = m->paramcount; p < TRACE_ARGS_NUM; p++) {
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4);
- }
+ /* Mark the whole fpu stack as free for native functions (only for saved */
+ /* register count == 0). */
- i386_mov_imm_membase(cd, (s4) m, REG_SP, TRACE_ARGS_NUM * 8);
+ i386_ffree_reg(cd, 0);
+ i386_ffree_reg(cd, 1);
+ i386_ffree_reg(cd, 2);
+ i386_ffree_reg(cd, 3);
+ i386_ffree_reg(cd, 4);
+ i386_ffree_reg(cd, 5);
+ i386_ffree_reg(cd, 6);
+ i386_ffree_reg(cd, 7);
- i386_mov_imm_reg(cd, (s4) builtin_trace_args, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
+ /* prepare data structures for native function call */
- i386_alu_imm_reg(cd, I386_ADD, TRACE_ARGS_NUM * 8 + 4, REG_SP);
- }
+ M_MOV(REG_SP, REG_ITMP1);
+ M_AADD_IMM(stackframesize * 4, REG_ITMP1);
- /*
- * mark the whole fpu stack as free for native functions
- * (only for saved register count == 0)
- */
- i386_ffree_reg(cd, 0);
- i386_ffree_reg(cd, 1);
- i386_ffree_reg(cd, 2);
- i386_ffree_reg(cd, 3);
- i386_ffree_reg(cd, 4);
- i386_ffree_reg(cd, 5);
- i386_ffree_reg(cd, 6);
- i386_ffree_reg(cd, 7);
+ M_AST(REG_ITMP1, REG_SP, 0 * 4);
+ M_IST_IMM(0, REG_SP, 1 * 4);
+ dseg_adddata(cd, cd->mcodeptr);
- /* calculate stackframe size for native function */
- tptr = m->paramtypes;
- for (i = 0; i < m->paramcount; i++) {
- switch (*tptr++) {
- case TYPE_INT:
- case TYPE_FLT:
- case TYPE_ADR:
- stackframesize += 4;
- break;
-
- case TYPE_LNG:
- case TYPE_DBL:
- stackframesize += 8;
- break;
-
- default:
- panic("unknown parameter type in native function");
- }
- }
+ M_MOV(REG_SP, REG_ITMP2);
+ M_AADD_IMM(stackframesize * 4 + SIZEOF_VOID_P, REG_ITMP2);
- i386_alu_imm_reg(cd, I386_SUB, stackframesize, REG_SP);
-
-/* CREATE DYNAMIC STACK INFO -- BEGIN*/
- i386_mov_imm_membase(cd, (s4) m, REG_SP,stackframesize-4);
- i386_mov_imm_reg(cd, (s4) builtin_asm_get_stackframeinfo, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_RESULT,REG_SP,stackframesize-8); /*save thread specific pointer*/
- i386_mov_membase_reg(cd, REG_RESULT,0,REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2,REG_SP,stackframesize-12); /*save previous value of memory adress pointed to by thread specific pointer*/
- i386_mov_reg_reg(cd, REG_SP,REG_ITMP2);
- i386_alu_imm_reg(cd, I386_ADD,stackframesize-12,REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2,REG_RESULT,0);
-
-/*TESTING ONLY */
-/* i386_mov_imm_membase(cd, (s4) m, REG_SP,stackframesize-4);
- i386_mov_imm_membase(cd, (s4) m, REG_SP,stackframesize-8);
- i386_mov_imm_membase(cd, (s4) m, REG_SP,stackframesize-12);*/
-
-/* CREATE DYNAMIC STACK INFO -- END*/
-
-/* RESOLVE NATIVE METHOD -- BEGIN*/
-#ifndef STATIC_CLASSPATH
- if (f==0) {
- log_text("Dynamic classpath: preparing for delayed native function resolving");
- i386_jmp_imm(cd,0);
- jmpInstrPos=cd->mcodeptr-4;
- /*patchposition*/
- i386_mov_imm_reg(cd,jmpInstrPos,REG_ITMP1);
- i386_push_reg(cd,REG_ITMP1);
- /*jmp offset*/
- i386_mov_imm_reg(cd,0,REG_ITMP1);
- jmpInstrPatchPos=cd->mcodeptr-4;
- i386_push_reg(cd,REG_ITMP1);
- /*position of call address to patch*/
- i386_mov_imm_reg(cd,0,REG_ITMP1);
- callAddrPatchPos=(cd->mcodeptr-4);
- i386_push_reg(cd,REG_ITMP1);
- /*method info structure*/
- i386_mov_imm_reg(cd,(s4) m, REG_ITMP1);
- i386_push_reg(cd,REG_ITMP1);
- /*call resolve functions*/
- i386_mov_imm_reg(cd, (s4)codegen_resolve_native,REG_ITMP1);
- i386_call_reg(cd,REG_ITMP1);
- /*cleanup*/
- i386_pop_reg(cd,REG_ITMP1);
- i386_pop_reg(cd,REG_ITMP1);
- i386_pop_reg(cd,REG_ITMP1);
- i386_pop_reg(cd,REG_ITMP1);
- /*fix jmp offset replacement*/
- (*jmpInstrPatchPos)=cd->mcodeptr-jmpInstrPos-4;
- } else log_text("Dynamic classpath: immediate native function resolution possible");
-#endif
-/* RESOLVE NATIVE METHOD -- END*/
-
-
-
- tptr = m->paramtypes;
- for (i = 0; i < m->paramcount; i++) {
- switch (*tptr++) {
- case TYPE_INT:
- case TYPE_FLT:
- case TYPE_ADR:
- i386_mov_membase_reg(cd, REG_SP, stackframesize + (1 * 4) + i * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, stackframeoffset);
- stackframeoffset += 4;
- break;
-
- case TYPE_LNG:
- case TYPE_DBL:
- i386_mov_membase_reg(cd, REG_SP, stackframesize + (1 * 4) + i * 8, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_SP, stackframesize + (1 * 4) + i * 8 + 4, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, stackframeoffset);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, stackframeoffset + 4);
- stackframeoffset += 8;
- break;
-
- default:
- panic("unknown parameter type in native function");
- }
- }
+ M_AST(REG_ITMP2, REG_SP, 2 * 4);
+ M_ALD(REG_ITMP3, REG_SP, stackframesize * 4);
+ M_AST(REG_ITMP3, REG_SP, 3 * 4);
+ M_MOV_IMM((ptrint) codegen_start_native_call, REG_ITMP1);
+ M_CALL(REG_ITMP1);
+
+ M_ALD(REG_ITMP3, REG_SP, 4 * 4);
+
+ /* copy arguments into new stackframe */
+
+ for (i = md->paramcount - 1, j = i + nativeparams; i >= 0; i--, j--) {
+ t = md->paramtypes[i].type;
+
+ if (!md->params[i].inmemory) {
+ /* no integer argument registers */
+ } else { /* float/double in memory can be copied like int/longs */
+ s1 = (md->params[i].regoff + stackframesize + 1) * 4;
+ s2 = nmd->params[j].regoff * 4;
- if (m->flags & ACC_STATIC) {
- /* put class into second argument */
- i386_mov_imm_membase(cd, (s4) m->class, REG_SP, 4);
+ M_ILD(REG_ITMP1, REG_SP, s1);
+ M_IST(REG_ITMP1, REG_SP, s2);
+ if (IS_2_WORD_TYPE(t)) {
+ M_ILD(REG_ITMP1, REG_SP, s1 + 4);
+ M_IST(REG_ITMP1, REG_SP, s2 + 4);
+ }
+ }
}
+ /* if function is static, put class into second argument */
+
+ if (m->flags & ACC_STATIC)
+ M_AST_IMM((ptrint) m->class, REG_SP, 1 * 4);
+
/* put env into first argument */
- i386_mov_imm_membase(cd, (s4) &env, REG_SP, 0);
- i386_mov_imm_reg(cd, (s4) f, REG_ITMP1);
-#ifndef STATIC_CLASSPATH
- if (f==0)
- (*callAddrPatchPos)=(cd->mcodeptr-4);
-#endif
- i386_call_reg(cd, REG_ITMP1);
+ M_AST_IMM((ptrint) &env, REG_SP, 0 * 4);
+
+ /* call the native function */
-/*REMOVE DYNAMIC STACK INFO -BEGIN */
- i386_push_reg(cd, REG_RESULT2);
- i386_mov_membase_reg(cd, REG_SP,stackframesize-8,REG_ITMP2); /*old value*/
- i386_mov_membase_reg(cd, REG_SP,stackframesize-4,REG_RESULT2); /*pointer*/
- i386_mov_reg_membase(cd, REG_ITMP2,REG_RESULT2,0);
- i386_pop_reg(cd, REG_RESULT2);
-/*REMOVE DYNAMIC STACK INFO -END */
+ M_CALL(REG_ITMP3);
- i386_alu_imm_reg(cd, I386_ADD, stackframesize, REG_SP);
+ /* save return value */
+ if (IS_INT_LNG_TYPE(md->returntype.type)) {
+ if (IS_2_WORD_TYPE(md->returntype.type))
+ M_IST(REG_RESULT2, REG_SP, 2 * 4);
+ M_IST(REG_RESULT, REG_SP, 1 * 4);
+
+ } else {
+ if (IS_2_WORD_TYPE(md->returntype.type))
+ i386_fstl_membase(cd, REG_SP, 1 * 4);
+ else
+ i386_fsts_membase(cd, REG_SP, 1 * 4);
+ }
+
+ /* remove data structures for native function call */
+
+ M_MOV(REG_SP, REG_ITMP1);
+ M_AADD_IMM(stackframesize * 4, REG_ITMP1);
+
+ M_AST(REG_ITMP1, REG_SP, 0 * 4);
+ M_MOV_IMM((ptrint) codegen_finish_native_call, REG_ITMP1);
+ M_CALL(REG_ITMP1);
if (runverbose) {
- i386_alu_imm_reg(cd, I386_SUB, 4 + 8 + 8 + 4, REG_SP);
-
- i386_mov_imm_membase(cd, (u4) m, REG_SP, 0);
-
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, 4);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, 4 + 4);
-
- i386_fstl_membase(cd, REG_SP, 4 + 8);
- i386_fsts_membase(cd, REG_SP, 4 + 8 + 8);
+ /* restore return value */
- i386_mov_imm_reg(cd, (u4) builtin_displaymethodstop, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1);
-
- i386_mov_membase_reg(cd, REG_SP, 4, REG_RESULT);
- i386_mov_membase_reg(cd, REG_SP, 4 + 4, REG_RESULT2);
-
- i386_alu_imm_reg(cd, I386_ADD, 4 + 8 + 8 + 4, REG_SP);
+ if (IS_INT_LNG_TYPE(md->returntype.type)) {
+ if (IS_2_WORD_TYPE(md->returntype.type))
+ M_ILD(REG_RESULT2, REG_SP, 2 * 4);
+ M_ILD(REG_RESULT, REG_SP, 1 * 4);
+
+ } else {
+ if (IS_2_WORD_TYPE(md->returntype.type))
+ i386_fldl_membase(cd, REG_SP, 1 * 4);
+ else
+ i386_flds_membase(cd, REG_SP, 1 * 4);
+ }
+
+ M_ASUB_IMM(4 + 8 + 8 + 4, REG_SP);
+
+ M_AST_IMM((ptrint) m, REG_SP, 0);
+
+ M_IST(REG_RESULT, REG_SP, 4);
+ M_IST(REG_RESULT2, REG_SP, 4 + 4);
+
+ i386_fstl_membase(cd, REG_SP, 4 + 8);
+ i386_fsts_membase(cd, REG_SP, 4 + 8 + 8);
+
+ M_MOV_IMM((ptrint) builtin_displaymethodstop, REG_ITMP1);
+ M_CALL(REG_ITMP1);
+
+ M_AADD_IMM(4 + 8 + 8 + 4, REG_SP);
}
+ /* check for exception */
- /* we can't use REG_ITMP3 == REG_RESULT2 */
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- i386_push_reg(cd, REG_RESULT);
- i386_push_reg(cd, REG_RESULT2);
- i386_call_mem(cd, (s4) &callgetexceptionptrptr);
- i386_mov_membase_reg(cd, REG_RESULT, 0, REG_ITMP2);
- i386_test_reg_reg(cd, REG_ITMP2, REG_ITMP2);
- i386_pop_reg(cd, REG_RESULT2);
- i386_pop_reg(cd, REG_RESULT);
+/* i386_call_mem(cd, (ptrint) builtin_get_exceptionptrptr); */
+ i386_call_mem(cd, (ptrint) &callgetexceptionptrptr);
#else
- i386_mov_imm_reg(cd, (s4) &_exceptionptr, REG_ITMP2);
- i386_mov_membase_reg(cd, REG_ITMP2, 0, REG_ITMP2);
- i386_test_reg_reg(cd, REG_ITMP2, REG_ITMP2);
+ M_MOV_IMM((ptrint) &_exceptionptr, REG_RESULT);
#endif
- i386_jcc(cd, I386_CC_NE, 1);
+ /* we can't use REG_ITMP3 == REG_RESULT2 */
+ M_ALD(REG_ITMP2, REG_RESULT, 0);
+
+ /* restore return value */
- i386_ret(cd);
+ if (IS_INT_LNG_TYPE(md->returntype.type)) {
+ if (IS_2_WORD_TYPE(md->returntype.type))
+ M_ILD(REG_RESULT2, REG_SP, 2 * 4);
+ M_ILD(REG_RESULT, REG_SP, 1 * 4);
+
+ } else {
+ if (IS_2_WORD_TYPE(md->returntype.type))
+ i386_fldl_membase(cd, REG_SP, 1 * 4);
+ else
+ i386_flds_membase(cd, REG_SP, 1 * 4);
+ }
+
+ M_AADD_IMM(stackframesize * 4, REG_SP);
+
+ M_TEST(REG_ITMP2);
+ M_BNE(1);
+
+ M_RET;
+
+ /* handle exception */
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
i386_push_reg(cd, REG_ITMP2);
- i386_call_mem(cd, (s4) &callgetexceptionptrptr);
+/* i386_call_mem(cd, (ptrint) builtin_get_exceptionptrptr); */
+ i386_call_mem(cd, (ptrint) &callgetexceptionptrptr);
i386_mov_imm_membase(cd, 0, REG_RESULT, 0);
i386_pop_reg(cd, REG_ITMP1_XPTR);
#else
- i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1_XPTR);
- i386_mov_imm_reg(cd, (s4) &_exceptionptr, REG_ITMP2);
+ M_MOV(REG_ITMP2, REG_ITMP1_XPTR);
+ M_MOV_IMM((ptrint) &_exceptionptr, REG_ITMP2);
i386_mov_imm_membase(cd, 0, REG_ITMP2, 0);
#endif
- i386_mov_membase_reg(cd, REG_SP, 0, REG_ITMP2_XPC);
- i386_alu_imm_reg(cd, I386_SUB, 2, REG_ITMP2_XPC);
+ M_ALD(REG_ITMP2_XPC, REG_SP, 0);
+ M_ASUB_IMM(2, REG_ITMP2_XPC);
- i386_mov_imm_reg(cd, (s4) asm_handle_nat_exception, REG_ITMP3);
- i386_jmp_reg(cd, REG_ITMP3);
+ M_MOV_IMM((ptrint) asm_handle_nat_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
- if (addmethod) {
- codegen_insertmethod(s, cd->mcodeptr);
- }
-#if 0
- dolog_plain("native stubentry: %p, stubsize: %x (for %d params) --", (s4)s,(s4) (cd->mcodeptr - s), m->paramcount);
- utf_display(m->name);
- dolog_plain("\n");
-#endif
+ /* process patcher calls **************************************************/
- /* free codegendata memory */
- codegen_close(m);
+ {
+ u1 *xcodeptr;
+ patchref *pref;
+ codegendata *tmpcd;
+ u8 mcode;
-#if defined(STATISTICS)
- if (opt_stat)
- count_nstub_len += NATIVESTUBSIZE;
-#endif
+ tmpcd = DNEW(codegendata);
- FREE(cd, codegendata);
- FREE(rd, registerdata);
- FREE(id, t_inlining_globals);
+ for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
+ /* Get machine code which is patched back in later. A */
+ /* `call rel32' is 5 bytes long. */
- return s;
-}
+ xcodeptr = cd->mcodebase + pref->branchpos;
+ mcode = *((u8 *) xcodeptr);
+ /* patch in `call rel32' to call the following code */
-/* function: removenativestub **************************************************
+ tmpcd->mcodeptr = xcodeptr; /* set dummy mcode pointer */
+ i386_call_imm(tmpcd, cd->mcodeptr - (xcodeptr + 5));
- removes a previously created native-stub from memory
-
-*******************************************************************************/
+ /* move pointer to java_objectheader onto stack */
-void removenativestub(u1 *stub)
-{
- CFREE(stub, NATIVESTUBSIZE);
+#if defined(USE_THREADS) && defined(NATIVE_THREADS)
+ /* create a virtual java_objectheader */
+
+ (void) dseg_addaddress(cd, get_dummyLR()); /* monitorPtr */
+ disp = dseg_addaddress(cd, NULL); /* vftbl */
+
+ M_MOV_IMM(0, REG_ITMP3);
+ dseg_adddata(cd, cd->mcodeptr);
+ M_AADD_IMM(disp, REG_ITMP3);
+ M_PUSH(REG_ITMP3);
+#else
+ M_PUSH_IMM(0);
+#endif
+
+ /* move machine code bytes and classinfo pointer onto stack */
+
+ M_PUSH_IMM((ptrint) (mcode >> 32));
+ M_PUSH_IMM((ptrint) mcode);
+ M_PUSH_IMM((ptrint) pref->ref);
+ M_PUSH_IMM((ptrint) pref->patcher);
+
+ M_MOV_IMM((ptrint) asm_wrapper_patcher, REG_ITMP3);
+ M_JMP(REG_ITMP3);
+ }
+ }
+
+ codegen_finish(m, cd, (s4) ((u1 *) cd->mcodeptr - cd->mcodebase));
+
+ return m->entrypoint;
}
projects / cacao.git / blobdiff