-/* jit/i386/codegen.c - machine code generator for i386
+/* vm/jit/i386/codegen.c - machine code generator for i386
- Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
- Institut f. Computersprachen, TU Wien
- R. Grafl, A. Krall, C. Kruegel, C. Oates, R. Obermaisser, M. Probst,
- S. Ring, E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich,
- J. Wenninger
+ Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
+ R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
+ C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
+ Institut f. Computersprachen - TU Wien
This file is part of CACAO.
Authors: Andreas Krall
Christian Thalinger
- $Id: codegen.c 1351 2004-07-22 22:39:05Z twisti $
+ Changes: Joseph Wenninger
+
+ $Id: codegen.c 1735 2004-12-07 14:33:27Z twisti $
*/
+
#define _GNU_SOURCE
-#include "global.h"
#include <stdio.h>
-#include <signal.h>
-#include <sys/ucontext.h>
-#include "types.h"
-#include "main.h"
-#include "builtin.h"
-#include "asmpart.h"
-#include "jni.h"
-#include "loader.h"
-#include "tables.h"
-#include "native.h"
-#include "jit/jit.h"
-#include "jit/parse.h"
-#include "jit/reg.h"
-#include "jit/i386/codegen.h"
-#include "jit/i386/emitfuncs.h"
-
-/* include independent code generation stuff */
-#include "jit/codegen.inc"
-#include "jit/reg.inc"
+#include <ucontext.h>
+#ifdef __FreeBSD__
+#include <machine/signal.h>
+#endif
+
+#include "config.h"
+#include "native/jni.h"
+#include "native/native.h"
+#include "vm/builtin.h"
+#include "vm/exceptions.h"
+#include "vm/global.h"
+#include "vm/loader.h"
+#include "vm/tables.h"
+#include "vm/jit/asmpart.h"
+#include "vm/jit/jit.h"
+#include "vm/jit/parse.h"
+#include "vm/jit/reg.h"
+#include "vm/jit/i386/codegen.h"
+#include "vm/jit/i386/emitfuncs.h"
+#include "vm/jit/i386/types.h"
+#include "vm/jit/i386/asmoffsets.h"
/* register descripton - array ************************************************/
/* #define REG_END -1 last entry in tables */
-/*
- we initially try to use %edx as scratch register, it cannot be used if we
- have one of these ICMDs:
- LMUL, LMULCONST, IDIV, IREM, LALOAD, AASTORE, LASTORE, IASTORE, CASTORE,
- SASTORE, BASTORE, INSTANCEOF, CHECKCAST, I2L, F2L, D2L
-*/
-int nregdescint[] = {
- REG_RET, REG_TMP, REG_TMP, REG_TMP, REG_RES, REG_SAV, REG_SAV, REG_SAV,
+static int nregdescint[] = {
+ REG_RET, REG_RES, REG_RES, REG_TMP, REG_RES, REG_SAV, REG_SAV, REG_SAV,
REG_END
};
-int nregdescfloat[] = {
+static int nregdescfloat[] = {
/* rounding problems with callee saved registers */
/* REG_SAV, REG_SAV, REG_SAV, REG_SAV, REG_TMP, REG_TMP, REG_RES, REG_RES, */
/* REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_RES, REG_RES, */
};
+/*******************************************************************************
+
+ include independent code generation stuff -- include after register
+ descriptions to avoid extern definitions
+
+*******************************************************************************/
+
+#include "vm/jit/codegen.inc"
+#include "vm/jit/reg.inc"
+#ifdef LSRA
+#include "vm/jit/lsra.inc"
+#endif
+
void codegen_stubcalled() {
log_text("Stub has been called");
}
void thread_restartcriticalsection(ucontext_t *uc)
{
void *critical;
+#ifdef __FreeBSD__
+ if ((critical = thread_checkcritical((void*) uc->uc_mcontext.mc_eip)) != NULL)
+ uc->uc_mcontext.mc_eip = (u4) critical;
+#else
if ((critical = thread_checkcritical((void*) uc->uc_mcontext.gregs[REG_EIP])) != NULL)
uc->uc_mcontext.gregs[REG_EIP] = (u4) critical;
+
+#endif
}
#endif
-#define PREPARE_NATIVE_STACKINFO \
- i386_push_reg(cd, REG_ITMP1); /*save itmp1, needed by some stubs */ \
- i386_alu_imm_reg(cd, I386_SUB, 2*4, REG_SP); /* build stack frame (2 * 4 bytes), together with previous =3*4 */ \
- i386_mov_imm_reg(cd, (s4) codegen_stubcalled,REG_ITMP1); \
- i386_call_reg(cd, REG_ITMP1); /*call codegen_stubcalled*/ \
- i386_mov_imm_reg(cd, (s4) builtin_asm_get_stackframeinfo,REG_ITMP1); \
- i386_call_reg(cd, REG_ITMP1); /*call builtin_asm_get_stackframeinfo*/ \
- i386_mov_reg_membase(cd, REG_RESULT,REG_SP,1*4); /* save thread pointer to native call stack*/ \
- i386_mov_membase_reg(cd, REG_RESULT,0,REG_ITMP2); /* get old value of thread specific native call stack */ \
- i386_mov_reg_membase(cd, REG_ITMP2,REG_SP,0*4); /* store value on stack */ \
- i386_mov_reg_membase(cd, REG_SP,REG_RESULT,0); /* store pointer to new stack frame information */ \
- i386_mov_membase_reg(cd, REG_SP,2*4,REG_ITMP1); /* restore ITMP1, need for some stubs*/ \
- i386_mov_imm_membase(cd, 0,REG_SP, 2*4); /* builtin */
-
-
-#define REMOVE_NATIVE_STACKINFO \
- i386_mov_membase_reg(cd, REG_SP,0,REG_ITMP2); \
- i386_mov_membase_reg(cd, REG_SP,4,REG_ITMP3); \
- i386_mov_reg_membase(cd, REG_ITMP2,REG_ITMP3,0); \
- i386_alu_imm_reg(cd, I386_ADD,3*4,REG_SP);
-
/* NullPointerException signal handler for hardware null pointer check */
sigset_t nsig;
/* long faultaddr; */
- struct ucontext *_uc = (struct ucontext *) _p;
- struct sigcontext *sigctx = (struct sigcontext *) &_uc->uc_mcontext;
+#ifdef __FreeBSD__
+ ucontext_t *_uc = (ucontext_t *) _p;
+ mcontext_t *sigctx = (mcontext_t *) &_uc->uc_mcontext;
+#else
+ struct ucontext *_uc = (struct ucontext *) _p;
+ struct sigcontext *sigctx = (struct sigcontext *) &_uc->uc_mcontext;
+#endif
struct sigaction act;
/* Reset signal handler - necessary for SysV, does no harm for BSD */
/* if (faultaddr == 0) { */
/* signal(sig, (void *) catch_NullPointerException); */
- act.sa_sigaction = (void *) catch_NullPointerException;
+ act.sa_sigaction = (functionptr) catch_NullPointerException;
act.sa_flags = SA_SIGINFO;
sigaction(sig, &act, NULL); /* reinstall handler */
- sigemptyset(&nsig);
- sigaddset(&nsig, sig);
- sigprocmask(SIG_UNBLOCK, &nsig, NULL); /* unblock signal */
+ sigemptyset(&nsig);
+ sigaddset(&nsig, sig);
+ sigprocmask(SIG_UNBLOCK, &nsig, NULL); /* unblock signal */
- sigctx->ecx = sigctx->eip; /* REG_ITMP2_XPC */
- sigctx->eax = (u4) string_java_lang_NullPointerException;
- sigctx->eip = (u4) asm_throw_and_handle_exception;
-
- return;
+#ifdef __FreeBSD__
+ sigctx->mc_ecx = sigctx->mc_eip; /* REG_ITMP2_XPC*/
+ sigctx->mc_eax = (u4) string_java_lang_NullPointerException;
+ sigctx->mc_eip = (u4) asm_throw_and_handle_exception;
+#else
+ sigctx->ecx = sigctx->eip; /* REG_ITMP2_XPC */
+ sigctx->eax = (u4) string_java_lang_NullPointerException;
+ sigctx->eip = (u4) asm_throw_and_handle_exception;
+#endif
+ return;
/* } else { */
/* faultaddr += (long) ((instr << 16) >> 16); */
/* void **_p = (void **) &sig; */
/* struct sigcontext *sigctx = (struct sigcontext *) ++_p; */
- struct ucontext *_uc = (struct ucontext *) _p;
- struct sigcontext *sigctx = (struct sigcontext *) &_uc->uc_mcontext;
+
+#ifdef __FreeBSD__
+ ucontext_t *_uc = (ucontext_t *) _p;
+ mcontext_t *sigctx = (mcontext_t *) &_uc->uc_mcontext;
+#else
+ struct ucontext *_uc = (struct ucontext *) _p;
+ struct sigcontext *sigctx = (struct sigcontext *) &_uc->uc_mcontext;
+#endif
+
struct sigaction act;
/* Reset signal handler - necessary for SysV, does no harm for BSD */
/* signal(sig, (void *) catch_ArithmeticException); */
- act.sa_sigaction = (void *) catch_ArithmeticException;
+ act.sa_sigaction = (functionptr) catch_ArithmeticException;
act.sa_flags = SA_SIGINFO;
sigaction(sig, &act, NULL); /* reinstall handler */
sigaddset(&nsig, sig);
sigprocmask(SIG_UNBLOCK, &nsig, NULL); /* unblock signal */
- sigctx->ecx = sigctx->eip; /* REG_ITMP2_XPC */
+#ifdef __FreeBSD__
+ sigctx->mc_ecx = sigctx->mc_eip; /* REG_ITMP2_XPC */
+ sigctx->mc_eip = (u4) asm_throw_and_handle_hardware_arithmetic_exception;
+#else
+ sigctx->ecx = sigctx->eip; /* REG_ITMP2_XPC */
sigctx->eip = (u4) asm_throw_and_handle_hardware_arithmetic_exception;
-
+#endif
return;
}
struct sigaction act;
/* install signal handlers we need to convert to exceptions */
+ sigemptyset(&act.sa_mask);
if (!checknull) {
#if defined(SIGSEGV)
/* signal(SIGSEGV, (void *) catch_NullPointerException); */
- act.sa_sigaction = (void *) catch_NullPointerException;
+ act.sa_sigaction = (functionptr) catch_NullPointerException;
act.sa_flags = SA_SIGINFO;
sigaction(SIGSEGV, &act, NULL);
#endif
#if defined(SIGBUS)
/* signal(SIGBUS, (void *) catch_NullPointerException); */
- act.sa_sigaction = (void *) catch_NullPointerException;
+ act.sa_sigaction = (functionptr) catch_NullPointerException;
act.sa_flags = SA_SIGINFO;
sigaction(SIGBUS, &act, NULL);
#endif
}
/* signal(SIGFPE, (void *) catch_ArithmeticException); */
- act.sa_sigaction = (void *) catch_ArithmeticException;
+ act.sa_sigaction = (functionptr) catch_ArithmeticException;
act.sa_flags = SA_SIGINFO;
sigaction(SIGFPE, &act, NULL);
}
*******************************************************************************/
-void codegen(methodinfo *m)
+void codegen(methodinfo *m, codegendata *cd, registerdata *rd)
{
- int len, s1, s2, s3, d;
- s4 a;
+ s4 len, s1, s2, s3, d;
+ s4 a;
stackptr src;
varinfo *var;
basicblock *bptr;
instruction *iptr;
- registerdata *r;
- codegendata *cd;
s4 parentargs_base;
u2 currentline;
s4 fpu_st_offset = 0;
s4 i, p, pa, t, l;
s4 savedregs_num = 0;
- /* keep code size smaller */
- r = m->registerdata;
- cd = m->codegendata;
-
/* space to save used callee saved registers */
- savedregs_num += (r->savintregcnt - r->maxsavintreguse);
- savedregs_num += (r->savfltregcnt - r->maxsavfltreguse);
+ savedregs_num += (rd->savintregcnt - rd->maxsavintreguse);
+ savedregs_num += (rd->savfltregcnt - rd->maxsavfltreguse);
- parentargs_base = r->maxmemuse + savedregs_num;
+ parentargs_base = rd->maxmemuse + savedregs_num;
+
#if defined(USE_THREADS) /* space to save argument of monitor_enter */
if (checksync && (m->flags & ACC_SYNCHRONIZED))
/* create method header */
- (void) dseg_addaddress(m, m); /* MethodPointer */
- (void) dseg_adds4(m, parentargs_base * 8); /* FrameSize */
+ (void) dseg_addaddress(cd, m); /* MethodPointer */
+ (void) dseg_adds4(cd, parentargs_base * 8); /* FrameSize */
#if defined(USE_THREADS)
*/
if (checksync && (m->flags & ACC_SYNCHRONIZED))
- (void) dseg_adds4(m, (r->maxmemuse + 1) * 8); /* IsSync */
+ (void) dseg_adds4(cd, (rd->maxmemuse + 1) * 8); /* IsSync */
else
#endif
- (void) dseg_adds4(m, 0); /* IsSync */
+ (void) dseg_adds4(cd, 0); /* IsSync */
- (void) dseg_adds4(m, m->isleafmethod); /* IsLeaf */
- (void) dseg_adds4(m, r->savintregcnt - r->maxsavintreguse); /* IntSave */
- (void) dseg_adds4(m, r->savfltregcnt - r->maxsavfltreguse); /* FltSave */
+ (void) dseg_adds4(cd, m->isleafmethod); /* IsLeaf */
+ (void) dseg_adds4(cd, rd->savintregcnt - rd->maxsavintreguse); /* IntSave */
+ (void) dseg_adds4(cd, rd->savfltregcnt - rd->maxsavfltreguse); /* FltSave */
/* adds a reference for the length of the line number counter. We don't
know the size yet, since we evaluate the information during code
generation, to save one additional iteration over the whole
instructions. During code optimization the position could have changed
to the information gotten from the class file */
- (void) dseg_addlinenumbertablesize(m);
+ (void) dseg_addlinenumbertablesize(cd);
- (void) dseg_adds4(m, m->exceptiontablelength); /* ExTableSize */
+ (void) dseg_adds4(cd, cd->exceptiontablelength); /* ExTableSize */
/* create exception table */
- for (ex = m->exceptiontable; ex != NULL; ex = ex->down) {
- dseg_addtarget(m, ex->start);
- dseg_addtarget(m, ex->end);
- dseg_addtarget(m, ex->handler);
- (void) dseg_addaddress(m, ex->catchtype);
+ for (ex = cd->exceptiontable; ex != NULL; ex = ex->down) {
+ dseg_addtarget(cd, ex->start);
+ dseg_addtarget(cd, ex->end);
+ dseg_addtarget(cd, ex->handler);
+ (void) dseg_addaddress(cd, ex->catchtype);
}
/* save return address and used callee saved registers */
p = parentargs_base;
- for (i = r->savintregcnt - 1; i >= r->maxsavintreguse; i--) {
- p--; i386_mov_reg_membase(cd, r->savintregs[i], REG_SP, p * 8);
+ for (i = rd->savintregcnt - 1; i >= rd->maxsavintreguse; i--) {
+ p--; i386_mov_reg_membase(cd, rd->savintregs[i], REG_SP, p * 8);
}
- for (i = r->savfltregcnt - 1; i >= r->maxsavfltreguse; i--) {
- p--; i386_fld_reg(cd, r->savfltregs[i]); i386_fstpl_membase(cd, REG_SP, p * 8);
+ for (i = rd->savfltregcnt - 1; i >= rd->maxsavfltreguse; i--) {
+ p--; i386_fld_reg(cd, rd->savfltregs[i]); i386_fstpl_membase(cd, REG_SP, p * 8);
}
/* save monitorenter argument */
#if defined(USE_THREADS)
- s4 func_enter = (m->flags & ACC_STATIC) ?
- (s4) builtin_staticmonitorenter : (s4) builtin_monitorenter;
-
if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
+ s4 func_enter = (m->flags & ACC_STATIC) ?
+ (s4) builtin_staticmonitorenter : (s4) builtin_monitorenter;
+
if (m->flags & ACC_STATIC) {
i386_mov_imm_reg(cd, (s4) m->class, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, r->maxmemuse * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, rd->maxmemuse * 8);
} else {
i386_mov_membase_reg(cd, REG_SP, parentargs_base * 8 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, r->maxmemuse * 8);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, rd->maxmemuse * 8);
}
/* call monitorenter function */
for (p = 0, l = 0; p < m->paramcount; p++) {
t = m->paramtypes[p];
- var = &(r->locals[l][t]);
+ var = &(rd->locals[l][t]);
l++;
if (IS_2_WORD_TYPE(t)) /* increment local counter for 2 word types */
l++;
if (var->type < 0)
continue;
if (IS_INT_LNG_TYPE(t)) { /* integer args */
- if (p < r->intreg_argnum) { /* register arguments */
+ if (p < rd->intreg_argnum) { /* register arguments */
panic("integer register argument");
if (!(var->flags & INMEMORY)) { /* reg arg -> register */
/* M_INTMOVE (argintregs[p], r); */
/* M_LST (argintregs[p], REG_SP, 8 * r); */
}
} else { /* stack arguments */
- pa = p - r->intreg_argnum;
+ pa = p - rd->intreg_argnum;
if (!(var->flags & INMEMORY)) { /* stack arg -> register */
i386_mov_membase_reg(cd, REG_SP, (parentargs_base + pa) * 8 + 4, var->regoff); /* + 4 for return address */
} else { /* stack arg -> spilled */
}
} else { /* floating args */
- if (p < r->fltreg_argnum) { /* register arguments */
+ if (p < rd->fltreg_argnum) { /* register arguments */
if (!(var->flags & INMEMORY)) { /* reg arg -> register */
panic("There are no float argument registers!");
}
} else { /* stack arguments */
- pa = p - r->fltreg_argnum;
+ pa = p - rd->fltreg_argnum;
if (!(var->flags & INMEMORY)) { /* stack-arg -> register */
if (t == TYPE_FLT) {
i386_flds_membase(cd, REG_SP, (parentargs_base + pa) * 8 + 4);
src = bptr->instack;
len = bptr->indepth;
MCODECHECK(64+len);
+
+#ifdef LSRA
+ if (opt_lsra) {
while (src != NULL) {
len--;
if ((len == 0) && (bptr->type != BBTYPE_STD)) {
if (!IS_2_WORD_TYPE(src->type)) {
if (bptr->type == BBTYPE_SBR) {
- d = reg_of_var(m, src, REG_ITMP1);
+ /* d = reg_of_var(m, src, REG_ITMP1); */
+ if (!(src->flags & INMEMORY))
+ d= src->regoff;
+ else
+ d=REG_ITMP1;
i386_pop_reg(cd, d);
store_reg_to_var_int(src, d);
+ } else if (bptr->type == BBTYPE_EXH) {
+ /* d = reg_of_var(m, src, REG_ITMP1); */
+ if (!(src->flags & INMEMORY))
+ d= src->regoff;
+ else
+ d=REG_ITMP1;
+ M_INTMOVE(REG_ITMP1, d);
+ store_reg_to_var_int(src, d);
+ }
+ } else {
+ panic("copy interface registers(EXH, SBR): longs have to me in memory (begin 1)");
+ }
+ }
+ src = src->prev;
+ }
+ } else {
+#endif
+ while (src != NULL) {
+ len--;
+ if ((len == 0) && (bptr->type != BBTYPE_STD)) {
+ if (!IS_2_WORD_TYPE(src->type)) {
+ if (bptr->type == BBTYPE_SBR) {
+ d = reg_of_var(rd, src, REG_ITMP1);
+ i386_pop_reg(cd, d);
+ store_reg_to_var_int(src, d);
} else if (bptr->type == BBTYPE_EXH) {
- d = reg_of_var(m, src, REG_ITMP1);
+ d = reg_of_var(rd, src, REG_ITMP1);
M_INTMOVE(REG_ITMP1, d);
store_reg_to_var_int(src, d);
}
}
} else {
- d = reg_of_var(m, src, REG_ITMP1);
+ d = reg_of_var(rd, src, REG_ITMP1);
if ((src->varkind != STACKVAR)) {
s2 = src->type;
if (IS_FLT_DBL_TYPE(s2)) {
- s1 = r->interfaces[len][s2].regoff;
- if (!(r->interfaces[len][s2].flags & INMEMORY)) {
+ s1 = rd->interfaces[len][s2].regoff;
+ if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
M_FLTMOVE(s1, d);
} else {
store_reg_to_var_flt(src, d);
} else {
- s1 = r->interfaces[len][s2].regoff;
- if (!IS_2_WORD_TYPE(r->interfaces[len][s2].type)) {
- if (!(r->interfaces[len][s2].flags & INMEMORY)) {
+ s1 = rd->interfaces[len][s2].regoff;
+ if (!IS_2_WORD_TYPE(rd->interfaces[len][s2].type)) {
+ if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
M_INTMOVE(s1, d);
} else {
store_reg_to_var_int(src, d);
} else {
- if (r->interfaces[len][s2].flags & INMEMORY) {
+ if (rd->interfaces[len][s2].flags & INMEMORY) {
M_LNGMEMMOVE(s1, src->regoff);
} else {
}
src = src->prev;
}
+#ifdef LSRA
+ }
+#endif
/* walk through all instructions */
currentline = 0;
for (iptr = bptr->iinstr; len > 0; src = iptr->dst, len--, iptr++) {
if (iptr->line != currentline) {
- dseg_addlinenumber(m, iptr->line, cd->mcodeptr);
+ dseg_addlinenumber(cd, iptr->line, cd->mcodeptr);
currentline = iptr->line;
}
i386_test_reg_reg(cd, src->regoff, src->regoff);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addxnullrefs(m, cd->mcodeptr);
+ codegen_addxnullrefs(cd, cd->mcodeptr);
break;
/* constant operations ************************************************/
case ICMD_ICONST: /* ... ==> ..., constant */
/* op1 = 0, val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->dst->flags & INMEMORY) {
i386_mov_imm_membase(cd, iptr->val.i, REG_SP, iptr->dst->regoff * 8);
case ICMD_LCONST: /* ... ==> ..., constant */
/* op1 = 0, val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->dst->flags & INMEMORY) {
i386_mov_imm_membase(cd, iptr->val.l, REG_SP, iptr->dst->regoff * 8);
i386_mov_imm_membase(cd, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 8 + 4);
case ICMD_FCONST: /* ... ==> ..., constant */
/* op1 = 0, val.f = constant */
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (iptr->val.f == 0.0) {
i386_fldz(cd);
fpu_st_offset++;
fpu_st_offset++;
} else {
- a = dseg_addfloat(m, iptr->val.f);
+ a = dseg_addfloat(cd, iptr->val.f);
i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(m, cd->mcodeptr);
+ dseg_adddata(cd, cd->mcodeptr);
i386_flds_membase(cd, REG_ITMP1, a);
fpu_st_offset++;
}
case ICMD_DCONST: /* ... ==> ..., constant */
/* op1 = 0, val.d = constant */
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (iptr->val.d == 0.0) {
i386_fldz(cd);
fpu_st_offset++;
fpu_st_offset++;
} else {
- a = dseg_adddouble(m, iptr->val.d);
+ a = dseg_adddouble(cd, iptr->val.d);
i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(m, cd->mcodeptr);
+ dseg_adddata(cd, cd->mcodeptr);
i386_fldl_membase(cd, REG_ITMP1, a);
fpu_st_offset++;
}
case ICMD_ACONST: /* ... ==> ..., constant */
/* op1 = 0, val.a = constant */
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->dst->flags & INMEMORY) {
i386_mov_imm_membase(cd, (s4) iptr->val.a, REG_SP, iptr->dst->regoff * 8);
case ICMD_ILOAD: /* ... ==> ..., content of local variable */
case ICMD_ALOAD: /* op1 = local variable */
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if ((iptr->dst->varkind == LOCALVAR) &&
(iptr->dst->varnum == iptr->op1)) {
break;
}
- var = &(r->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
+ var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
if (iptr->dst->flags & INMEMORY) {
if (var->flags & INMEMORY) {
i386_mov_membase_reg(cd, REG_SP, var->regoff * 8, REG_ITMP1);
case ICMD_LLOAD: /* ... ==> ..., content of local variable */
/* op1 = local variable */
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if ((iptr->dst->varkind == LOCALVAR) &&
(iptr->dst->varnum == iptr->op1)) {
break;
}
- var = &(r->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
+ var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
if (iptr->dst->flags & INMEMORY) {
if (var->flags & INMEMORY) {
M_LNGMEMMOVE(var->regoff, iptr->dst->regoff);
case ICMD_FLOAD: /* ... ==> ..., content of local variable */
/* op1 = local variable */
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if ((iptr->dst->varkind == LOCALVAR) &&
(iptr->dst->varnum == iptr->op1)) {
break;
}
- var = &(r->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
+ var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
if (var->flags & INMEMORY) {
i386_flds_membase(cd, REG_SP, var->regoff * 8);
fpu_st_offset++;
case ICMD_DLOAD: /* ... ==> ..., content of local variable */
/* op1 = local variable */
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if ((iptr->dst->varkind == LOCALVAR) &&
(iptr->dst->varnum == iptr->op1)) {
break;
}
- var = &(r->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
+ var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
if (var->flags & INMEMORY) {
i386_fldl_membase(cd, REG_SP, var->regoff * 8);
fpu_st_offset++;
(src->varnum == iptr->op1)) {
break;
}
- var = &(r->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
+ var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
if (var->flags & INMEMORY) {
if (src->flags & INMEMORY) {
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
(src->varnum == iptr->op1)) {
break;
}
- var = &(r->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
+ var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
if (var->flags & INMEMORY) {
if (src->flags & INMEMORY) {
M_LNGMEMMOVE(src->regoff, var->regoff);
(src->varnum == iptr->op1)) {
break;
}
- var = &(r->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
+ var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
if (var->flags & INMEMORY) {
var_to_reg_flt(s1, src, REG_FTMP1);
i386_fstps_membase(cd, REG_SP, var->regoff * 8);
(src->varnum == iptr->op1)) {
break;
}
- var = &(r->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
+ var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
if (var->flags & INMEMORY) {
var_to_reg_flt(s1, src, REG_FTMP1);
i386_fstpl_membase(cd, REG_SP, var->regoff * 8);
case ICMD_INEG: /* ..., value ==> ..., - value */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
case ICMD_LNEG: /* ..., value ==> ..., - value */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
case ICMD_I2L: /* ..., value ==> ..., value */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, EAX);
case ICMD_L2I: /* ..., value ==> ..., value */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
case ICMD_INT2BYTE: /* ..., value ==> ..., value */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
case ICMD_INT2CHAR: /* ..., value ==> ..., value */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
case ICMD_INT2SHORT: /* ..., value ==> ..., value */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
case ICMD_IADD: /* ..., val1, val2 ==> ..., val1 + val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialu(cd, I386_ADD, src, iptr);
break;
case ICMD_IADDCONST: /* ..., value ==> ..., value + constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
- /* should we use a inc optimization for smaller code size? */
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialuconst(cd, I386_ADD, src, iptr);
break;
case ICMD_LADD: /* ..., val1, val2 ==> ..., val1 + val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
if (src->regoff == iptr->dst->regoff) {
case ICMD_LADDCONST: /* ..., value ==> ..., value + constant */
/* val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
case ICMD_ISUB: /* ..., val1, val2 ==> ..., val1 - val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
if (src->prev->regoff == iptr->dst->regoff) {
case ICMD_ISUBCONST: /* ..., value ==> ..., value + constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialuconst(cd, I386_SUB, src, iptr);
break;
case ICMD_LSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
if (src->prev->regoff == iptr->dst->regoff) {
case ICMD_LSUBCONST: /* ..., value ==> ..., value - constant */
/* val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
if (src->regoff == iptr->dst->regoff) {
case ICMD_IMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
case ICMD_IMULCONST: /* ..., value ==> ..., value * constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 8, REG_ITMP1);
case ICMD_LMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, EAX); /* mem -> EAX */
case ICMD_LMULCONST: /* ..., value ==> ..., value * constant */
/* val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
i386_mov_imm_reg(cd, iptr->val.l, EAX); /* imm -> EAX */
case ICMD_IDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
var_to_reg_int(s1, src, REG_ITMP2);
gen_div_check(src);
if (src->prev->flags & INMEMORY) {
case ICMD_IREM: /* ..., val1, val2 ==> ..., val1 % val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
var_to_reg_int(s1, src, REG_ITMP2);
gen_div_check(src);
if (src->prev->flags & INMEMORY) {
/* TODO: optimize for `/ 2' */
var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
M_INTMOVE(s1, d);
i386_test_reg_reg(cd, d, d);
case ICMD_LDIVPOW2: /* ..., value ==> ..., value >> constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
a = 2;
/* val.i = constant */
var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(m, iptr->dst, REG_ITMP2);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP2);
if (s1 == d) {
M_INTMOVE(s1, REG_ITMP1);
s1 = REG_ITMP1;
case ICMD_LREMPOW2: /* ..., value ==> ..., value % constant */
/* val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
if (src->flags & INMEMORY) {
/* Intel algorithm -- does not work, because constant is wrong */
case ICMD_ISHL: /* ..., val1, val2 ==> ..., val1 << val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishift(cd, I386_SHL, src, iptr);
break;
case ICMD_ISHLCONST: /* ..., value ==> ..., value << constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishiftconst(cd, I386_SHL, src, iptr);
break;
case ICMD_ISHR: /* ..., val1, val2 ==> ..., val1 >> val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishift(cd, I386_SAR, src, iptr);
break;
case ICMD_ISHRCONST: /* ..., value ==> ..., value >> constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishiftconst(cd, I386_SAR, src, iptr);
break;
case ICMD_IUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishift(cd, I386_SHR, src, iptr);
break;
case ICMD_IUSHRCONST: /* ..., value ==> ..., value >>> constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ishiftconst(cd, I386_SHR, src, iptr);
break;
case ICMD_LSHL: /* ..., val1, val2 ==> ..., val1 << val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ){
if (src->prev->flags & INMEMORY) {
/* if (src->prev->regoff == iptr->dst->regoff) { */
case ICMD_LSHLCONST: /* ..., value ==> ..., value << constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ) {
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
case ICMD_LSHR: /* ..., val1, val2 ==> ..., val1 >> val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ){
if (src->prev->flags & INMEMORY) {
/* if (src->prev->regoff == iptr->dst->regoff) { */
case ICMD_LSHRCONST: /* ..., value ==> ..., value >> constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ) {
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
case ICMD_LUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ){
if (src->prev->flags & INMEMORY) {
/* if (src->prev->regoff == iptr->dst->regoff) { */
case ICMD_LUSHRCONST: /* ..., value ==> ..., value >>> constant */
/* val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY ) {
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
case ICMD_IAND: /* ..., val1, val2 ==> ..., val1 & val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialu(cd, I386_AND, src, iptr);
break;
case ICMD_IANDCONST: /* ..., value ==> ..., value & constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialuconst(cd, I386_AND, src, iptr);
break;
case ICMD_LAND: /* ..., val1, val2 ==> ..., val1 & val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_lalu(cd, I386_AND, src, iptr);
break;
case ICMD_LANDCONST: /* ..., value ==> ..., value & constant */
/* val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_laluconst(cd, I386_AND, src, iptr);
break;
case ICMD_IOR: /* ..., val1, val2 ==> ..., val1 | val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialu(cd, I386_OR, src, iptr);
break;
case ICMD_IORCONST: /* ..., value ==> ..., value | constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialuconst(cd, I386_OR, src, iptr);
break;
case ICMD_LOR: /* ..., val1, val2 ==> ..., val1 | val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_lalu(cd, I386_OR, src, iptr);
break;
case ICMD_LORCONST: /* ..., value ==> ..., value | constant */
/* val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_laluconst(cd, I386_OR, src, iptr);
break;
case ICMD_IXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialu(cd, I386_XOR, src, iptr);
break;
case ICMD_IXORCONST: /* ..., value ==> ..., value ^ constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ialuconst(cd, I386_XOR, src, iptr);
break;
case ICMD_LXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_lalu(cd, I386_XOR, src, iptr);
break;
case ICMD_LXORCONST: /* ..., value ==> ..., value ^ constant */
/* val.l = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_laluconst(cd, I386_XOR, src, iptr);
break;
case ICMD_IINC: /* ..., value ==> ..., value + constant */
/* op1 = variable, val.i = constant */
- var = &(r->locals[iptr->op1][TYPE_INT]);
+ var = &(rd->locals[iptr->op1][TYPE_INT]);
if (var->flags & INMEMORY) {
i386_alu_imm_membase(cd, I386_ADD, iptr->val.i, REG_SP, var->regoff * 8);
} else {
+ /* `inc reg' is slower on p4's (regarding to ia32 */
+ /* optimization reference manual and benchmarks) and as fast */
+ /* on athlon's. */
i386_alu_imm_reg(cd, I386_ADD, iptr->val.i, var->regoff);
}
break;
FPU_SET_24BIT_MODE;
var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
i386_fchs(cd);
store_reg_to_var_flt(iptr->dst, d);
break;
FPU_SET_53BIT_MODE;
var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
i386_fchs(cd);
store_reg_to_var_flt(iptr->dst, d);
break;
case ICMD_FADD: /* ..., val1, val2 ==> ..., val1 + val2 */
FPU_SET_24BIT_MODE;
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
var_to_reg_flt(s2, src, REG_FTMP2);
i386_faddp(cd);
case ICMD_DADD: /* ..., val1, val2 ==> ..., val1 + val2 */
FPU_SET_53BIT_MODE;
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
var_to_reg_flt(s2, src, REG_FTMP2);
i386_faddp(cd);
case ICMD_FSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
FPU_SET_24BIT_MODE;
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
var_to_reg_flt(s2, src, REG_FTMP2);
i386_fsubp(cd);
case ICMD_DSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
FPU_SET_53BIT_MODE;
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
var_to_reg_flt(s2, src, REG_FTMP2);
i386_fsubp(cd);
case ICMD_FMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
FPU_SET_24BIT_MODE;
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
var_to_reg_flt(s2, src, REG_FTMP2);
i386_fmulp(cd);
case ICMD_DMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
FPU_SET_53BIT_MODE;
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
/* i386_fldt_mem(cd, subnormal_bias1); */
case ICMD_FDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
FPU_SET_24BIT_MODE;
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
var_to_reg_flt(s2, src, REG_FTMP2);
i386_fdivp(cd);
case ICMD_DDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
FPU_SET_53BIT_MODE;
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
/* i386_fldt_mem(cd, subnormal_bias1); */
/* exchanged to skip fxch */
var_to_reg_flt(s2, src, REG_FTMP2);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
/* i386_fxch(cd); */
i386_fprem(cd);
i386_wait(cd);
/* exchanged to skip fxch */
var_to_reg_flt(s2, src, REG_FTMP2);
var_to_reg_flt(s1, src->prev, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
/* i386_fxch(cd); */
i386_fprem(cd);
i386_wait(cd);
case ICMD_I2F: /* ..., value ==> ..., (float) value */
case ICMD_I2D: /* ..., value ==> ..., (double) value */
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (src->flags & INMEMORY) {
i386_fildl_membase(cd, REG_SP, src->regoff * 8);
fpu_st_offset++;
} else {
- a = dseg_adds4(m, 0);
+ a = dseg_adds4(cd, 0);
i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(m, cd->mcodeptr);
+ dseg_adddata(cd, cd->mcodeptr);
i386_mov_reg_membase(cd, src->regoff, REG_ITMP1, a);
i386_fildl_membase(cd, REG_ITMP1, a);
fpu_st_offset++;
case ICMD_L2F: /* ..., value ==> ..., (float) value */
case ICMD_L2D: /* ..., value ==> ..., (double) value */
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (src->flags & INMEMORY) {
i386_fildll_membase(cd, REG_SP, src->regoff * 8);
fpu_st_offset++;
case ICMD_F2I: /* ..., value ==> ..., (int) value */
var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
- a = dseg_adds4(m, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
+ a = dseg_adds4(cd, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(m, cd->mcodeptr);
+ dseg_adddata(cd, cd->mcodeptr);
i386_fldcw_membase(cd, REG_ITMP1, a);
if (iptr->dst->flags & INMEMORY) {
i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 8);
fpu_st_offset--;
- a = dseg_adds4(m, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
+ a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
i386_fldcw_membase(cd, REG_ITMP1, a);
i386_alu_imm_membase(cd, I386_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 8);
CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
} else {
- a = dseg_adds4(m, 0);
+ a = dseg_adds4(cd, 0);
i386_fistpl_membase(cd, REG_ITMP1, a);
fpu_st_offset--;
i386_mov_membase_reg(cd, REG_ITMP1, a, iptr->dst->regoff);
- a = dseg_adds4(m, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
+ a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
i386_fldcw_membase(cd, REG_ITMP1, a);
i386_alu_imm_reg(cd, I386_CMP, 0x80000000, iptr->dst->regoff);
case ICMD_D2I: /* ..., value ==> ..., (int) value */
var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
- a = dseg_adds4(m, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
+ a = dseg_adds4(cd, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(m, cd->mcodeptr);
+ dseg_adddata(cd, cd->mcodeptr);
i386_fldcw_membase(cd, REG_ITMP1, a);
if (iptr->dst->flags & INMEMORY) {
i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 8);
fpu_st_offset--;
- a = dseg_adds4(m, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
+ a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
i386_fldcw_membase(cd, REG_ITMP1, a);
i386_alu_imm_membase(cd, I386_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 8);
CALCOFFSETBYTES(a, REG_SP, iptr->dst->regoff * 8);
} else {
- a = dseg_adds4(m, 0);
+ a = dseg_adds4(cd, 0);
i386_fistpl_membase(cd, REG_ITMP1, a);
fpu_st_offset--;
i386_mov_membase_reg(cd, REG_ITMP1, a, iptr->dst->regoff);
- a = dseg_adds4(m, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
+ a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
i386_fldcw_membase(cd, REG_ITMP1, a);
i386_alu_imm_reg(cd, I386_CMP, 0x80000000, iptr->dst->regoff);
case ICMD_F2L: /* ..., value ==> ..., (long) value */
var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
- a = dseg_adds4(m, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
+ a = dseg_adds4(cd, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(m, cd->mcodeptr);
+ dseg_adddata(cd, cd->mcodeptr);
i386_fldcw_membase(cd, REG_ITMP1, a);
if (iptr->dst->flags & INMEMORY) {
i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 8);
fpu_st_offset--;
- a = dseg_adds4(m, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
+ a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
i386_fldcw_membase(cd, REG_ITMP1, a);
i386_alu_imm_membase(cd, I386_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 8 + 4);
case ICMD_D2L: /* ..., value ==> ..., (long) value */
var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
- a = dseg_adds4(m, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
+ a = dseg_adds4(cd, 0x0e7f); /* Round to zero, 53-bit mode, exception masked */
i386_mov_imm_reg(cd, 0, REG_ITMP1);
- dseg_adddata(m, cd->mcodeptr);
+ dseg_adddata(cd, cd->mcodeptr);
i386_fldcw_membase(cd, REG_ITMP1, a);
if (iptr->dst->flags & INMEMORY) {
i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 8);
fpu_st_offset--;
- a = dseg_adds4(m, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
+ a = dseg_adds4(cd, 0x027f); /* Round to nearest, 53-bit mode, exceptions masked */
i386_fldcw_membase(cd, REG_ITMP1, a);
i386_alu_imm_membase(cd, I386_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 8 + 4);
case ICMD_F2D: /* ..., value ==> ..., (double) value */
var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
/* nothing to do */
store_reg_to_var_flt(iptr->dst, d);
break;
case ICMD_D2F: /* ..., value ==> ..., (float) value */
var_to_reg_flt(s1, src, REG_FTMP1);
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
/* nothing to do */
store_reg_to_var_flt(iptr->dst, d);
break;
/* exchanged to skip fxch */
var_to_reg_flt(s2, src->prev, REG_FTMP1);
var_to_reg_flt(s1, src, REG_FTMP2);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
/* i386_fxch(cd); */
i386_fucompp(cd);
fpu_st_offset -= 2;
/* exchanged to skip fxch */
var_to_reg_flt(s2, src->prev, REG_FTMP1);
var_to_reg_flt(s1, src, REG_FTMP2);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
/* i386_fxch(cd); */
i386_fucompp(cd);
fpu_st_offset -= 2;
case ICMD_ARRAYLENGTH: /* ..., arrayref ==> ..., length */
var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
gen_nullptr_check(s1);
i386_mov_membase_reg(cd, s1, OFFSET(java_arrayheader, size), d);
store_reg_to_var_int(iptr->dst, d);
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->op1 == 0) {
gen_nullptr_check(s1);
gen_bound_check;
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(m, iptr->dst, REG_ITMP3);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP3);
if (iptr->op1 == 0) {
gen_nullptr_check(s1);
gen_bound_check;
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->op1 == 0) {
gen_nullptr_check(s1);
gen_bound_check;
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
if (iptr->op1 == 0) {
gen_nullptr_check(s1);
gen_bound_check;
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(m, iptr->dst, REG_FTMP3);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP3);
if (iptr->op1 == 0) {
gen_nullptr_check(s1);
gen_bound_check;
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->op1 == 0) {
gen_nullptr_check(s1);
gen_bound_check;
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->op1 == 0) {
gen_nullptr_check(s1);
gen_bound_check;
var_to_reg_int(s1, src->prev, REG_ITMP1);
var_to_reg_int(s2, src, REG_ITMP2);
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
if (iptr->op1 == 0) {
gen_nullptr_check(s1);
gen_bound_check;
case ICMD_PUTSTATIC: /* ..., value ==> ... */
/* op1 = type, val.a = field address */
- /* if class isn't yet initialized, do it */
+ /* If the static fields' class is not yet initialized, we do it */
+ /* now. The call code is generated later. */
if (!((fieldinfo *) iptr->val.a)->class->initialized) {
- /* call helper function which patches this code */
- i386_mov_imm_reg(cd, (s4) ((fieldinfo *) iptr->val.a)->class, REG_ITMP1);
- i386_mov_imm_reg(cd, (s4) asm_check_clinit, REG_ITMP2);
- i386_call_reg(cd, REG_ITMP2);
+ codegen_addclinitref(cd, cd->mcodeptr, ((fieldinfo *) iptr->val.a)->class);
+
+ /* This is just for debugging purposes. Is very difficult to */
+ /* read patched code. Here we patch the following 5 nop's */
+ /* so that the real code keeps untouched. */
+ if (showdisassemble) {
+ i386_nop(cd);
+ i386_nop(cd);
+ i386_nop(cd);
+ i386_nop(cd);
+ i386_nop(cd);
+ }
}
- a = dseg_addaddress(m, &(((fieldinfo *) iptr->val.a)->value));
- /* here it's slightly slower */
- i386_mov_imm_reg(cd, 0, REG_ITMP2);
- dseg_adddata(m, cd->mcodeptr);
- i386_mov_membase_reg(cd, REG_ITMP2, a, REG_ITMP2);
+ a = (u4) &(((fieldinfo *) iptr->val.a)->value);
switch (iptr->op1) {
case TYPE_INT:
case TYPE_ADR:
var_to_reg_int(s2, src, REG_ITMP1);
- i386_mov_reg_membase(cd, s2, REG_ITMP2, 0);
+ i386_mov_reg_mem(cd, s2, a);
break;
case TYPE_LNG:
if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_ITMP2, 0);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_ITMP2, 0 + 4);
+ /* Using both REG_ITMP1 and REG_ITMP2 is faster than only */
+ /* using REG_ITMP1 alternating. */
+ s2 = src->regoff;
+ i386_mov_membase_reg(cd, REG_SP, s2 * 8, REG_ITMP1);
+ i386_mov_membase_reg(cd, REG_SP, s2 * 8 + 4, REG_ITMP2);
+ i386_mov_reg_mem(cd, REG_ITMP1, a);
+ i386_mov_reg_mem(cd, REG_ITMP2, a + 4);
} else {
panic("PUTSTATIC: longs have to be in memory");
}
break;
case TYPE_FLT:
var_to_reg_flt(s2, src, REG_FTMP1);
- i386_fstps_membase(cd, REG_ITMP2, 0);
+ i386_fstps_mem(cd, a);
fpu_st_offset--;
break;
case TYPE_DBL:
var_to_reg_flt(s2, src, REG_FTMP1);
- i386_fstpl_membase(cd, REG_ITMP2, 0);
+ i386_fstpl_mem(cd, a);
fpu_st_offset--;
break;
- default: panic ("internal error");
+ default:
+ throw_cacao_exception_exit(string_java_lang_InternalError,
+ "Unknown PUTSTATIC operand type %d",
+ iptr->op1);
}
break;
case ICMD_GETSTATIC: /* ... ==> ..., value */
/* op1 = type, val.a = field address */
- /* if class isn't yet initialized, do it */
+ /* If the static fields' class is not yet initialized, we do it */
+ /* now. The call code is generated later. */
if (!((fieldinfo *) iptr->val.a)->class->initialized) {
- /* call helper function which patches this code */
- i386_mov_imm_reg(cd, (s4) ((fieldinfo *) iptr->val.a)->class, REG_ITMP1);
- i386_mov_imm_reg(cd, (s4) asm_check_clinit, REG_ITMP2);
- i386_call_reg(cd, REG_ITMP2);
- }
+ codegen_addclinitref(cd, cd->mcodeptr, ((fieldinfo *) iptr->val.a)->class);
+
+ /* This is just for debugging purposes. Is very difficult to */
+ /* read patched code. Here we patch the following 5 nop's */
+ /* so that the real code keeps untouched. */
+ if (showdisassemble) {
+ i386_nop(cd);
+ i386_nop(cd);
+ i386_nop(cd);
+ i386_nop(cd);
+ i386_nop(cd);
+ }
+ }
- a = dseg_addaddress(m, &(((fieldinfo *) iptr->val.a)->value));
- i386_mov_imm_reg(cd, 0, REG_ITMP2);
- dseg_adddata(m, cd->mcodeptr);
- i386_mov_membase_reg(cd, REG_ITMP2, a, REG_ITMP2);
+ a = (u4) &(((fieldinfo *) iptr->val.a)->value);
switch (iptr->op1) {
case TYPE_INT:
case TYPE_ADR:
- d = reg_of_var(m, iptr->dst, REG_ITMP1);
- i386_mov_membase_reg(cd, REG_ITMP2, 0, d);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP1);
+ i386_mov_mem_reg(cd, a, d);
store_reg_to_var_int(iptr->dst, d);
break;
case TYPE_LNG:
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (iptr->dst->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_ITMP2, 0, REG_ITMP1);
+ /* Using both REG_ITMP1 and REG_ITMP2 is faster than only */
+ /* using REG_ITMP1 alternating. */
+ i386_mov_mem_reg(cd, a, REG_ITMP1);
+ i386_mov_mem_reg(cd, a + 4, REG_ITMP2);
i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, REG_ITMP2, 0 + 4, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8 + 4);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
} else {
panic("GETSTATIC: longs have to be in memory");
}
break;
case TYPE_FLT:
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
- i386_flds_membase(cd, REG_ITMP2, 0);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
+ i386_flds_mem(cd, a);
fpu_st_offset++;
store_reg_to_var_flt(iptr->dst, d);
break;
case TYPE_DBL:
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
- i386_fldl_membase(cd, REG_ITMP2, 0);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
+ i386_fldl_mem(cd, a);
fpu_st_offset++;
store_reg_to_var_flt(iptr->dst, d);
break;
- default: panic ("internal error");
+ default:
+ throw_cacao_exception_exit(string_java_lang_InternalError,
+ "Unknown GETSTATIC operand type %d",
+ iptr->op1);
}
break;
case ICMD_PUTFIELD: /* ..., value ==> ... */
/* op1 = type, val.i = field offset */
- a = ((fieldinfo *)(iptr->val.a))->offset;
+ a = ((fieldinfo *) (iptr->val.a))->offset;
switch (iptr->op1) {
- case TYPE_INT:
- case TYPE_ADR:
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_int(s2, src, REG_ITMP2);
- gen_nullptr_check(s1);
- i386_mov_reg_membase(cd, s2, s1, a);
- break;
- case TYPE_LNG:
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- gen_nullptr_check(s1);
- if (src->flags & INMEMORY) {
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, s1, a);
- i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, s1, a + 4);
- } else {
- panic("PUTFIELD: longs have to be in memory");
- }
- break;
- case TYPE_FLT:
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_flt(s2, src, REG_FTMP1);
- gen_nullptr_check(s1);
- i386_fstps_membase(cd, s1, a);
- fpu_st_offset--;
- break;
- case TYPE_DBL:
- var_to_reg_int(s1, src->prev, REG_ITMP1);
- var_to_reg_flt(s2, src, REG_FTMP1);
- gen_nullptr_check(s1);
- i386_fstpl_membase(cd, s1, a);
- fpu_st_offset--;
- break;
- default: panic ("internal error");
+ case TYPE_INT:
+ case TYPE_ADR:
+ var_to_reg_int(s1, src->prev, REG_ITMP1);
+ var_to_reg_int(s2, src, REG_ITMP2);
+ gen_nullptr_check(s1);
+ i386_mov_reg_membase(cd, s2, s1, a);
+ break;
+ case TYPE_LNG:
+ var_to_reg_int(s1, src->prev, REG_ITMP1);
+ gen_nullptr_check(s1);
+ if (src->flags & INMEMORY) {
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP2);
+ i386_mov_reg_membase(cd, REG_ITMP2, s1, a);
+ i386_mov_membase_reg(cd, REG_SP, src->regoff * 8 + 4, REG_ITMP2);
+ i386_mov_reg_membase(cd, REG_ITMP2, s1, a + 4);
+ } else {
+ panic("PUTFIELD: longs have to be in memory");
}
+ break;
+ case TYPE_FLT:
+ var_to_reg_int(s1, src->prev, REG_ITMP1);
+ var_to_reg_flt(s2, src, REG_FTMP1);
+ gen_nullptr_check(s1);
+ i386_fstps_membase(cd, s1, a);
+ fpu_st_offset--;
+ break;
+ case TYPE_DBL:
+ var_to_reg_int(s1, src->prev, REG_ITMP1);
+ var_to_reg_flt(s2, src, REG_FTMP1);
+ gen_nullptr_check(s1);
+ i386_fstpl_membase(cd, s1, a);
+ fpu_st_offset--;
+ break;
+ default:
+ throw_cacao_exception_exit(string_java_lang_InternalError,
+ "Unknown PUTFIELD operand type %d",
+ iptr->op1);
+ }
break;
case ICMD_GETFIELD: /* ... ==> ..., value */
/* op1 = type, val.i = field offset */
- a = ((fieldinfo *)(iptr->val.a))->offset;
+ a = ((fieldinfo *) (iptr->val.a))->offset;
switch (iptr->op1) {
- case TYPE_INT:
- case TYPE_ADR:
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(m, iptr->dst, REG_ITMP2);
- gen_nullptr_check(s1);
- i386_mov_membase_reg(cd, s1, a, d);
- store_reg_to_var_int(iptr->dst, d);
- break;
- case TYPE_LNG:
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(m, iptr->dst, REG_NULL);
- gen_nullptr_check(s1);
- i386_mov_membase_reg(cd, s1, a, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8);
- i386_mov_membase_reg(cd, s1, a + 4, REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
- break;
- case TYPE_FLT:
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
- gen_nullptr_check(s1);
- i386_flds_membase(cd, s1, a);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
- break;
- case TYPE_DBL:
- var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(m, iptr->dst, REG_FTMP1);
- gen_nullptr_check(s1);
- i386_fldl_membase(cd, s1, a);
- fpu_st_offset++;
- store_reg_to_var_flt(iptr->dst, d);
- break;
- default: panic ("internal error");
- }
+ case TYPE_INT:
+ case TYPE_ADR:
+ var_to_reg_int(s1, src, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP2);
+ gen_nullptr_check(s1);
+ i386_mov_membase_reg(cd, s1, a, d);
+ store_reg_to_var_int(iptr->dst, d);
+ break;
+ case TYPE_LNG:
+ var_to_reg_int(s1, src, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
+ gen_nullptr_check(s1);
+ i386_mov_membase_reg(cd, s1, a, REG_ITMP2);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8);
+ i386_mov_membase_reg(cd, s1, a + 4, REG_ITMP2);
+ i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 8 + 4);
+ break;
+ case TYPE_FLT:
+ var_to_reg_int(s1, src, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
+ gen_nullptr_check(s1);
+ i386_flds_membase(cd, s1, a);
+ fpu_st_offset++;
+ store_reg_to_var_flt(iptr->dst, d);
+ break;
+ case TYPE_DBL:
+ var_to_reg_int(s1, src, REG_ITMP1);
+ d = reg_of_var(rd, iptr->dst, REG_FTMP1);
+ gen_nullptr_check(s1);
+ i386_fldl_membase(cd, s1, a);
+ fpu_st_offset++;
+ store_reg_to_var_flt(iptr->dst, d);
+ break;
+ default:
+ throw_cacao_exception_exit(string_java_lang_InternalError,
+ "Unknown GETFIELD operand type %d",
+ iptr->op1);
+ }
break;
/* branch operations **************************************************/
- /* TWISTI */
-/* #define ALIGNCODENOP {if((int)((long)cd->mcodeptr&7)){M_NOP;}} */
-#define ALIGNCODENOP do {} while (0)
-
case ICMD_ATHROW: /* ..., objectref ==> ... (, objectref) */
var_to_reg_int(s1, src, REG_ITMP1);
M_INTMOVE(s1, REG_ITMP1_XPTR);
- i386_call_imm(cd, 0); /* passing exception pointer */
+ i386_call_imm(cd, 0); /* passing exception pointer */
i386_pop_reg(cd, REG_ITMP2_XPC);
i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
/* op1 = target JavaVM pc */
i386_jmp_imm(cd, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
ALIGNCODENOP;
break;
/* op1 = target JavaVM pc */
i386_call_imm(cd, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_RET: /* ... ==> ... */
/* op1 = local variable */
- var = &(r->locals[iptr->op1][TYPE_ADR]);
+ var = &(rd->locals[iptr->op1][TYPE_ADR]);
var_to_reg_int(s1, var, REG_ITMP1);
i386_jmp_reg(cd, s1);
break;
i386_test_reg_reg(cd, src->regoff, src->regoff);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IFNONNULL: /* ..., value ==> ... */
i386_test_reg_reg(cd, src->regoff, src->regoff);
}
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IFEQ: /* ..., value ==> ... */
i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IFLT: /* ..., value ==> ... */
i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IFLE: /* ..., value ==> ... */
i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_LE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IFNE: /* ..., value ==> ... */
i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IFGT: /* ..., value ==> ... */
i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IFGE: /* ..., value ==> ... */
i386_alu_imm_reg(cd, I386_CMP, iptr->val.i, src->regoff);
}
i386_jcc(cd, I386_CC_GE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LEQ: /* ..., value ==> ... */
}
i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LLT: /* ..., value ==> ... */
if (src->flags & INMEMORY) {
i386_alu_imm_membase(cd, I386_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 8 + 4);
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
a = 3 + 6;
CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
i386_alu_imm_membase(cd, I386_CMP, iptr->val.l, REG_SP, src->regoff * 8);
i386_jcc(cd, I386_CC_B, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
}
break;
if (src->flags & INMEMORY) {
i386_alu_imm_membase(cd, I386_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 8 + 4);
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
a = 3 + 6;
CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
i386_alu_imm_membase(cd, I386_CMP, iptr->val.l, REG_SP, src->regoff * 8);
i386_jcc(cd, I386_CC_BE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
}
break;
}
i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LGT: /* ..., value ==> ... */
if (src->flags & INMEMORY) {
i386_alu_imm_membase(cd, I386_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 8 + 4);
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
a = 3 + 6;
CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
i386_alu_imm_membase(cd, I386_CMP, iptr->val.l, REG_SP, src->regoff * 8);
i386_jcc(cd, I386_CC_A, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
}
break;
if (src->flags & INMEMORY) {
i386_alu_imm_membase(cd, I386_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 8 + 4);
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
a = 3 + 6;
CALCOFFSETBYTES(a, REG_SP, src->regoff * 8);
i386_alu_imm_membase(cd, I386_CMP, iptr->val.l, REG_SP, src->regoff * 8);
i386_jcc(cd, I386_CC_AE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
}
break;
i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LCMPEQ: /* ..., value, value ==> ... */
i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
}
i386_jcc(cd, I386_CC_E, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_ICMPNE: /* ..., value, value ==> ... */
i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LCMPNE: /* ..., value, value ==> ... */
i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1);
}
i386_jcc(cd, I386_CC_NE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_ICMPLT: /* ..., value, value ==> ... */
i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LCMPLT: /* ..., value, value ==> ... */
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
a = 3 + 3 + 6;
CALCOFFSETBYTES(a, REG_SP, src->prev->regoff * 8);
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, REG_ITMP1);
i386_jcc(cd, I386_CC_B, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
}
break;
i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LCMPGT: /* ..., value, value ==> ... */
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
a = 3 + 3 + 6;
CALCOFFSETBYTES(a, REG_SP, src->prev->regoff * 8);
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, REG_ITMP1);
i386_jcc(cd, I386_CC_A, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
}
break;
i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_LE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LCMPLE: /* ..., value, value ==> ... */
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
i386_jcc(cd, I386_CC_L, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
a = 3 + 3 + 6;
CALCOFFSETBYTES(a, REG_SP, src->prev->regoff * 8);
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, REG_ITMP1);
i386_jcc(cd, I386_CC_BE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
}
break;
i386_alu_reg_reg(cd, I386_CMP, src->regoff, src->prev->regoff);
}
i386_jcc(cd, I386_CC_GE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
break;
case ICMD_IF_LCMPGE: /* ..., value, value ==> ... */
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8 + 4, REG_ITMP1);
i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8 + 4, REG_ITMP1);
i386_jcc(cd, I386_CC_G, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
a = 3 + 3 + 6;
CALCOFFSETBYTES(a, REG_SP, src->prev->regoff * 8);
i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
i386_alu_membase_reg(cd, I386_CMP, REG_SP, src->regoff * 8, REG_ITMP1);
i386_jcc(cd, I386_CC_AE, 0);
- codegen_addreference(m, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
+ codegen_addreference(cd, BlockPtrOfPC(iptr->op1), cd->mcodeptr);
}
break;
case ICMD_IFEQ_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_NE, src, iptr);
break;
case ICMD_IFNE_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_E, src, iptr);
break;
case ICMD_IFLT_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_GE, src, iptr);
break;
case ICMD_IFGE_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_L, src, iptr);
break;
case ICMD_IFGT_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_LE, src, iptr);
break;
case ICMD_IFLE_ICONST: /* ..., value ==> ..., constant */
/* val.i = constant */
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
i386_emit_ifcc_iconst(cd, I386_CC_G, src, iptr);
break;
#if defined(USE_THREADS)
if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
- i386_mov_membase_reg(cd, REG_SP, 8 * r->maxmemuse, REG_ITMP2);
+ i386_mov_membase_reg(cd, REG_SP, 8 * rd->maxmemuse, REG_ITMP2);
/* we need to save the proper return value */
switch (iptr->opc) {
case ICMD_IRETURN:
case ICMD_ARETURN:
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, r->maxmemuse * 8);
+ i386_mov_reg_membase(cd, REG_RESULT, REG_SP, rd->maxmemuse * 8);
break;
case ICMD_LRETURN:
- i386_mov_reg_membase(cd, REG_RESULT, REG_SP, r->maxmemuse * 8);
- i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, r->maxmemuse * 8 + 4);
+ i386_mov_reg_membase(cd, REG_RESULT, REG_SP, rd->maxmemuse * 8);
+ i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, rd->maxmemuse * 8 + 4);
break;
case ICMD_FRETURN:
- i386_fsts_membase(cd, REG_SP, r->maxmemuse * 8);
+ i386_fsts_membase(cd, REG_SP, rd->maxmemuse * 8);
break;
case ICMD_DRETURN:
- i386_fstl_membase(cd, REG_SP, r->maxmemuse * 8);
+ i386_fstl_membase(cd, REG_SP, rd->maxmemuse * 8);
break;
}
switch (iptr->opc) {
case ICMD_IRETURN:
case ICMD_ARETURN:
- i386_mov_membase_reg(cd, REG_SP, r->maxmemuse * 8, REG_RESULT);
+ i386_mov_membase_reg(cd, REG_SP, rd->maxmemuse * 8, REG_RESULT);
break;
case ICMD_LRETURN:
- i386_mov_membase_reg(cd, REG_SP, r->maxmemuse * 8, REG_RESULT);
- i386_mov_membase_reg(cd, REG_SP, r->maxmemuse * 8 + 4, REG_RESULT2);
+ i386_mov_membase_reg(cd, REG_SP, rd->maxmemuse * 8, REG_RESULT);
+ i386_mov_membase_reg(cd, REG_SP, rd->maxmemuse * 8 + 4, REG_RESULT2);
break;
case ICMD_FRETURN:
- i386_flds_membase(cd, REG_SP, r->maxmemuse * 8);
+ i386_flds_membase(cd, REG_SP, rd->maxmemuse * 8);
break;
case ICMD_DRETURN:
- i386_fldl_membase(cd, REG_SP, r->maxmemuse * 8);
+ i386_fldl_membase(cd, REG_SP, rd->maxmemuse * 8);
break;
}
}
#endif
/* restore saved registers */
- for (i = r->savintregcnt - 1; i >= r->maxsavintreguse; i--) {
+ for (i = rd->savintregcnt - 1; i >= rd->maxsavintreguse; i--) {
p--;
- i386_mov_membase_reg(cd, REG_SP, p * 8, r->savintregs[i]);
+ i386_mov_membase_reg(cd, REG_SP, p * 8, rd->savintregs[i]);
}
- for (i = r->savfltregcnt - 1; i >= r->maxsavfltreguse; i--) {
+ for (i = rd->savfltregcnt - 1; i >= rd->maxsavfltreguse; i--) {
p--;
i386_fldl_membase(cd, REG_SP, p * 8);
fpu_st_offset++;
if (iptr->opc == ICMD_FRETURN || iptr->opc == ICMD_DRETURN) {
- i386_fstp_reg(cd, r->savfltregs[i] + fpu_st_offset + 1);
+ i386_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset + 1);
} else {
- i386_fstp_reg(cd, r->savfltregs[i] + fpu_st_offset);
+ i386_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset);
}
fpu_st_offset--;
}
i386_alu_imm_reg(cd, I386_CMP, i - 1, REG_ITMP1);
i386_jcc(cd, I386_CC_A, 0);
- /* codegen_addreference(m, BlockPtrOfPC(s4ptr[0]), cd->mcodeptr); */
- codegen_addreference(m, (basicblock *) tptr[0], cd->mcodeptr);
+ /* codegen_addreference(cd, BlockPtrOfPC(s4ptr[0]), cd->mcodeptr); */
+ codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
/* build jump table top down and use address of lowest entry */
tptr += i;
while (--i >= 0) {
- /* dseg_addtarget(m, BlockPtrOfPC(*--s4ptr)); */
- dseg_addtarget(m, (basicblock *) tptr[0]);
+ /* dseg_addtarget(cd, BlockPtrOfPC(*--s4ptr)); */
+ dseg_addtarget(cd, (basicblock *) tptr[0]);
--tptr;
}
/* length of dataseg after last dseg_addtarget is used by load */
i386_mov_imm_reg(cd, 0, REG_ITMP2);
- dseg_adddata(m, cd->mcodeptr);
+ dseg_adddata(cd, cd->mcodeptr);
i386_mov_memindex_reg(cd, -(cd->dseglen), REG_ITMP2, REG_ITMP1, 2, REG_ITMP1);
i386_jmp_reg(cd, REG_ITMP1);
ALIGNCODENOP;
val = s4ptr[0];
i386_alu_imm_reg(cd, I386_CMP, val, s1);
i386_jcc(cd, I386_CC_E, 0);
- /* codegen_addreference(m, BlockPtrOfPC(s4ptr[1]), cd->mcodeptr); */
- codegen_addreference(m, (basicblock *) tptr[0], cd->mcodeptr);
+ /* codegen_addreference(cd, BlockPtrOfPC(s4ptr[1]), cd->mcodeptr); */
+ codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
}
i386_jmp_imm(cd, 0);
- /* codegen_addreference(m, BlockPtrOfPC(l), cd->mcodeptr); */
+ /* codegen_addreference(cd, BlockPtrOfPC(l), cd->mcodeptr); */
tptr = (void **) iptr->target;
- codegen_addreference(m, (basicblock *) tptr[0], cd->mcodeptr);
+ codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr);
ALIGNCODENOP;
}
}
if (IS_INT_LNG_TYPE(src->type)) {
- if (s3 < r->intreg_argnum) {
+ if (s3 < rd->intreg_argnum) {
panic("No integer argument registers available!");
} else {
}
} else {
- if (s3 < r->fltreg_argnum) {
+ if (s3 < rd->fltreg_argnum) {
panic("No float argument registers available!");
} else {
/* d contains return type */
if (d != TYPE_VOID) {
- d = reg_of_var(m, iptr->dst, REG_NULL);
+ d = reg_of_var(rd, iptr->dst, REG_NULL);
if (IS_INT_LNG_TYPE(iptr->dst->type)) {
if (IS_2_WORD_TYPE(iptr->dst->type)) {
classinfo *super = (classinfo*) iptr->val.a;
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritrestart(m, cd->mcodeptr - cd->mcodebase);
+ codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase);
#endif
var_to_reg_int(s1, src, REG_ITMP1);
- d = reg_of_var(m, iptr->dst, REG_ITMP3);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP3);
if (s1 == d) {
M_INTMOVE(s1, REG_ITMP1);
s1 = REG_ITMP1;
i386_mov_membase_reg(cd, s1, OFFSET(java_objectheader, vftbl), REG_ITMP1);
i386_mov_imm_reg(cd, (s4) super->vftbl, REG_ITMP2);
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritstart(m, cd->mcodeptr - cd->mcodebase);
+ codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase);
#endif
i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, baseval), REG_ITMP1);
i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, baseval), REG_ITMP3);
i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, diffval), REG_ITMP2);
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritstop(m, cd->mcodeptr - cd->mcodebase);
+ codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
#endif
i386_alu_reg_reg(cd, I386_SUB, REG_ITMP3, REG_ITMP1);
i386_alu_reg_reg(cd, I386_XOR, d, d);
classinfo *super = (classinfo*) iptr->val.a;
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritrestart(m, cd->mcodeptr - cd->mcodebase);
+ codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase);
#endif
- d = reg_of_var(m, iptr->dst, REG_ITMP3);
+ d = reg_of_var(rd, iptr->dst, REG_ITMP3);
var_to_reg_int(s1, src, d);
if (iptr->op1) { /* class/interface */
if (super->flags & ACC_INTERFACE) { /* interface */
/* TODO: test */
i386_alu_imm_reg(cd, I386_CMP, 0, REG_ITMP2);
i386_jcc(cd, I386_CC_LE, 0);
- codegen_addxcastrefs(m, cd->mcodeptr);
+ codegen_addxcastrefs(cd, cd->mcodeptr);
i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, interfacetable[0]) - super->index * sizeof(methodptr*), REG_ITMP2);
/* TODO: test */
i386_alu_imm_reg(cd, I386_CMP, 0, REG_ITMP2);
i386_jcc(cd, I386_CC_E, 0);
- codegen_addxcastrefs(m, cd->mcodeptr);
+ codegen_addxcastrefs(cd, cd->mcodeptr);
} else { /* class */
i386_test_reg_reg(cd, s1, s1);
i386_mov_membase_reg(cd, s1, OFFSET(java_objectheader, vftbl), REG_ITMP1);
i386_mov_imm_reg(cd, (s4) super->vftbl, REG_ITMP2);
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritstart(m, cd->mcodeptr - cd->mcodebase);
+ codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase);
#endif
i386_mov_membase_reg(cd, REG_ITMP1, OFFSET(vftbl_t, baseval), REG_ITMP1);
if (d != REG_ITMP3) {
i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, baseval), REG_ITMP3);
i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, diffval), REG_ITMP2);
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritstop(m, cd->mcodeptr - cd->mcodebase);
+ codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
#endif
i386_alu_reg_reg(cd, I386_SUB, REG_ITMP3, REG_ITMP1);
i386_mov_imm_reg(cd, (s4) super->vftbl, REG_ITMP2);
i386_mov_membase_reg(cd, REG_ITMP2, OFFSET(vftbl_t, diffval), REG_ITMP2);
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
- codegen_threadcritstop(m, cd->mcodeptr - cd->mcodebase);
+ codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
#endif
}
i386_alu_reg_reg(cd, I386_CMP, REG_ITMP2, REG_ITMP1);
i386_jcc(cd, I386_CC_A, 0); /* (u) REG_ITMP1 > (u) REG_ITMP2 -> jump */
- codegen_addxcastrefs(m, cd->mcodeptr);
+ codegen_addxcastrefs(cd, cd->mcodeptr);
}
} else
i386_test_reg_reg(cd, src->regoff, src->regoff);
}
i386_jcc(cd, I386_CC_L, 0);
- codegen_addxcheckarefs(m, cd->mcodeptr);
+ codegen_addxcheckarefs(cd, cd->mcodeptr);
break;
case ICMD_CHECKEXCEPTION: /* ... ==> ... */
i386_test_reg_reg(cd, REG_RESULT, REG_RESULT);
i386_jcc(cd, I386_CC_E, 0);
- codegen_addxexceptionrefs(m, cd->mcodeptr);
+ codegen_addxexceptionrefs(cd, cd->mcodeptr);
break;
case ICMD_MULTIANEWARRAY:/* ..., cnt1, [cnt2, ...] ==> ..., arrayref */
i386_test_reg_reg(cd, src->regoff, src->regoff);
}
i386_jcc(cd, I386_CC_L, 0);
- codegen_addxcheckarefs(m, cd->mcodeptr);
+ codegen_addxcheckarefs(cd, cd->mcodeptr);
/*
* copy sizes to new stack location, be cause native function
i386_call_reg(cd, REG_ITMP1);
i386_alu_imm_reg(cd, I386_ADD, 12 + iptr->op1 * 4, REG_SP);
- s1 = reg_of_var(m, iptr->dst, REG_RESULT);
+ s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
M_INTMOVE(REG_RESULT, s1);
store_reg_to_var_int(iptr->dst, s1);
break;
+ case ICMD_INLINE_START:
+ case ICMD_INLINE_END:
+ break;
default:
error ("Unknown pseudo command: %d", iptr->opc);
} /* switch */
src = bptr->outstack;
len = bptr->outdepth;
MCODECHECK(64+len);
+#ifdef LSRA
+ if (!opt_lsra)
+#endif
while (src) {
len--;
if ((src->varkind != STACKVAR)) {
s2 = src->type;
if (IS_FLT_DBL_TYPE(s2)) {
var_to_reg_flt(s1, src, REG_FTMP1);
- if (!(r->interfaces[len][s2].flags & INMEMORY)) {
- M_FLTMOVE(s1, r->interfaces[len][s2].regoff);
+ if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
+ M_FLTMOVE(s1, rd->interfaces[len][s2].regoff);
} else {
panic("double store");
} else {
var_to_reg_int(s1, src, REG_ITMP1);
- if (!IS_2_WORD_TYPE(r->interfaces[len][s2].type)) {
- if (!(r->interfaces[len][s2].flags & INMEMORY)) {
- M_INTMOVE(s1, r->interfaces[len][s2].regoff);
+ if (!IS_2_WORD_TYPE(rd->interfaces[len][s2].type)) {
+ if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
+ M_INTMOVE(s1, rd->interfaces[len][s2].regoff);
} else {
- i386_mov_reg_membase(cd, s1, REG_SP, r->interfaces[len][s2].regoff * 8);
+ i386_mov_reg_membase(cd, s1, REG_SP, rd->interfaces[len][s2].regoff * 8);
}
} else {
- if (r->interfaces[len][s2].flags & INMEMORY) {
- M_LNGMEMMOVE(s1, r->interfaces[len][s2].regoff);
+ if (rd->interfaces[len][s2].flags & INMEMORY) {
+ M_LNGMEMMOVE(s1, rd->interfaces[len][s2].regoff);
} else {
panic("copy interface registers: longs have to be in memory (end)");
} /* if (bptr -> flags >= BBREACHED) */
} /* for basic block */
- codegen_createlinenumbertable(m);
+ codegen_createlinenumbertable(cd);
{
/* generate bound check stubs */
u1 *xcodeptr = NULL;
-
- for (; cd->xboundrefs != NULL; cd->xboundrefs = cd->xboundrefs->next) {
- gen_resolvebranch(cd->mcodebase + cd->xboundrefs->branchpos,
- cd->xboundrefs->branchpos,
+ branchref *bref;
+
+ for (bref = cd->xboundrefs; bref != NULL; bref = bref->next) {
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(8);
+ MCODECHECK(100);
/* move index register into REG_ITMP1 */
- i386_mov_reg_reg(cd, cd->xboundrefs->reg, REG_ITMP1); /* 2 bytes */
+ i386_mov_reg_reg(cd, bref->reg, REG_ITMP1); /* 2 bytes */
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
- dseg_adddata(m, cd->mcodeptr);
- i386_mov_imm_reg(cd, cd->xboundrefs->branchpos - 6, REG_ITMP3);/* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP3, REG_ITMP2_XPC); /* 2 bytes */
+ i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ dseg_adddata(cd, cd->mcodeptr);
+ i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP3); /* 5 bytes */
+ i386_alu_reg_reg(cd, I386_ADD, REG_ITMP3, REG_ITMP2_XPC); /* 2 bytes */
if (xcodeptr != NULL) {
i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
i386_push_reg(cd, REG_ITMP2_XPC);
- PREPARE_NATIVE_STACKINFO;
+ /*PREPARE_NATIVE_STACKINFO;*/
+ i386_push_imm(cd,0); /* the pushed XPC is directly below the java frame*/
+ i386_push_imm(cd,0);
+ i386_mov_imm_reg(cd,(s4)asm_prepare_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
- i386_alu_imm_reg(cd, I386_SUB, 2 * 4, REG_SP);
- i386_mov_imm_membase(cd, (s4) string_java_lang_ArrayIndexOutOfBoundsException, REG_SP, 0 * 4);
- i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 1 * 4);
- i386_mov_imm_reg(cd, (s4) new_exception_int, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
- i386_alu_imm_reg(cd, I386_ADD, 2 * 4, REG_SP);
+ i386_alu_imm_reg(cd, I386_SUB, 1 * 4, REG_SP);
+ i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, 0 * 4);
+ i386_mov_imm_reg(cd, (u4) new_arrayindexoutofboundsexception, REG_ITMP1);
+ i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
+ i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);
- REMOVE_NATIVE_STACKINFO;
+ /*REMOVE_NATIVE_STACKINFO;*/
+ i386_mov_imm_reg(cd,(s4)asm_remove_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
i386_pop_reg(cd, REG_ITMP2_XPC);
xcodeptr = NULL;
- for (; cd->xcheckarefs != NULL; cd->xcheckarefs = cd->xcheckarefs->next) {
- if ((m->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + cd->xcheckarefs->branchpos,
- cd->xcheckarefs->branchpos,
+ for (bref = cd->xcheckarefs; bref != NULL; bref = bref->next) {
+ if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
xcodeptr - cd->mcodebase - (5 + 5 + 2));
continue;
}
- gen_resolvebranch(cd->mcodebase + cd->xcheckarefs->branchpos,
- cd->xcheckarefs->branchpos,
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(8);
+ MCODECHECK(100);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
- dseg_adddata(m, cd->mcodeptr);
- i386_mov_imm_reg(cd, cd->xcheckarefs->branchpos - 6, REG_ITMP1);/* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
+ i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ dseg_adddata(cd, cd->mcodeptr);
+ i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
+ i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
if (xcodeptr != NULL) {
i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
i386_push_reg(cd, REG_ITMP2_XPC);
- PREPARE_NATIVE_STACKINFO;
+ /*PREPARE_NATIVE_STACKINFO;*/
+ i386_push_imm(cd,0); /* the pushed XPC is directly below the java frame*/
+ i386_push_imm(cd,0);
+ i386_mov_imm_reg(cd,(s4)asm_prepare_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
- i386_alu_imm_reg(cd, I386_SUB, 1 * 4, REG_SP);
- i386_mov_imm_membase(cd, (s4) string_java_lang_NegativeArraySizeException, REG_SP, 0 * 4);
- i386_mov_imm_reg(cd, (s4) new_exception, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
- i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);
- REMOVE_NATIVE_STACKINFO;
+ i386_mov_imm_reg(cd, (u4) new_negativearraysizeexception, REG_ITMP1);
+ i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
+ /*i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);*/
+
+
+ /*REMOVE_NATIVE_STACKINFO;*/
+ i386_mov_imm_reg(cd,(s4)asm_remove_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
+
i386_pop_reg(cd, REG_ITMP2_XPC);
xcodeptr = NULL;
- for (; cd->xcastrefs != NULL; cd->xcastrefs = cd->xcastrefs->next) {
- if ((m->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + cd->xcastrefs->branchpos,
- cd->xcastrefs->branchpos,
+ for (bref = cd->xcastrefs; bref != NULL; bref = bref->next) {
+ if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
xcodeptr - cd->mcodebase - (5 + 5 + 2));
continue;
}
- gen_resolvebranch(cd->mcodebase + cd->xcastrefs->branchpos,
- cd->xcastrefs->branchpos,
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(8);
+ MCODECHECK(100);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
- dseg_adddata(m, cd->mcodeptr);
- i386_mov_imm_reg(cd, cd->xcastrefs->branchpos - 6, REG_ITMP1); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
+ i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ dseg_adddata(cd, cd->mcodeptr);
+ i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
+ i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
if (xcodeptr != NULL) {
i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
i386_push_reg(cd, REG_ITMP2_XPC);
+ /*PREPARE_NATIVE_STACKINFO;*/
+ i386_push_imm(cd,0); /* the pushed XPC is directly below the java frame*/
+ i386_push_imm(cd,0);
+ i386_mov_imm_reg(cd,(s4)asm_prepare_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
- PREPARE_NATIVE_STACKINFO;
- i386_alu_imm_reg(cd, I386_SUB, 1 * 4, REG_SP);
- i386_mov_imm_membase(cd, (s4) string_java_lang_ClassCastException, REG_SP, 0 * 4);
- i386_mov_imm_reg(cd, (s4) new_exception, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
- i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);
+ i386_mov_imm_reg(cd, (u4) new_classcastexception, REG_ITMP1);
+ i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
+ /*i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);*/
+
+ /*REMOVE_NATIVE_STACKINFO;*/
+ i386_mov_imm_reg(cd,(s4)asm_remove_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
- REMOVE_NATIVE_STACKINFO;
i386_pop_reg(cd, REG_ITMP2_XPC);
- i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
+ i386_mov_imm_reg(cd, (u4) asm_handle_exception, REG_ITMP3);
i386_jmp_reg(cd, REG_ITMP3);
}
}
xcodeptr = NULL;
- for (; cd->xdivrefs != NULL; cd->xdivrefs = cd->xdivrefs->next) {
- if ((m->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + cd->xdivrefs->branchpos,
- cd->xdivrefs->branchpos,
+ for (bref = cd->xdivrefs; bref != NULL; bref = bref->next) {
+ if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
xcodeptr - cd->mcodebase - (5 + 5 + 2));
continue;
}
- gen_resolvebranch(cd->mcodebase + cd->xdivrefs->branchpos,
- cd->xdivrefs->branchpos,
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(8);
+ MCODECHECK(100);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
- dseg_adddata(m, cd->mcodeptr);
- i386_mov_imm_reg(cd, cd->xdivrefs->branchpos - 6, REG_ITMP1); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
+ i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ dseg_adddata(cd, cd->mcodeptr);
+ i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
+ i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
if (xcodeptr != NULL) {
i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
i386_push_reg(cd, REG_ITMP2_XPC);
- PREPARE_NATIVE_STACKINFO;
+ /*PREPARE_NATIVE_STACKINFO;*/
+ i386_push_imm(cd,0); /* the pushed XPC is directly below the java frame*/
+ i386_push_imm(cd,0);
+ i386_mov_imm_reg(cd,(s4)asm_prepare_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
- i386_alu_imm_reg(cd, I386_SUB, 2 * 4, REG_SP);
- i386_mov_imm_membase(cd, (s4) string_java_lang_ArithmeticException, REG_SP, 0 * 4);
- i386_mov_imm_membase(cd, (s4) string_java_lang_ArithmeticException_message, REG_SP, 1 * 4);
- i386_mov_imm_reg(cd, (s4) new_exception_message, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
- i386_alu_imm_reg(cd, I386_ADD, 2 * 4, REG_SP);
- REMOVE_NATIVE_STACKINFO;
+
+ i386_mov_imm_reg(cd, (u4) new_arithmeticexception, REG_ITMP1);
+ i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
+
+ /*REMOVE_NATIVE_STACKINFO;*/
+ i386_mov_imm_reg(cd,(s4)asm_remove_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
+
i386_pop_reg(cd, REG_ITMP2_XPC);
xcodeptr = NULL;
- for (; cd->xexceptionrefs != NULL; cd->xexceptionrefs = cd->xexceptionrefs->next) {
- if ((m->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + cd->xexceptionrefs->branchpos,
- cd->xexceptionrefs->branchpos,
+ for (bref = cd->xexceptionrefs; bref != NULL; bref = bref->next) {
+ if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
xcodeptr - cd->mcodebase - (5 + 5 + 2));
continue;
}
- gen_resolvebranch(cd->mcodebase + cd->xexceptionrefs->branchpos,
- cd->xexceptionrefs->branchpos,
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(8);
+ MCODECHECK(200);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
- dseg_adddata(m, cd->mcodeptr);
- i386_mov_imm_reg(cd, cd->xexceptionrefs->branchpos - 6, REG_ITMP1);/* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
+ i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ dseg_adddata(cd, cd->mcodeptr);
+ i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
+ i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
if (xcodeptr != NULL) {
i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
i386_push_reg(cd, REG_ITMP2_XPC);
- PREPARE_NATIVE_STACKINFO;
+ /*PREPARE_NATIVE_STACKINFO;*/
+ i386_push_imm(cd,0); /* the pushed XPC is directly below the java frame*/
+ i386_push_imm(cd,0);
+ i386_mov_imm_reg(cd,(s4)asm_prepare_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
+
i386_mov_imm_reg(cd, (s4) codegen_general_stubcalled, REG_ITMP1);
i386_call_reg(cd, REG_ITMP1);
i386_pop_reg(cd, REG_ITMP1_XPTR);
i386_pop_reg(cd, REG_ITMP3); /* just remove the no longer needed 0 from the stack*/
- REMOVE_NATIVE_STACKINFO;
+ /*REMOVE_NATIVE_STACKINFO;*/
+ i386_mov_imm_reg(cd,(s4)asm_remove_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
+
i386_pop_reg(cd, REG_ITMP2_XPC);
xcodeptr = NULL;
- for (; cd->xnullrefs != NULL; cd->xnullrefs = cd->xnullrefs->next) {
- if ((m->exceptiontablelength == 0) && (xcodeptr != NULL)) {
- gen_resolvebranch(cd->mcodebase + cd->xnullrefs->branchpos,
- cd->xnullrefs->branchpos,
+ for (bref = cd->xnullrefs; bref != NULL; bref = bref->next) {
+ if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
xcodeptr - cd->mcodebase - (5 + 5 + 2));
continue;
}
- gen_resolvebranch(cd->mcodebase + cd->xnullrefs->branchpos,
- cd->xnullrefs->branchpos,
+ gen_resolvebranch(cd->mcodebase + bref->branchpos,
+ bref->branchpos,
cd->mcodeptr - cd->mcodebase);
- MCODECHECK(8);
+ MCODECHECK(100);
- i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
- dseg_adddata(m, cd->mcodeptr);
- i386_mov_imm_reg(cd, cd->xnullrefs->branchpos - 6, REG_ITMP1); /* 5 bytes */
- i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
+ i386_mov_imm_reg(cd, 0, REG_ITMP2_XPC); /* 5 bytes */
+ dseg_adddata(cd, cd->mcodeptr);
+ i386_mov_imm_reg(cd, bref->branchpos - 6, REG_ITMP1); /* 5 bytes */
+ i386_alu_reg_reg(cd, I386_ADD, REG_ITMP1, REG_ITMP2_XPC); /* 2 bytes */
if (xcodeptr != NULL) {
i386_jmp_imm(cd, (xcodeptr - cd->mcodeptr) - 5);
i386_push_reg(cd, REG_ITMP2_XPC);
+ /*PREPARE_NATIVE_STACKINFO;*/
+ i386_push_imm(cd,0); /* the pushed XPC is directly below the java frame*/
+ i386_push_imm(cd,0);
+ i386_mov_imm_reg(cd,(s4)asm_prepare_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
+
- PREPARE_NATIVE_STACKINFO;
#if 0
/* create native call block*/
i386_mov_reg_membase(cd, REG_SP,REG_RESULT,0); /* store pointer to new stack frame information */
#endif
- /* create exception*/
- i386_alu_imm_reg(cd, I386_SUB, 1 * 4, REG_SP);
- i386_mov_imm_membase(cd, (s4) string_java_lang_NullPointerException, REG_SP, 0 * 4);
- i386_mov_imm_reg(cd, (s4) new_exception, REG_ITMP1);
- i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
- i386_alu_imm_reg(cd, I386_ADD, 1 * 4, REG_SP);
+ i386_mov_imm_reg(cd, (u4) new_nullpointerexception, REG_ITMP1);
+ i386_call_reg(cd, REG_ITMP1); /* return value is REG_ITMP1_XPTR */
+ /*REMOVE_NATIVE_STACKINFO;*/
+ i386_mov_imm_reg(cd,(s4)asm_remove_native_stackinfo,REG_ITMP3);
+ i386_call_reg(cd,REG_ITMP3);
- REMOVE_NATIVE_STACKINFO;
#if 0
/* restore native call stack */
i386_alu_imm_reg(cd, I386_ADD,3*4,REG_SP);
#endif
-
i386_pop_reg(cd, REG_ITMP2_XPC);
i386_mov_imm_reg(cd, (s4) asm_handle_exception, REG_ITMP3);
i386_jmp_reg(cd, REG_ITMP3);
}
}
+
+ /* generate put/getstatic stub call code */
+
+ {
+ clinitref *cref;
+ codegendata *tmpcd;
+ u1 xmcode;
+ u4 mcode;
+
+ tmpcd = DNEW(codegendata);
+
+ for (cref = cd->clinitrefs; cref != NULL; cref = cref->next) {
+ /* Get machine code which is patched back in later. A */
+ /* `call rel32' is 5 bytes long. */
+ xcodeptr = cd->mcodebase + cref->branchpos;
+ xmcode = *xcodeptr;
+ mcode = *((u4 *) (xcodeptr + 1));
+
+ MCODECHECK(50);
+
+ /* patch in `call rel32' to call the following code */
+ tmpcd->mcodeptr = xcodeptr; /* set dummy mcode pointer */
+ i386_call_imm(tmpcd, cd->mcodeptr - (xcodeptr + 5));
+
+ /* Save current stack pointer into a temporary register. */
+ i386_mov_reg_reg(cd, REG_SP, REG_ITMP1);
+
+ /* Push machine code bytes to patch onto the stack. */
+ i386_push_imm(cd, (u4) xmcode);
+ i386_push_imm(cd, (u4) mcode);
+
+ i386_push_imm(cd, (u4) cref->class);
+
+ /* Push previously saved stack pointer onto stack. */
+ i386_push_reg(cd, REG_ITMP1);
+
+ i386_mov_imm_reg(cd, (u4) asm_check_clinit, REG_ITMP1);
+ i386_jmp_reg(cd, REG_ITMP1);
+ }
+ }
}
- codegen_finish(m, (u4) (cd->mcodeptr - cd->mcodebase));
+ codegen_finish(m, cd, (u4) (cd->mcodeptr - cd->mcodebase));
}
{
u1 *s = CNEW(u1, COMPSTUBSIZE); /* memory to hold the stub */
codegendata *cd;
+ s4 dumpsize;
- /* setup codegendata structure */
- codegen_setup(m);
+ /* mark start of dump memory area */
- cd = m->codegendata;
+ dumpsize = dump_size();
+
+ cd = DNEW(codegendata);
cd->mcodeptr = s;
/* code for the stub */
i386_mov_imm_reg(cd, (u4) asm_call_jit_compiler, REG_ITMP3);
i386_jmp_reg(cd, REG_ITMP3); /* jump to compiler */
- /* free codegendata memory */
- codegen_close(m);
-
#if defined(STATISTICS)
if (opt_stat)
count_cstub_len += COMPSTUBSIZE;
#endif
+ /* release dump area */
+
+ dump_release(dumpsize);
+
return s;
}
*******************************************************************************/
-#define NATIVESTUBSIZE 350
+#define NATIVESTUBSIZE 370 + 36
+
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
static java_objectheader **(*callgetexceptionptrptr)() = builtin_get_exceptionptrptr;
}
+
u1 *createnativestub(functionptr f, methodinfo *m)
{
u1 *s = CNEW(u1, NATIVESTUBSIZE); /* memory to hold the stub */
+ codegendata *cd;
+ registerdata *rd;
+ t_inlining_globals *id;
+ s4 dumpsize;
+
int addmethod=0;
u1 *tptr;
int i;
- int stackframesize = 4+12; /* initial 4 bytes is space for jni env,
- + 4 byte thread pointer + 4 byte previous pointer + method info*/
+ int stackframesize = 4+16; /* initial 4 bytes is space for jni env,
+ + 4 byte thread pointer + 4 byte previous pointer + method info + 4 offset native*/
int stackframeoffset = 4;
int p, t;
- codegendata *cd;
- /* setup codegendata structure */
- codegen_setup(m);
+ void** callAddrPatchPos=0;
+ u1* jmpInstrPos=0;
+ void** jmpInstrPatchPos=0;
+
+ /* mark start of dump memory area */
+
+ dumpsize = dump_size();
+
+ /* allocate required dump memory */
+
+ cd = DNEW(codegendata);
+ rd = DNEW(registerdata);
+ id = DNEW(t_inlining_globals);
- cd = m->codegendata;
+ /* setup registers before using it */
+
+ inlining_setup(m, id);
+ reg_setup(m, rd, id);
+
+ /* set some required varibles which are normally set by codegen_setup */
+ cd->mcodebase = s;
cd->mcodeptr = s;
+ cd->clinitrefs = NULL;
if (m->flags & ACC_STATIC) {
stackframesize += 4;
stackframeoffset += 4;
}
- reg_init(m);
descriptor2types(m); /* set paramcount and paramtypes */
/*DEBUG*/
/* if function is static, check for initialized */
if (m->flags & ACC_STATIC) {
- /* if class isn't yet initialized, do it */
+ /* if class isn't yet initialized, do it */
if (!m->class->initialized) {
s4 *header = (s4 *) s;
*header = 0;/*extablesize*/
- header;
+ header++;
*header = 0;/*line number table start*/
header++;
*header = 0;/*line number table size*/
*header = 0;/*framesize*/
header++;
*header = (u4) m;/*methodpointer*/
- *header++;
- cd->mcodeptr = s = (u1 *) header;
+ header++;
+
+ s = (u1 *) header;
+
+ cd->mcodebase = s;
+ cd->mcodeptr = s;
addmethod = 1;
- /* call helper function which patches this code */
- i386_mov_imm_reg(cd, (u4) m->class, REG_ITMP1);
- i386_mov_imm_reg(cd, (u4) asm_check_clinit, REG_ITMP2);
- i386_call_reg(cd, REG_ITMP2);
+ codegen_addclinitref(cd, cd->mcodeptr, m->class);
}
}
i386_alu_imm_reg(cd, I386_SUB, stackframesize, REG_SP);
/* CREATE DYNAMIC STACK INFO -- BEGIN*/
- i386_mov_imm_membase(cd, (s4) m, REG_SP,stackframesize-4);
+ i386_mov_imm_membase(cd,0,REG_SP,stackframesize-4);
+ i386_mov_imm_membase(cd, (s4) m, REG_SP,stackframesize-8);
i386_mov_imm_reg(cd, (s4) builtin_asm_get_stackframeinfo, REG_ITMP1);
i386_call_reg(cd, REG_ITMP1);
- i386_mov_reg_membase(cd, REG_RESULT,REG_SP,stackframesize-8); /*save thread specific pointer*/
+ i386_mov_reg_membase(cd, REG_RESULT,REG_SP,stackframesize-12); /*save thread specific pointer*/
i386_mov_membase_reg(cd, REG_RESULT,0,REG_ITMP2);
- i386_mov_reg_membase(cd, REG_ITMP2,REG_SP,stackframesize-12); /*save previous value of memory adress pointed to by thread specific pointer*/
+ i386_mov_reg_membase(cd, REG_ITMP2,REG_SP,stackframesize-16); /*save previous value of memory adress pointed to by thread specific pointer*/
i386_mov_reg_reg(cd, REG_SP,REG_ITMP2);
- i386_alu_imm_reg(cd, I386_ADD,stackframesize-12,REG_ITMP2);
+ i386_alu_imm_reg(cd, I386_ADD,stackframesize-16,REG_ITMP2);
i386_mov_reg_membase(cd, REG_ITMP2,REG_RESULT,0);
/*TESTING ONLY */
/* CREATE DYNAMIC STACK INFO -- END*/
+/* RESOLVE NATIVE METHOD -- BEGIN*/
+#ifndef STATIC_CLASSPATH
+ if (f==0) {
+ /*log_text("Dynamic classpath: preparing for delayed native function resolving");*/
+ i386_jmp_imm(cd,0);
+ jmpInstrPos=cd->mcodeptr-4;
+ /*patchposition*/
+ i386_mov_imm_reg(cd,jmpInstrPos,REG_ITMP1);
+ i386_push_reg(cd,REG_ITMP1);
+ /*jmp offset*/
+ i386_mov_imm_reg(cd,0,REG_ITMP1);
+ jmpInstrPatchPos=cd->mcodeptr-4;
+ i386_push_reg(cd,REG_ITMP1);
+ /*position of call address to patch*/
+ i386_mov_imm_reg(cd,0,REG_ITMP1);
+ callAddrPatchPos=(cd->mcodeptr-4);
+ i386_push_reg(cd,REG_ITMP1);
+ /*method info structure*/
+ i386_mov_imm_reg(cd,(s4) m, REG_ITMP1);
+ i386_push_reg(cd,REG_ITMP1);
+ /*call resolve functions*/
+ i386_mov_imm_reg(cd, (s4)codegen_resolve_native,REG_ITMP1);
+ i386_call_reg(cd,REG_ITMP1);
+ /*cleanup*/
+ i386_pop_reg(cd,REG_ITMP1);
+ i386_pop_reg(cd,REG_ITMP1);
+ i386_pop_reg(cd,REG_ITMP1);
+ i386_pop_reg(cd,REG_ITMP1);
+ /*fix jmp offset replacement*/
+ (*jmpInstrPatchPos)=cd->mcodeptr-jmpInstrPos-4;
+ } /*else log_text("Dynamic classpath: immediate native function resolution possible");*/
+#endif
+/* RESOLVE NATIVE METHOD -- END*/
+
+
tptr = m->paramtypes;
for (i = 0; i < m->paramcount; i++) {
i386_mov_imm_membase(cd, (s4) &env, REG_SP, 0);
i386_mov_imm_reg(cd, (s4) f, REG_ITMP1);
+#ifndef STATIC_CLASSPATH
+ if (f==0)
+ (*callAddrPatchPos)=(cd->mcodeptr-4);
+#endif
i386_call_reg(cd, REG_ITMP1);
+
/*REMOVE DYNAMIC STACK INFO -BEGIN */
i386_push_reg(cd, REG_RESULT2);
- i386_mov_membase_reg(cd, REG_SP,stackframesize-8,REG_ITMP2); /*old value*/
- i386_mov_membase_reg(cd, REG_SP,stackframesize-4,REG_RESULT2); /*pointer*/
+ i386_mov_membase_reg(cd, REG_SP,stackframesize-12,REG_ITMP2); /*old value*/
+ i386_mov_membase_reg(cd, REG_SP,stackframesize-8,REG_RESULT2); /*pointer*/
i386_mov_reg_membase(cd, REG_ITMP2,REG_RESULT2,0);
i386_pop_reg(cd, REG_RESULT2);
/*REMOVE DYNAMIC STACK INFO -END */
i386_alu_imm_reg(cd, I386_ADD, 4 + 8 + 8 + 4, REG_SP);
}
-
/* we can't use REG_ITMP3 == REG_RESULT2 */
#if defined(USE_THREADS) && defined(NATIVE_THREADS)
i386_push_reg(cd, REG_RESULT);
codegen_insertmethod(s, cd->mcodeptr);
}
+ {
+ u1 *xcodeptr;
+ clinitref *cref;
+ codegendata *tmpcd;
+ u1 xmcode;
+ u4 mcode;
+
+ tmpcd = DNEW(codegendata);
+
+ /* there can only be one clinit ref entry */
+ cref = cd->clinitrefs;
+
+ if (cref) {
+ /* Get machine code which is patched back in later. A */
+ /* `call rel32' is 5 bytes long. */
+ xcodeptr = cd->mcodebase + cref->branchpos;
+ xmcode = *xcodeptr;
+ mcode = *((u4 *) (xcodeptr + 1));
+
+ /* patch in `call rel32' to call the following code */
+ tmpcd->mcodeptr = xcodeptr; /* set dummy mcode pointer */
+ i386_call_imm(tmpcd, cd->mcodeptr - (xcodeptr + 5));
+
+ /* Save current stack pointer into a temporary register. */
+ i386_mov_reg_reg(cd, REG_SP, REG_ITMP1);
+
+ /* Push machine code bytes to patch onto the stack. */
+ i386_push_imm(cd, (u4) xmcode);
+ i386_push_imm(cd, (u4) mcode);
+
+ i386_push_imm(cd, (u4) cref->class);
+
+ /* Push previously saved stack pointer onto stack. */
+ i386_push_reg(cd, REG_ITMP1);
+
+ i386_mov_imm_reg(cd, (u4) asm_check_clinit, REG_ITMP1);
+ i386_jmp_reg(cd, REG_ITMP1);
+ }
+ }
+
#if 0
- dolog_plain("native stubentry: %p, stubsize: %x (for %d params) --", (s4)s,(s4) (cd->mcodeptr - s), m->paramcount);
+ dolog_plain("native stubentry: %p, stubsize: %d (for %d params) --", (s4)s,(s4) (cd->mcodeptr - s), m->paramcount);
utf_display(m->name);
dolog_plain("\n");
#endif
- /* free codegendata memory */
- codegen_close(m);
-
#if defined(STATISTICS)
if (opt_stat)
count_nstub_len += NATIVESTUBSIZE;
#endif
+ /* release dump area */
+
+ dump_release(dumpsize);
+
return s;
}
projects / cacao.git / blobdiff