* src/vm/jit/jit.cpp: Eliminate one instance of useless cache flushing.

[cacao.git] / src / vm / jit / alpha / md-atomic.hpp

diff --git a/src/vm/jit/alpha/md-atomic.hpp b/src/vm/jit/alpha/md-atomic.hpp
index efdec57672e7d976e296f5d5aa325aa49a6fdd67..07c3a85428a5c61dd98aeffd3930e9d5b8e91507 100644 (file)
--- a/src/vm/jit/alpha/md-atomic.hpp
+++ b/src/vm/jit/alpha/md-atomic.hpp
@@ -32,6 +32,7 @@
 
 #include "threads/atomic.hpp"
 
+namespace Atomic_md {
 
 /**
  * An atomic compare and swap for 32-bit integer values.
@@ -42,7 +43,7 @@
  *
  * @return value of the memory location before the store
  */
-inline static uint32_t Atomic_compare_and_swap_32(volatile uint32_t *p, uint32_t oldval, uint32_t newval)
+inline uint32_t compare_and_swap(volatile uint32_t *p, uint32_t oldval, uint32_t newval)
 {
        uint32_t temp;
        uint32_t result;
@@ -72,7 +73,7 @@ inline static uint32_t Atomic_compare_and_swap_32(volatile uint32_t *p, uint32_t
  *
  * @return value of the memory location before the store
  */
-inline static uint64_t Atomic_compare_and_swap_64(volatile uint64_t *p, uint64_t oldval, uint64_t newval)
+inline uint64_t compare_and_swap(volatile uint64_t *p, uint64_t oldval, uint64_t newval)
 {
        uint64_t temp;
        uint64_t result;
@@ -94,31 +95,32 @@ inline static uint64_t Atomic_compare_and_swap_64(volatile uint64_t *p, uint64_t
 
 
 /**
- * An atomic compare and swap for pointer values.
- *
- * @param p      Pointer to memory address.
- * @param oldval Old value to be expected.
- * @param newval New value to be stored.
- *
- * @return value of the memory location before the store
+ * A memory barrier.
  */
-inline static void* Atomic_compare_and_swap_ptr(volatile void** p, void* oldval, void* newval)
+inline void memory_barrier(void)
 {
-       return (void*) Atomic_compare_and_swap_64((volatile uint64_t*) p, (uint64_t) oldval, (uint64_t) newval);
+       __asm__ __volatile__ ("mb" : : : "memory");
 }
 
 
 /**
- * A memory barrier.
+ * A write memory barrier.
  */
-inline static void Atomic_memory_barrier(void)
+inline void write_memory_barrier(void)
 {
-       __asm__ __volatile__ ("mb" : : : "memory");
+       __asm__ __volatile__ ("wmb" : : : "memory");
 }
 
 
-#define STORE_ORDER_BARRIER() __asm__ __volatile__ ("wmb" : : : "memory");
-#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ ("mb" : : : "memory");
+/**
+ * An instruction barrier.
+ */
+inline void instruction_barrier(void)
+{
+       __asm__ __volatile__ ("mb" : : : "memory");
+}
+
+}
 
 #endif // _MD_ATOMIC_HPP