-/* vm/jit/alpha/codegen.h - code generation macros and definitions for alpha
+/* src/vm/jit/alpha/codegen.h - code generation macros and definitions for Alpha
- Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
- R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
- C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
- Institut f. Computersprachen - TU Wien
+ Copyright (C) 1996-2005, 2006, 2007
+ CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
+ Copyright (C) 2008 Theobroma Systems Ltd.
This file is part of CACAO.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA.
-
- Contact: cacao@complang.tuwien.ac.at
-
- Authors: Andreas Krall
- Reinhard Grafl
-
- $Id: codegen.h 2397 2005-04-27 12:44:54Z twisti $
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
*/
#ifndef _CODEGEN_H
#define _CODEGEN_H
-#include <ucontext.h>
-
-/* SET_ARG_STACKSLOTS ***************************************************
-Macro for stack.c to set Argument Stackslots
-
-Sets the first call_argcount stackslots of curstack to varkind ARGVAR, if
-they to not have the SAVEDVAR flag set. According to the calling
-conventions these stackslots are assigned argument registers or memory
-locations
-
---- in
-i,call_argcount: Number of arguments for this method
-curstack: instack of the method invokation
-
---- uses
-i, copy
-
---- out
-copy: Points to first stackslot after the parameters
-rd->argintreguse: max. number of used integer argument register so far
-rd->argfltreguse: max. number of used float argument register so far
-rd->ifmemuse: max. number of stackslots used for spilling parameters
- so far
-************************************************************************/
-#define SET_ARG_STACKSLOTS { \
- s4 stacksize; /* Stackoffset for spilled arg */ \
- s4 iarg = 0; \
- s4 farg = 0; \
- \
- stacksize = (i < rd->intreg_argnum)? 0 : (i - rd->intreg_argnum); \
- if (rd->ifmemuse < stacksize) \
- rd->ifmemuse = stacksize; \
- \
- copy = curstack; \
- for (;i > 0; i--) { \
- if (IS_FLT_DBL_TYPE(copy->type)) { \
- if (farg == 0) farg = i; \
- } else { \
- if (iarg == 0) iarg = i; \
- } \
- copy = copy->prev; \
- } \
- \
- if (rd->argintreguse < iarg) \
- rd->argintreguse = iarg; \
- if (rd->argfltreguse < farg) \
- rd->argfltreguse = farg; \
- \
- i = call_argcount; \
- copy = curstack; \
- while (--i >= 0) { \
- if (!(copy->flags & SAVEDVAR)) { \
- copy->varnum = i; \
- copy->varkind = ARGVAR; \
- if (IS_FLT_DBL_TYPE(copy->type)) { \
- if (i < rd->fltreg_argnum) { \
- copy->flags = 0; \
- copy->regoff = rd->argfltregs[i]; \
- } else { \
- copy->flags = INMEMORY; \
- copy->regoff = --stacksize; \
- } \
- } else { /* int arg */ \
- if (i < rd->intreg_argnum) { \
- copy->flags = 0; \
- copy->regoff = rd->argintregs[i]; \
- } else { \
- copy->flags = INMEMORY; \
- copy->regoff = --stacksize; \
- } \
- } \
- } \
- copy = copy->prev; \
- } \
- }
-
-/* additional functions and macros to generate code ***************************/
-
-/* #define BlockPtrOfPC(pc) block+block_index[pc] */
-#define BlockPtrOfPC(pc) ((basicblock *) iptr->target)
-
+#include "config.h"
+#include "vm/types.h"
-#ifdef STATISTICS
-#define COUNT_SPILLS count_spills++
-#else
-#define COUNT_SPILLS
-#endif
+#include "vm/jit/jit.hpp"
-/* gen_nullptr_check(objreg) */
-
-#define gen_nullptr_check(objreg) \
- if (checknull) { \
- M_BEQZ((objreg), 0); \
- codegen_addxnullrefs(cd, mcodeptr); \
- }
+/* additional functions and macros to generate code ***************************/
#define gen_bound_check \
if (checkbounds) { \
M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));\
M_CMPULT(s2, REG_ITMP3, REG_ITMP3);\
M_BEQZ(REG_ITMP3, 0);\
- codegen_addxboundrefs(cd, mcodeptr, s2); \
+ codegen_add_arrayindexoutofboundsexception_ref(cd, s2); \
}
/* MCODECHECK(icnt) */
#define MCODECHECK(icnt) \
- if ((mcodeptr + (icnt)) > cd->mcodeend) \
- mcodeptr = codegen_increase(cd, (u1 *) mcodeptr)
+ do { \
+ if ((cd->mcodeptr + (icnt) * 4) > cd->mcodeend) \
+ codegen_increase(cd); \
+ } while (0)
#define ALIGNCODENOP \
- if ((s4) ((ptrint) mcodeptr & 7)) { \
+ if ((s4) ((ptrint) cd->mcodeptr & 7)) { \
M_NOP; \
}
-/* M_INTMOVE:
- generates an integer-move from register a to b.
- if a and b are the same int-register, no code will be generated.
-*/
+#define ICONST(d,c) emit_iconst(cd, (d), (c))
+#define LCONST(d,c) emit_lconst(cd, (d), (c))
-#define M_INTMOVE(a,b) if (a != b) { M_MOV(a, b); }
+/* branch defines *************************************************************/
-/* M_FLTMOVE:
- generates a floating-point-move from register a to b.
- if a and b are the same float-register, no code will be generated
-*/
+#define BRANCH_NOPS \
+ do { \
+ M_NOP; \
+ } while (0)
-#define M_FLTMOVE(a,b) if (a != b) { M_FMOV(a, b); }
+/* patcher defines ************************************************************/
-/* var_to_reg_xxx:
- this function generates code to fetch data from a pseudo-register
- into a real register.
- If the pseudo-register has actually been assigned to a real
- register, no code will be emitted, since following operations
- can use this register directly.
-
- v: pseudoregister to be fetched from
- tempregnum: temporary register to be used if v is actually spilled to ram
+#define PATCHER_CALL_SIZE 1 * 4 /* an instruction is 4-bytes long */
- return: the register number, where the operand can be found after
- fetching (this wil be either tempregnum or the register
- number allready given to v)
-*/
+#define PATCHER_NOPS \
+ do { \
+ M_NOP; \
+ } while (0)
-#define var_to_reg_int(regnr,v,tempnr) { \
- if ((v)->flags & INMEMORY) { \
- COUNT_SPILLS; \
- M_LLD(tempnr, REG_SP, 8 * (v)->regoff); \
- regnr = tempnr; \
- } else regnr = (v)->regoff; \
-}
-
-
-#define var_to_reg_flt(regnr,v,tempnr) { \
- if ((v)->flags & INMEMORY) { \
- COUNT_SPILLS; \
- M_DLD(tempnr, REG_SP, 8 * (v)->regoff); \
- regnr = tempnr; \
- } else regnr = (v)->regoff; \
-}
-
-
-/* store_reg_to_var_xxx:
- This function generates the code to store the result of an operation
- back into a spilled pseudo-variable.
- If the pseudo-variable has not been spilled in the first place, this
- function will generate nothing.
-
- v ............ Pseudovariable
- tempregnum ... Number of the temporary registers as returned by
- reg_of_var.
-*/
-
-#define store_reg_to_var_int(sptr, tempregnum) { \
- if ((sptr)->flags & INMEMORY) { \
- COUNT_SPILLS; \
- M_LST(tempregnum, REG_SP, 8 * (sptr)->regoff); \
- } \
- }
-
-#define store_reg_to_var_flt(sptr, tempregnum) { \
- if ((sptr)->flags & INMEMORY) { \
- COUNT_SPILLS; \
- M_DST(tempregnum, REG_SP, 8 * (sptr)->regoff); \
- } \
- }
-
-
-#define M_COPY(from,to) \
- d = reg_of_var(rd, to, REG_IFTMP); \
- if ((from->regoff != to->regoff) || \
- ((from->flags ^ to->flags) & INMEMORY)) { \
- if (IS_FLT_DBL_TYPE(from->type)) { \
- var_to_reg_flt(s1, from, d); \
- M_FLTMOVE(s1,d); \
- store_reg_to_var_flt(to, d); \
- }\
- else { \
- var_to_reg_int(s1, from, d); \
- M_INTMOVE(s1,d); \
- store_reg_to_var_int(to, d); \
- }\
- }
-
-
-#define ICONST(r,c) \
- if ((c) >= -32768 && (c) <= 32767) { \
- M_LDA((r), REG_ZERO, c); \
- } else { \
- a = dseg_adds4(cd, (c)); \
- M_ILD((r), REG_PV, a); \
- }
-#define LCONST(r,c) \
- if ((c) >= -32768 && (c) <= 32767) { \
- M_LDA((r), REG_ZERO, (c)); \
- } else { \
- a = dseg_adds8(cd, (c)); \
- M_LLD((r), REG_PV, a); \
- }
+/* macros to create code ******************************************************/
+/* M_MEM - memory instruction format *******************************************
+
+ Opcode ........ opcode
+ Ra ............ source/target register for memory access
+ Rb ............ base register
+ Memory_disp ... memory displacement (16 bit signed) to be added to Rb
+
+*******************************************************************************/
+
+#define M_MEM(Opcode,Ra,Rb,Memory_disp) \
+ do { \
+ *((uint32_t *) cd->mcodeptr) = ((((Opcode)) << 26) | ((Ra) << 21) | ((Rb) << 16) | ((Memory_disp) & 0xffff)); \
+ cd->mcodeptr += 4; \
+ } while (0)
+
+#define M_MEM_GET_Opcode(x) ( (((x) >> 26) & 0x3f ))
+#define M_MEM_GET_Ra(x) ( (((x) >> 21) & 0x1f ))
+#define M_MEM_GET_Rb(x) ( (((x) >> 16) & 0x1f ))
+#define M_MEM_GET_Memory_disp(x) ((int16_t) ( (x) & 0xffff))
+
+
+/* M_BRA - branch instruction format *******************************************
+
+ Opcode ........ opcode
+ Ra ............ register to be tested
+ Branch_disp ... relative address to be jumped to (divided by 4)
+
+*******************************************************************************/
+
+#define M_BRA(Opcode,Ra,Branch_disp) \
+ do { \
+ *((uint32_t *) cd->mcodeptr) = ((((Opcode)) << 26) | ((Ra) << 21) | ((Branch_disp) & 0x1fffff)); \
+ cd->mcodeptr += 4; \
+ } while (0)
-/* macros to create code ******************************************************/
#define REG 0
#define CONST 1
*/
#define M_OP3(op,fu,a,b,c,const) \
- *(mcodeptr++) = ( (((s4)(op))<<26)|((a)<<21)|((b)<<(16-3*(const)))| \
- ((const)<<12)|((fu)<<5)|((c)) )
+ do { \
+ *((u4 *) cd->mcodeptr) = ((((s4) (op)) << 26) | ((a) << 21) | ((b) << (16 - 3 * (const))) | ((const) << 12) | ((fu) << 5) | ((c))); \
+ cd->mcodeptr += 4; \
+ } while (0)
+
+#define M_OP3_GET_Opcode(x) ( (((x) >> 26) & 0x3f ))
/* 3-address-floating-point-operation: M_FOP3
*/
#define M_FOP3(op,fu,a,b,c) \
- *(mcodeptr++) = ( (((s4)(op))<<26)|((a)<<21)|((b)<<16)|((fu)<<5)|(c) )
-
-
-/* branch instructions: M_BRA
- op ..... opcode
- a ...... register to be tested
- disp ... relative address to be jumped to (divided by 4)
-*/
+ do { \
+ *((u4 *) cd->mcodeptr) = ((((s4) (op)) << 26) | ((a) << 21) | ((b) << 16) | ((fu) << 5) | (c)); \
+ cd->mcodeptr += 4; \
+ } while (0)
-#define M_BRA(op,a,disp) \
- *(mcodeptr++) = ((((s4) (op)) << 26) | ((a) << 21) | ((disp) & 0x1fffff))
+/* macros for all used commands (see an Alpha-manual for description) *********/
-/* memory operations: M_MEM
- op ..... opcode
- a ...... source/target register for memory access
- b ...... base register
- disp ... displacement (16 bit signed) to be added to b
-*/
-
-#define M_MEM(op,a,b,disp) \
- *(mcodeptr++) = ((((s4) (op)) << 26) | ((a) << 21) | ((b) << 16) | ((disp) & 0xffff))
-
+#define M_LDA_INTERN(a,b,disp) M_MEM(0x08,a,b,disp) /* low const */
-/* macros for all used commands (see an Alpha-manual for description) *********/
+#define M_LDA(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_LDA_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(a,b,hi); \
+ M_LDA_INTERN(a,a,lo); \
+ } \
+ } while (0)
-#define M_LDA(a,b,disp) M_MEM (0x08,a,b,disp) /* low const */
#define M_LDAH(a,b,disp) M_MEM (0x09,a,b,disp) /* high const */
+
#define M_BLDU(a,b,disp) M_MEM (0x0a,a,b,disp) /* 8 load */
#define M_SLDU(a,b,disp) M_MEM (0x0c,a,b,disp) /* 16 load */
-#define M_ILD(a,b,disp) M_MEM (0x28,a,b,disp) /* 32 load */
-#define M_LLD(a,b,disp) M_MEM (0x29,a,b,disp) /* 64 load */
-#define M_ALD(a,b,disp) M_MEM (0x29,a,b,disp) /* addr load */
-#define M_BST(a,b,disp) M_MEM (0x0e,a,b,disp) /* 8 store */
-#define M_SST(a,b,disp) M_MEM (0x0d,a,b,disp) /* 16 store */
-#define M_IST(a,b,disp) M_MEM (0x2c,a,b,disp) /* 32 store */
-#define M_LST(a,b,disp) M_MEM (0x2d,a,b,disp) /* 64 store */
-#define M_AST(a,b,disp) M_MEM (0x2d,a,b,disp) /* addr store */
+
+#define M_ILD_INTERN(a,b,disp) M_MEM(0x28,a,b,disp) /* 32 load */
+#define M_LLD_INTERN(a,b,disp) M_MEM(0x29,a,b,disp) /* 64 load */
+
+#define M_ILD(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_ILD_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(a,b,hi); \
+ M_ILD_INTERN(a,a,lo); \
+ } \
+ } while (0)
+
+#define M_LLD(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_LLD_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(a,b,hi); \
+ M_LLD_INTERN(a,a,lo); \
+ } \
+ } while (0)
+
+#define M_ALD_INTERN(a,b,disp) M_LLD_INTERN(a,b,disp)
+#define M_ALD(a,b,disp) M_LLD(a,b,disp) /* addr load */
+#define M_ALD_DSEG(a,disp) M_LLD(a,REG_PV,disp)
+
+#define M_BST(a,b,disp) M_MEM(0x0e,a,b,disp) /* 8 store */
+#define M_SST(a,b,disp) M_MEM(0x0d,a,b,disp) /* 16 store */
+
+#define M_IST_INTERN(a,b,disp) M_MEM(0x2c,a,b,disp) /* 32 store */
+#define M_LST_INTERN(a,b,disp) M_MEM(0x2d,a,b,disp) /* 64 store */
+
+/* Stores with displacement overflow should only happen with PUTFIELD or on */
+/* the stack. The PUTFIELD instruction does not use REG_ITMP3 and a */
+/* reg_of_var call should not use REG_ITMP3!!! */
+
+#define M_IST(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_IST_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(REG_ITMP3,b,hi); \
+ M_IST_INTERN(a,REG_ITMP3,lo); \
+ } \
+ } while (0)
+
+#define M_LST(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_LST_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(REG_ITMP3,b,hi); \
+ M_LST_INTERN(a,REG_ITMP3,lo); \
+ } \
+ } while (0)
+
+#define M_AST(a,b,disp) M_LST(a,b,disp) /* addr store */
#define M_BSEXT(b,c) M_OP3 (0x1c,0x0,REG_ZERO,b,c,0) /* 8 signext */
#define M_SSEXT(b,c) M_OP3 (0x1c,0x1,REG_ZERO,b,c,0) /* 16 signext */
#define M_IMUL_IMM(a,b,c) M_OP3 (0x13,0x00, a,b,c,1) /* 32 mul */
#define M_LMUL_IMM(a,b,c) M_OP3 (0x13,0x20, a,b,c,1) /* 64 mul */
+#define M_AADD_IMM(a,b,c) M_LADD_IMM(a,b,c)
+#define M_ASUB_IMM(a,b,c) M_LSUB_IMM(a,b,c)
+
#define M_CMPEQ(a,b,c) M_OP3 (0x10,0x2d, a,b,c,0) /* c = a == b */
#define M_CMPLT(a,b,c) M_OP3 (0x10,0x4d, a,b,c,0) /* c = a < b */
#define M_CMPLE(a,b,c) M_OP3 (0x10,0x6d, a,b,c,0) /* c = a <= b */
#define M_SRA_IMM(a,b,c) M_OP3 (0x12,0x3c, a,b,c,1) /* c = a >> b */
#define M_SRL_IMM(a,b,c) M_OP3 (0x12,0x34, a,b,c,1) /* c = a >>>b */
-#define M_FLD(a,b,disp) M_MEM (0x22,a,b,disp) /* load flt */
-#define M_DLD(a,b,disp) M_MEM (0x23,a,b,disp) /* load dbl */
-#define M_FST(a,b,disp) M_MEM (0x26,a,b,disp) /* store flt */
-#define M_DST(a,b,disp) M_MEM (0x27,a,b,disp) /* store dbl */
+#define M_FLD_INTERN(a,b,disp) M_MEM(0x22,a,b,disp) /* load flt */
+#define M_DLD_INTERN(a,b,disp) M_MEM(0x23,a,b,disp) /* load dbl */
+
+#define M_FLD(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_FLD_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(REG_ITMP3,b,hi); \
+ M_FLD_INTERN(a,REG_ITMP3,lo); \
+ } \
+ } while (0)
+
+#define M_DLD(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_DLD_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(REG_ITMP3,b,hi); \
+ M_DLD_INTERN(a,REG_ITMP3,lo); \
+ } \
+ } while (0)
+
+#define M_FST_INTERN(a,b,disp) M_MEM(0x26,a,b,disp) /* store flt */
+#define M_DST_INTERN(a,b,disp) M_MEM(0x27,a,b,disp) /* store dbl */
+
+/* Stores with displacement overflow should only happen with PUTFIELD or on */
+/* the stack. The PUTFIELD instruction does not use REG_ITMP3 and a */
+/* reg_of_var call should not use REG_ITMP3!!! */
+
+#define M_FST(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_FST_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(REG_ITMP3,b,hi); \
+ M_FST_INTERN(a,REG_ITMP3,lo); \
+ } \
+ } while (0)
+
+#define M_DST(a,b,disp) \
+ do { \
+ s4 lo = (short) (disp); \
+ s4 hi = (short) (((disp) - lo) >> 16); \
+ if (hi == 0) { \
+ M_DST_INTERN(a,b,lo); \
+ } else { \
+ M_LDAH(REG_ITMP3,b,hi); \
+ M_DST_INTERN(a,REG_ITMP3,lo); \
+ } \
+ } while (0)
+
#define M_FADD(a,b,c) M_FOP3 (0x16, 0x080, a,b,c) /* flt add */
#define M_DADD(a,b,c) M_FOP3 (0x16, 0x0a0, a,b,c) /* dbl add */
#define M_FCMPLTS(a,b,c) M_FOP3 (0x16, 0x5a6, a,b,c) /* c = a<b */
#define M_FMOV(fa,fb) M_FOP3 (0x17, 0x020, fa,fa,fb) /* b = a */
+#define M_DMOV(fa,fb) M_FMOV (fa,fb)
#define M_FMOVN(fa,fb) M_FOP3 (0x17, 0x021, fa,fa,fb) /* b = -a */
#define M_FNOP M_FMOV (31,31)
#define M_FBEQZ(fa,disp) M_BRA (0x31,fa,disp) /* br a == 0.0*/
-/* macros for special commands (see an Alpha-manual for description) **********/
+/* macros for special commands (see an Alpha-manual for description) **********/
#define M_TRAPB M_MEM (0x18,0,0,0x0000) /* trap barrier*/
#define M_CMOVLE_IMM(a,b,c) M_OP3 (0x11,0x64, a,b,c,1) /* a<=0 ? c=b */
#define M_CMOVGT_IMM(a,b,c) M_OP3 (0x11,0x66, a,b,c,1) /* a> 0 ? c=b */
-/* macros for unused commands (see an Alpha-manual for description) ***********/
+// 0x04 seems to be the first undefined instruction which does not
+// call PALcode.
+#define M_UNDEFINED M_OP3(0x04, 0, 0, 0, 0, 0)
+
+/* macros for unused commands (see an Alpha-manual for description) ***********/
#define M_ANDNOT(a,b,c,const) M_OP3 (0x11,0x08, a,b,c,const) /* c = a &~ b */
#define M_ORNOT(a,b,c,const) M_OP3 (0x11,0x28, a,b,c,const) /* c = a |~ b */
#define M_JMP_CO(a,b) M_MEM (0x1a,a,b,0xc000) /* call cosub */
-
-/* function gen_resolvebranch **************************************************
-
- backpatches a branch instruction; Alpha branch instructions are very
- regular, so it is only necessary to overwrite some fixed bits in the
- instruction.
-
- parameters: ip ... pointer to instruction after branch (void*)
- so ... offset of instruction after branch (s4)
- to ... offset of branch target (s4)
-
-*******************************************************************************/
-
-#define gen_resolvebranch(ip,so,to) \
- ((s4 *) (ip))[-1] |= ((s4) (to) - (so)) >> 2 & 0x1fffff
-
-
-/* function prototypes */
-
-void thread_restartcriticalsection(ucontext_t*);
-
#endif /* _CODEGEN_H */
projects / cacao.git / blobdiff