* Updated header: Added 2006. Changed address of FSF. Changed email

[cacao.git] / src / vm / jit / alpha / arch.h

diff --git a/src/vm/jit/alpha/arch.h b/src/vm/jit/alpha/arch.h
index dd9c05e618baa8fefc9008d568e49d593803930e..46e23090d016344279715ae25f59b56640bd1feb 100644 (file)
--- a/src/vm/jit/alpha/arch.h
+++ b/src/vm/jit/alpha/arch.h
@@ -1,9 +1,9 @@
-/* vm/jit/alpha/arch.h - architecture defines for Alpha
+/* src/vm/jit/alpha/arch.h - architecture defines for Alpha
 
-   Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
-   R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
-   C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
-   Institut f. Computersprachen - TU Wien
+   Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
+   C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
+   E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
+   J. Wenninger, Institut f. Computersprachen - TU Wien
 
    This file is part of CACAO.
 
@@ -19,14 +19,16 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301, USA.
 
-   Contact: cacao@complang.tuwien.ac.at
+   Contact: cacao@cacaojvm.org
 
    Authors: Christian Thalinger
 
-   $Id: arch.h 1735 2004-12-07 14:33:27Z twisti $
+   Changes:
+
+   $Id: arch.h 4357 2006-01-22 23:33:38Z twisti $
 
 */
 
@@ -34,84 +36,43 @@
 #ifndef _ARCH_H
 #define _ARCH_H
 
-
-/* preallocated registers *****************************************************/
-
-/* integer registers */
-  
-#define REG_RESULT      0    /* to deliver method results                     */
-
-#define REG_RA          26   /* return address                                */
-#define REG_PV          27   /* procedure vector, must be provided by caller  */
-#define REG_METHODPTR   28   /* pointer to the place from where the procedure */
-                             /* vector has been fetched                       */
-#define REG_ITMP1       25   /* temporary register                            */
-#define REG_ITMP2       28   /* temporary register and method pointer         */
-#define REG_ITMP3       29   /* temporary register                            */
-
-#define REG_ITMP1_XPTR  25   /* exception pointer = temporary register 1      */
-#define REG_ITMP2_XPC   28   /* exception pc = temporary register 2           */
-
-#define REG_SP          30   /* stack pointer                                 */
-#define REG_ZERO        31   /* always zero                                   */
-
-/* floating point registers */
-
-#define REG_FRESULT     0    /* to deliver floating point method results      */
-
-#define REG_FTMP1       28   /* temporary floating point register             */
-#define REG_FTMP2       29   /* temporary floating point register             */
-#define REG_FTMP3       30   /* temporary floating point register             */
-
-#define REG_IFTMP       28   /* temporary integer and floating point register */
-
-
-#define INT_SAV_CNT      7   /* number of int callee saved registers          */
-#define INT_ARG_CNT      6   /* number of int argument registers              */
-
-#define FLT_SAV_CNT      8   /* number of flt callee saved registers          */
-#define FLT_ARG_CNT      6   /* number of flt argument registers              */
-
-
-#define TRACE_ARGS_NUM  6
-
-
 /* define architecture features ***********************************************/
 
-#define POINTERSIZE              8
-#define WORDS_BIGENDIAN          0
-
-#define U8_AVAILABLE             1
-
-#define USE_CODEMMAP             1
-
-#define SUPPORT_DIVISION         0
-#define SUPPORT_LONG             1
-#define SUPPORT_FLOAT            1
-#define SUPPORT_DOUBLE           1
-
-/*  #define SUPPORT_IFCVT            1 */
-/*  #define SUPPORT_FICVT            1 */
-
-#define SUPPORT_LONG_ADD         1
-#define SUPPORT_LONG_CMP         1
-#define SUPPORT_LONG_LOG         1
-#define SUPPORT_LONG_SHIFT       1
-#define SUPPORT_LONG_MUL         1
-#define SUPPORT_LONG_DIV         0
-#define SUPPORT_LONG_ICVT        1
-#define SUPPORT_LONG_FCVT        1
-
-#define SUPPORT_CONST_ASTORE     1      /* do we support const astores        */
-#define SUPPORT_ONLY_ZERO_ASTORE 1      /* on risc machines we can only store */
-                                        /* REG_ZERO                           */
+#define U8_AVAILABLE                     1
 
 /*  #define USEBUILTINTABLE */
 
-#define CONDITIONAL_LOADCONST
-
-/*  #define CONSECUTIVE_INTARGS */
-/*  #define CONSECUTIVE_FLOATARGS */
+#define SUPPORT_DIVISION                 0
+#define SUPPORT_LONG                     1
+#define SUPPORT_FLOAT                    1
+#define SUPPORT_DOUBLE                   1
+
+#define SUPPORT_I2F                      1
+#define SUPPORT_I2D                      1
+#define SUPPORT_L2F                      1
+#define SUPPORT_L2D                      1
+
+#define SUPPORT_F2I                      0
+#define SUPPORT_F2L                      0
+#define SUPPORT_D2I                      0
+#define SUPPORT_D2L                      0
+
+#define SUPPORT_LONG_ADD                 1
+#define SUPPORT_LONG_CMP                 1
+#define SUPPORT_LONG_CMP_CONST           1
+#define SUPPORT_LONG_LOGICAL             1
+#define SUPPORT_LONG_SHIFT               1
+#define SUPPORT_LONG_MUL                 1
+#define SUPPORT_LONG_DIV                 0
+
+#define SUPPORT_CONST_LOGICAL            1  /* AND, OR, XOR with immediates   */
+#define SUPPORT_CONST_MUL                1  /* mutiply with immediate         */
+
+#define SUPPORT_CONST_STORE              1  /* do we support const stores     */
+#define SUPPORT_CONST_STORE_ZERO_ONLY    1  /* on some risc machines we can   */
+                                            /* only store REG_ZERO            */
+
+#define CONDITIONAL_LOADCONST            1
 
 #endif /* _ARCH_H */