#include "util.h" // dprintf
#include "pci.h" // pci_bdf_to_bus
#include "config.h" // CONFIG_*
-#include "ioport.h" // outw
-#include "usb-ohci.h" // USBLEGSUP
-#include "pci_regs.h" // PCI_BASE_ADDRESS_4
+#include "usb-ohci.h" // struct ohci_hcca
+#include "pci_regs.h" // PCI_BASE_ADDRESS_0
#include "usb.h" // struct usb_s
#include "farptr.h" // GET_FLATPTR
-#include "biosvar.h" // GET_GLOBAL
-static void
-reset_ohci(struct usb_s *cntl)
-{
-}
+#define FIT (1 << 31)
-static void
-configure_ohci(struct usb_s *cntl)
+
+/****************************************************************
+ * Setup
+ ****************************************************************/
+
+static int
+start_ohci(struct usb_s *cntl, struct ohci_hcca *hcca)
{
- // XXX - check for SMM control?
+ u32 oldfminterval = readl(&cntl->ohci.regs->fminterval);
+ u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
- writel(&cntl->ohci.regs->intrdisable, OHCI_INTR_MIE);
+ // XXX - check if already running?
- struct ohci_hcca *hcca = memalign_low(256, sizeof(*hcca));
- if (!hcca) {
- dprintf(1, "No ram for ohci init\n");
- return;
+ // Do reset
+ writel(&cntl->ohci.regs->control, OHCI_USB_RESET | oldrwc);
+ readl(&cntl->ohci.regs->control); // flush writes
+ msleep(USB_TIME_DRSTR);
+
+ // Do software init (min 10us, max 2ms)
+ u64 end = calc_future_tsc_usec(10);
+ writel(&cntl->ohci.regs->cmdstatus, OHCI_HCR);
+ for (;;) {
+ u32 status = readl(&cntl->ohci.regs->cmdstatus);
+ if (! status & OHCI_HCR)
+ break;
+ if (check_time(end)) {
+ warn_timeout();
+ return -1;
+ }
}
-
+ // Init memory
+ writel(&cntl->ohci.regs->ed_controlhead, 0);
+ writel(&cntl->ohci.regs->ed_bulkhead, 0);
+ writel(&cntl->ohci.regs->hcca, (u32)hcca);
+
+ // Init fminterval
+ u32 fi = oldfminterval & 0x3fff;
+ writel(&cntl->ohci.regs->fminterval
+ , (((oldfminterval & FIT) ^ FIT)
+ | fi | (((6 * (fi - 210)) / 7) << 16)));
+ writel(&cntl->ohci.regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
+ readl(&cntl->ohci.regs->control); // flush writes
+
+ // XXX - verify that fminterval was setup correctly.
+
+ // Go into operational state
+ writel(&cntl->ohci.regs->control
+ , (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_PLE
+ | OHCI_USB_OPER | oldrwc));
+ readl(&cntl->ohci.regs->control); // flush writes
+
+ return 0;
}
static void
-start_ohci(struct usb_s *cntl)
+stop_ohci(struct usb_s *cntl)
{
+ u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
+ writel(&cntl->ohci.regs->control, oldrwc);
+ readl(&cntl->ohci.regs->control); // flush writes
}
// Find any devices connected to the root hub.
static int
check_ohci_ports(struct usb_s *cntl)
{
+ // Turn on power for all devices on roothub.
+ u32 rha = readl(&cntl->ohci.regs->roothub_a);
+ rha &= ~(RH_A_PSM | RH_A_OCPM);
+ writel(&cntl->ohci.regs->roothub_status, RH_HS_LPSC);
+ writel(&cntl->ohci.regs->roothub_b, RH_B_PPCM);
+ msleep((rha >> 24) * 2);
+ // XXX - need to sleep for USB_TIME_SIGATT if just powered up?
+
+ // Count and reset connected devices
+ int ports = rha & RH_A_NDP;
+ int totalcount = 0;
+ int i;
+ for (i=0; i<ports; i++) {
+ u32 sts = readl(&cntl->ohci.regs->roothub_portstatus[i]);
+ if (!(sts & RH_PS_CCS))
+ continue;
+ // XXX - need to wait for USB_TIME_ATTDB if just powered up?
+ writel(&cntl->ohci.regs->roothub_portstatus[i], RH_PS_PRS);
+ u64 end = calc_future_tsc(USB_TIME_DRSTR * 2);
+ for (;;) {
+ sts = readl(&cntl->ohci.regs->roothub_portstatus[i]);
+ if (!(sts & RH_PS_PRS))
+ // XXX - need to ensure USB_TIME_DRSTR time in reset?
+ break;
+ if (check_time(end)) {
+ // Timeout.
+ warn_timeout();
+ goto shutdown;
+ }
+ yield();
+ }
+
+ if ((sts & (RH_PS_CCS|RH_PS_PES)) != (RH_PS_CCS|RH_PS_PES))
+ // Device no longer present
+ continue;
+
+ msleep(USB_TIME_RSTRCY);
+
+ // XXX - should try to parallelize configuration.
+ int count = configure_usb_device(cntl, !!(sts & RH_PS_LSDA));
+ if (! count)
+ // Shutdown port
+ writel(&cntl->ohci.regs->roothub_portstatus[i]
+ , RH_PS_CCS|RH_PS_LSDA);
+ totalcount += count;
+ }
+ if (!totalcount)
+ // No devices connected
+ goto shutdown;
+ return totalcount;
+
+shutdown:
+ // Turn off power to all ports
+ writel(&cntl->ohci.regs->roothub_status, RH_HS_LPS);
return 0;
}
-int
-ohci_init(struct usb_s *cntl)
+void
+ohci_init(void *data)
{
if (! CONFIG_USB_OHCI)
- return 0;
+ return;
+ struct usb_s *cntl = data;
+ // XXX - don't call pci_config_XXX from a thread
cntl->type = USB_TYPE_OHCI;
u32 baseaddr = pci_config_readl(cntl->bdf, PCI_BASE_ADDRESS_0);
cntl->ohci.regs = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
pci_config_maskw(cntl->bdf, PCI_COMMAND
, 0, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY);
- reset_ohci(cntl);
- configure_ohci(cntl);
- start_ohci(cntl);
+ // XXX - check for and disable SMM control?
+
+ // Disable interrupts
+ writel(&cntl->ohci.regs->intrdisable, ~0);
+ writel(&cntl->ohci.regs->intrstatus, ~0);
+
+ // Allocate memory
+ struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
+ struct ohci_ed *intr_ed = malloc_high(sizeof(*intr_ed));
+ if (!hcca || !intr_ed) {
+ warn_noalloc();
+ goto free;
+ }
+ memset(hcca, 0, sizeof(*hcca));
+ memset(intr_ed, 0, sizeof(*intr_ed));
+ intr_ed->hwINFO = ED_SKIP;
+ int i;
+ for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
+ hcca->int_table[i] = (u32)intr_ed;
+
+ int ret = start_ohci(cntl, hcca);
+ if (ret)
+ goto err;
int count = check_ohci_ports(cntl);
- if (! count) {
- // XXX - no devices; free data structures.
- return 0;
+ free_pipe(cntl->defaultpipe);
+ if (! count)
+ goto err;
+ return;
+
+err:
+ stop_ohci(cntl);
+free:
+ free(hcca);
+ free(intr_ed);
+}
+
+
+/****************************************************************
+ * End point communication
+ ****************************************************************/
+
+static int
+wait_ed(struct ohci_ed *ed)
+{
+ // XXX - 500ms just a guess
+ u64 end = calc_future_tsc(500);
+ for (;;) {
+ if (ed->hwHeadP == ed->hwTailP)
+ return 0;
+ if (check_time(end)) {
+ warn_timeout();
+ return -1;
+ }
+ yield();
}
+}
- return 0;
+// Wait for next USB frame to start - for ensuring safe memory release.
+static void
+ohci_waittick(struct usb_s *cntl)
+{
+ barrier();
+ struct ohci_hcca *hcca = (void*)cntl->ohci.regs->hcca;
+ u32 startframe = hcca->frame_no;
+ u64 end = calc_future_tsc(1000 * 5);
+ for (;;) {
+ if (hcca->frame_no != startframe)
+ break;
+ if (check_time(end)) {
+ warn_timeout();
+ return;
+ }
+ yield();
+ }
+}
+
+static void
+signal_freelist(struct usb_s *cntl)
+{
+ u32 v = readl(&cntl->ohci.regs->control);
+ if (v & OHCI_CTRL_CLE) {
+ writel(&cntl->ohci.regs->control, v & ~(OHCI_CTRL_CLE|OHCI_CTRL_BLE));
+ ohci_waittick(cntl);
+ writel(&cntl->ohci.regs->ed_controlcurrent, 0);
+ writel(&cntl->ohci.regs->ed_bulkcurrent, 0);
+ writel(&cntl->ohci.regs->control, v);
+ } else {
+ ohci_waittick(cntl);
+ }
+}
+
+struct ohci_pipe {
+ struct ohci_ed ed;
+ struct usb_pipe pipe;
+ void *data;
+ int count;
+ struct ohci_td *tds;
+};
+
+void
+ohci_free_pipe(struct usb_pipe *p)
+{
+ if (! CONFIG_USB_OHCI)
+ return;
+ struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
+ u32 endp = pipe->pipe.endp;
+ dprintf(7, "ohci_free_pipe %x\n", endp);
+ struct usb_s *cntl = endp2cntl(endp);
+
+ u32 *pos = &cntl->ohci.regs->ed_controlhead;
+ for (;;) {
+ struct ohci_ed *next = (void*)*pos;
+ if (!next) {
+ // Not found?! Exit without freeing.
+ warn_internalerror();
+ return;
+ }
+ if (next == &pipe->ed) {
+ *pos = next->hwNextED;
+ signal_freelist(cntl);
+ free(pipe);
+ return;
+ }
+ pos = &next->hwNextED;
+ }
+}
+
+struct usb_pipe *
+ohci_alloc_control_pipe(u32 endp)
+{
+ if (! CONFIG_USB_OHCI)
+ return NULL;
+ struct usb_s *cntl = endp2cntl(endp);
+ dprintf(7, "ohci_alloc_control_pipe %x\n", endp);
+
+ // Allocate a queue head.
+ struct ohci_pipe *pipe = malloc_tmphigh(sizeof(*pipe));
+ if (!pipe) {
+ warn_noalloc();
+ return NULL;
+ }
+ memset(pipe, 0, sizeof(*pipe));
+ pipe->ed.hwINFO = ED_SKIP;
+ pipe->pipe.endp = endp;
+
+ // Add queue head to controller list.
+ pipe->ed.hwNextED = cntl->ohci.regs->ed_controlhead;
+ barrier();
+ cntl->ohci.regs->ed_controlhead = (u32)&pipe->ed;
+ return &pipe->pipe;
}
int
-ohci_control(u32 endp, int dir, const void *cmd, int cmdsize
+ohci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
, void *data, int datasize)
{
if (! CONFIG_USB_OHCI)
- return 0;
-
+ return -1;
+ if (datasize > 4096) {
+ // XXX - should support larger sizes.
+ warn_noalloc();
+ return -1;
+ }
+ struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
+ u32 endp = pipe->pipe.endp;
dprintf(5, "ohci_control %x\n", endp);
- return 0;
+ struct usb_s *cntl = endp2cntl(endp);
+ int maxpacket = endp2maxsize(endp);
+ int lowspeed = endp2speed(endp);
+ int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
+
+ // Setup transfer descriptors
+ struct ohci_td *tds = malloc_tmphigh(sizeof(*tds) * 3);
+ tds[0].hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
+ tds[0].hwCBP = (u32)cmd;
+ tds[0].hwNextTD = (u32)&tds[1];
+ tds[0].hwBE = (u32)cmd + cmdsize - 1;
+ tds[1].hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | TD_T_DATA1 | TD_CC;
+ tds[1].hwCBP = datasize ? (u32)data : 0;
+ tds[1].hwNextTD = (u32)&tds[2];
+ tds[1].hwBE = (u32)data + datasize - 1;
+ tds[2].hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
+ tds[2].hwCBP = 0;
+ tds[2].hwNextTD = (u32)&tds[3];
+ tds[2].hwBE = 0;
+
+ // Transfer data
+ pipe->ed.hwINFO = ED_SKIP;
+ barrier();
+ pipe->ed.hwHeadP = (u32)&tds[0];
+ pipe->ed.hwTailP = (u32)&tds[3];
+ barrier();
+ pipe->ed.hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
+ writel(&cntl->ohci.regs->cmdstatus, OHCI_CLF);
+
+ int ret = wait_ed(&pipe->ed);
+ pipe->ed.hwINFO = ED_SKIP;
+ if (ret)
+ ohci_waittick(cntl);
+ free(tds);
+ return ret;
}
struct usb_pipe *
-ohci_alloc_intr_pipe(u32 endp, int period)
+ohci_alloc_intr_pipe(u32 endp, int frameexp)
{
if (! CONFIG_USB_OHCI)
return NULL;
- dprintf(7, "ohci_alloc_intr_pipe %x %d\n", endp, period);
+ dprintf(7, "ohci_alloc_intr_pipe %x %d\n", endp, frameexp);
+ if (frameexp > 5)
+ frameexp = 5;
+ struct usb_s *cntl = endp2cntl(endp);
+ int maxpacket = endp2maxsize(endp);
+ int lowspeed = endp2speed(endp);
+ int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
+ // Determine number of entries needed for 2 timer ticks.
+ int ms = 1<<frameexp;
+ int count = DIV_ROUND_UP(PIT_TICK_INTERVAL * 1000 * 2, PIT_TICK_RATE * ms);
+ struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
+ struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
+ void *data = malloc_low(maxpacket * count);
+ if (!pipe || !tds || !data)
+ goto err;
+
+ struct ohci_ed *ed = &pipe->ed;
+ ed->hwHeadP = (u32)&tds[0];
+ ed->hwTailP = (u32)&tds[count-1];
+ ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
+
+ int i;
+ for (i=0; i<count-1; i++) {
+ tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
+ tds[i].hwCBP = (u32)data + maxpacket * i;
+ tds[i].hwNextTD = (u32)&tds[i+1];
+ tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
+ }
+
+ // Add to interrupt schedule.
+ barrier();
+ struct ohci_hcca *hcca = (void*)cntl->ohci.regs->hcca;
+ if (frameexp == 0) {
+ // Add to existing interrupt entry.
+ struct ohci_ed *intr_ed = (void*)hcca->int_table[0];
+ ed->hwNextED = intr_ed->hwNextED;
+ intr_ed->hwNextED = (u32)ed;
+ } else {
+ int startpos = 1<<(frameexp-1);
+ ed->hwNextED = hcca->int_table[startpos];
+ for (i=startpos; i<ARRAY_SIZE(hcca->int_table); i+=ms)
+ hcca->int_table[i] = (u32)ed;
+ }
+
+ pipe->data = data;
+ pipe->count = count;
+ pipe->tds = tds;
+ pipe->pipe.endp = endp;
+ return &pipe->pipe;
+
+err:
+ free(pipe);
+ free(tds);
+ free(data);
return NULL;
}
int
-ohci_poll_intr(void *pipe, void *data)
+ohci_poll_intr(struct usb_pipe *p, void *data)
{
ASSERT16();
if (! CONFIG_USB_OHCI)
return -1;
- return -1;
+
+ struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
+ struct ohci_td *tds = GET_FLATPTR(pipe->tds);
+ struct ohci_td *head = (void*)GET_FLATPTR(pipe->ed.hwHeadP);
+ struct ohci_td *tail = (void*)GET_FLATPTR(pipe->ed.hwTailP);
+ int count = GET_FLATPTR(pipe->count);
+ int pos = (tail - tds + 1) % count;
+ struct ohci_td *next = &tds[pos];
+ if (head == next)
+ // No intrs found.
+ return -1;
+ // XXX - check for errors.
+
+ // Copy data.
+ u32 endp = GET_FLATPTR(pipe->pipe.endp);
+ int maxpacket = endp2maxsize(endp);
+ void *pipedata = GET_FLATPTR(pipe->data);
+ void *intrdata = pipedata + maxpacket * pos;
+ memcpy_far(GET_SEG(SS), data
+ , FLATPTR_TO_SEG(intrdata), (void*)FLATPTR_TO_OFFSET(intrdata)
+ , maxpacket);
+
+ // Reenable this td.
+ SET_FLATPTR(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
+ intrdata = pipedata + maxpacket * (tail-tds);
+ SET_FLATPTR(tail->hwCBP, (u32)intrdata);
+ SET_FLATPTR(tail->hwNextTD, (u32)next);
+ SET_FLATPTR(tail->hwBE, (u32)intrdata + maxpacket - 1);
+
+ SET_FLATPTR(pipe->ed.hwTailP, (u32)next);
+
+ return 0;
}
projects / seabios.git / blobdiff