C and other Super I/O cosmetic fixes.

[coreboot.git] / src / superio / winbond / w83627uhg / superio.c

diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c
index 57c74b614da74eea719f900d7d0b26f857753f91..a132446352772bded53c32d30179278cd5a94cf4 100644 (file)
--- a/src/superio/winbond/w83627uhg/superio.c
+++ b/src/superio/winbond/w83627uhg/superio.c
@@ -72,13 +72,12 @@ static void set_uart_clock_source(device_t dev, u8 uart_clock)
 
 static void w83627uhg_init(device_t dev)
 {
-       struct superio_winbond_w83627uhg_config *conf;
-       struct resource *res0, *res1;
+       struct superio_winbond_w83627uhg_config *conf = dev->chip_info;
+       struct resource *res0;
 
        if (!dev->enabled)
                return;
 
-       conf = dev->chip_info;
        switch(dev->path.pnp.device) {
        case W83627UHG_SP1:
                res0 = find_resource(dev, PNP_IDX_IO0);
@@ -111,8 +110,6 @@ static void w83627uhg_init(device_t dev)
                init_uart8250(res0->base, &conf->com6);
                break;
        case W83627UHG_KBC:
-               res0 = find_resource(dev, PNP_IDX_IO0);
-               res1 = find_resource(dev, PNP_IDX_IO1);
                pc_keyboard_init(&conf->keyboard);
                break;
        }
@@ -148,21 +145,21 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-       { &ops, W83627UHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-       { &ops, W83627UHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-       { &ops, W83627UHG_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, W83627UHG_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, W83627UHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
-       { &ops, W83627UHG_SP3,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+       { &ops, W83627UHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, W83627UHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, W83627UHG_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, W83627UHG_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, W83627UHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+       { &ops, W83627UHG_SP3,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
        { &ops, W83627UHG_GPIO3_4, },
        { &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
-       { &ops, W83627UHG_GPIO1_2,},
-       { &ops, W83627UHG_ACPI, PNP_IRQ0,  },
-       { &ops, W83627UHG_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
-       { &ops, W83627UHG_PECI_SST,},
-       { &ops, W83627UHG_SP4,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, W83627UHG_SP5,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, W83627UHG_SP6,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+       { &ops, W83627UHG_GPIO1_2, },
+       { &ops, W83627UHG_ACPI, PNP_IRQ0, },
+       { &ops, W83627UHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+       { &ops, W83627UHG_PECI_SST, },
+       { &ops, W83627UHG_SP4,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, W83627UHG_SP5,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, W83627UHG_SP6,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 };
 
 static void enable_dev(device_t dev)