C and other Super I/O cosmetic fixes.

[coreboot.git] / src / superio / winbond / w83627thf / superio.c

diff --git a/src/superio/winbond/w83627thf/superio.c b/src/superio/winbond/w83627thf/superio.c
index 021937e9886dcb142bbe86521dd99fdace259ec3..602ed1b7e558f296cc25c8c53e0714c9a010f7c9 100644 (file)
--- a/src/superio/winbond/w83627thf/superio.c
+++ b/src/superio/winbond/w83627thf/superio.c
@@ -46,7 +46,7 @@ static void w83627thf_exit_ext_func_mode(device_t dev)
 static void w83627thf_init(device_t dev)
 {
        struct superio_winbond_w83627thf_config *conf = dev->chip_info;
-       struct resource *res0, *res1;
+       struct resource *res0;
 
        if (!dev->enabled)
                return;
@@ -61,8 +61,6 @@ static void w83627thf_init(device_t dev)
                init_uart8250(res0->base, &conf->com2);
                break;
        case W83627THF_KBC:
-               res0 = find_resource(dev, PNP_IDX_IO0);
-               res1 = find_resource(dev, PNP_IDX_IO1);
                pc_keyboard_init(&conf->keyboard);
                break;
        }
@@ -98,17 +96,17 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-       { &ops, W83627THF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-       { &ops, W83627THF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-       { &ops, W83627THF_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, W83627THF_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, W83627THF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
-       { &ops, W83627THF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, W83627THF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
-       /* { W83627THF_GPIO2,}, */
-       /* { W83627THF_GPIO3,}, */
-       { &ops, W83627THF_ACPI, PNP_IRQ0,  },
-       { &ops, W83627THF_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
+       { &ops, W83627THF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, W83627THF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, W83627THF_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, W83627THF_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, W83627THF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+       { &ops, W83627THF_CIR,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, W83627THF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
+       /* { W83627THF_GPIO2, }, */
+       /* { W83627THF_GPIO3, }, */
+       { &ops, W83627THF_ACPI, PNP_IRQ0, },
+       { &ops, W83627THF_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
 };
 
 static void enable_dev(device_t dev)