-/* Copyright 2000 AG Electronics Ltd. */
-/* Copyright 2003-2004 Linux Networx */
-/* Copyright 2004 Tyan
- By LYH change from PC87360 */
-/* This code is distributed without warranty under the GPL v2 (see COPYING) */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
#include <arch/io.h>
#include <device/device.h>
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
+#include <pc80/mc146818rtc.h>
+#include <stdlib.h>
#include "chip.h"
#include "w83627hf.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(device_t dev)
{
- outb(0x87, dev->path.u.pnp.port);
- outb(0x87, dev->path.u.pnp.port);
+ outb(0x87, dev->path.pnp.port);
+ outb(0x87, dev->path.pnp.port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+
+static void pnp_exit_ext_func_mode(device_t dev)
{
- outb(0xaa, dev->path.u.pnp.port);
+ outb(0xaa, dev->path.pnp.port);
}
-static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
+static void pnp_write_index(u16 port, u8 reg, u8 value)
{
- outb(reg, port_base);
- outb(value, port_base + 1);
+ outb(reg, port);
+ outb(value, port + 1);
}
-static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
+static u8 pnp_read_index(u16 port, u8 reg)
{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-static void enable_hwm_smbus(device_t dev) {
- /* set the pin 91,92 as I2C bus */
- uint8_t reg, value;
- reg = 0x2b;
- value = pnp_read_config(dev, reg);
- value &= 0x3f;
- pnp_write_config(dev, reg, value);
+ outb(reg, port);
+ return inb(port + 1);
}
-#if 0
-static void dump_pnp_device(device_t dev)
+#if CONFIG_EXPERT
+static void w83627hf_16_bit_addr_qual(device_t dev)
{
- int i;
- print_debug("\r\n");
-
- for(i = 0; i <= 255; i++) {
- uint8_t reg, val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
- reg = i;
- if(i!=0xaa) {
- val = pnp_read_config(dev, reg);
- }
- else {
- val = 0xaa;
- }
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
- }
- }
+ u8 reg8;
+
+ /* Enable 16 bit address qualification. */
+ pnp_enter_ext_func_mode(dev);
+ reg8 = pnp_read_config(dev, 0x24);
+ reg8 |= (1 << 7);
+ pnp_write_config(dev, 0x24, reg8);
+ pnp_exit_ext_func_mode(dev);
}
#endif
-static void init_hwm(unsigned long base)
+static void enable_hwm_smbus(device_t dev)
+{
+ u8 reg8;
+
+ /* Configure pins 91/92 as SDA/SCL (I2C bus). */
+ reg8 = pnp_read_config(dev, 0x2b);
+ reg8 &= 0x3f;
+ pnp_write_config(dev, 0x2b, reg8);
+}
+
+static void init_acpi(device_t dev)
+{
+ u8 value = 0x20; /* FIXME: The 0x20 value here is never used? */
+ int power_on = 1;
+
+ get_option(&power_on, "power_on_after_fail");
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ value = pnp_read_config(dev, 0xE4);
+ value &= ~(3 << 5);
+ if (power_on)
+ value |= (1 << 5);
+ pnp_write_config(dev, 0xE4, value);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void init_hwm(u16 base)
{
- uint8_t reg, value;
+ u8 reg, value;
int i;
- unsigned hwm_reg_values[] = {
-/* reg mask data */
- 0x40, 0xff, 0x81, /* start HWM */
- 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
- 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
- 0x4e, 0x80, 0x00,
- 0x43, 0x00, 0xff,
- 0x44, 0x00, 0x3f,
- 0x4c, 0xbf, 0x18,
- 0x4d, 0xff, 0x80 /* turn off beep */
-
+ u8 hwm_reg_values[] = {
+ /* reg mask data */
+ 0x40, 0xff, 0x81, /* Start HWM. */
+ 0x48, 0xaa, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
+ 0x4a, 0x21, 0x21, /* Set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1. */
+ 0x4e, 0x80, 0x00,
+ 0x43, 0x00, 0xff,
+ 0x44, 0x00, 0x3f,
+ 0x4c, 0xbf, 0x18,
+ 0x4d, 0xff, 0x80, /* Turn off beep */
};
- for(i = 0; i< sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i+=3 ) {
- reg = hwm_reg_values[i];
- value = pnp_read_index(base, reg);
- value &= 0xff & hwm_reg_values[i+1];
- value |= 0xff & hwm_reg_values[i+2];
-#if 0
- printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
-#endif
+ for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
+ reg = hwm_reg_values[i];
+ value = pnp_read_index(base, reg);
+ value &= 0xff & hwm_reg_values[i + 1];
+ value |= 0xff & hwm_reg_values[i + 2];
+ printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
+ "value = 0x%02x\n", base, reg, value);
pnp_write_index(base, reg, value);
}
}
-
static void w83627hf_init(device_t dev)
{
- struct superio_winbond_w83627hf_config *conf;
- struct resource *res0, *res1;
- if (!dev->enabled) {
+ struct superio_winbond_w83627hf_config *conf = dev->chip_info;
+ struct resource *res0;
+
+ if (!dev->enabled)
return;
- }
- conf = dev->chip_info;
- switch(dev->path.u.pnp.device) {
- case W83627HF_SP1:
+
+ switch(dev->path.pnp.device) {
+ case W83627HF_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
init_uart8250(res0->base, &conf->com2);
break;
case W83627HF_KBC:
- res0 = find_resource(dev, PNP_IDX_IO0);
- res1 = find_resource(dev, PNP_IDX_IO1);
- init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+ pc_keyboard_init(&conf->keyboard);
break;
- case W83627HF_HWM:
- res0 = find_resource(dev, PNP_IDX_IO0);
+ case W83627HF_HWM:
+ res0 = find_resource(dev, PNP_IDX_IO0);
#define HWM_INDEX_PORT 5
- init_hwm(res0->base + HWM_INDEX_PORT);
- break;
+ init_hwm(res0->base + HWM_INDEX_PORT);
+ break;
+ case W83627HF_ACPI:
+ init_acpi(dev);
+ break;
}
-
}
-void w83627hf_pnp_set_resources(device_t dev)
+static void w83627hf_pnp_set_resources(device_t dev)
{
-
- pnp_enter_ext_func_mode(dev);
-
+ pnp_enter_ext_func_mode(dev);
pnp_set_resources(dev);
+ pnp_exit_ext_func_mode(dev);
+}
-#if 0
- dump_pnp_device(dev);
-#endif
-
- pnp_exit_ext_func_mode(dev);
-
-}
-
-void w83627hf_pnp_enable_resources(device_t dev)
-{
- pnp_enter_ext_func_mode(dev);
-
- pnp_enable_resources(dev);
-
- switch(dev->path.u.pnp.device) {
+static void w83627hf_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_enable_resources(dev);
+ switch(dev->path.pnp.device) {
case W83627HF_HWM:
- printk_debug("w83627hf hwm smbus enabled\r\n");
+ printk(BIOS_DEBUG, "W83627HF HWM SMBus enabled\n");
enable_hwm_smbus(dev);
break;
}
-
-#if 0
- dump_pnp_device(dev);
-#endif
-
- pnp_exit_ext_func_mode(dev);
-
+ pnp_exit_ext_func_mode(dev);
}
-void w83627hf_pnp_enable(device_t dev)
+static void w83627hf_pnp_enable(device_t dev)
{
+ if (dev->enabled)
+ return;
- if (!dev->enabled) {
- pnp_enter_ext_func_mode(dev);
-
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
-
- pnp_exit_ext_func_mode(dev);
- }
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_exit_ext_func_mode(dev);
}
static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- // No 4 { 0,},
- { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
- { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
- { &ops, W83627HF_GPIO2, },
- { &ops, W83627HF_GPIO3, },
- { &ops, W83627HF_ACPI, },
- { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+ { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+ { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
+ { &ops, W83627HF_GPIO2, },
+ { &ops, W83627HF_GPIO3, },
+ { &ops, W83627HF_ACPI, },
+ { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
};
static void enable_dev(struct device *dev)
{
- pnp_enable_devices(dev, &pnp_ops,
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_winbond_w83627hf_ops = {
- CHIP_NAME("Winbond w83627hf")
+ CHIP_NAME("Winbond W83627HF Super I/O")
.enable_dev = enable_dev,
};
-
projects / coreboot.git / blobdiff