C and other Super I/O cosmetic fixes.

[coreboot.git] / src / superio / winbond / w83627dhg / superio.c

diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c
index 7ed236775958f3a8a1cd5a195cc284a31e14070f..bc19297ea63f72f6fe6eb1a883801ad0d76178c7 100644 (file)
--- a/src/superio/winbond/w83627dhg/superio.c
+++ b/src/superio/winbond/w83627dhg/superio.c
@@ -40,7 +40,7 @@ static void pnp_exit_ext_func_mode(device_t dev)
 static void w83627dhg_init(device_t dev)
 {
        struct superio_winbond_w83627dhg_config *conf = dev->chip_info;
-       struct resource *res0, *res1;
+       struct resource *res0;
 
        if (!dev->enabled)
                return;
@@ -55,8 +55,6 @@ static void w83627dhg_init(device_t dev)
                init_uart8250(res0->base, &conf->com2);
                break;
        case W83627DHG_KBC:
-               res0 = find_resource(dev, PNP_IDX_IO0);
-               res1 = find_resource(dev, PNP_IDX_IO1);
                pc_keyboard_init(&conf->keyboard);
                break;
        }
@@ -96,18 +94,18 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-       { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x0ff8, 0}, },
-       { &ops, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x0ff8, 0}, },
-       { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
-       { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
-       { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0xfff, 0 }, { 0xfff, 0x4}, },
+       { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
+       { &ops, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
+       { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+       { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+       { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, },
        /* the next line makes coreboot hang in pnp_enable_devices() */
        /* { &ops, W83627DHG_SPI, PNP_IO1, { 0xff8, 0 }, }, */
        { &ops, W83627DHG_GPIO6, },
        { &ops, W83627DHG_WDTO_PLED, },
        { &ops, W83627DHG_GPIO2345, },
        { &ops, W83627DHG_ACPI, },
-       { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xffe, 0 }, },
+       { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, },
        { &ops, W83627DHG_PECI_SST, },
 };