#include "chip.h"
/* The following Super I/O chips are currently supported by this driver: */
+#define LPC47M172 0x14
#define FDC37B80X 0x42 /* Same ID: FDC37M70X (a.k.a. FDC37M707) */
#define FDC37B78X 0x44
#define FDC37B72X 0x4c
#define FDC37M81X 0x4d
#define FDC37M60X 0x47
#define LPC47B27X 0x51 /* a.k.a. LPC47B272 */
+#define LPC47U33X 0x54
#define LPC47M10X 0x59 /* Same ID: LPC47M112, LPC47M13X */
#define LPC47M15X 0x60 /* Same ID: LPC47M192 */
#define LPC47S45X 0x62
#define DME1737 0x78
#define SCH3112 0x7c
#define SCH5307 0x81 /* Rebranded LPC47B397(?) */
+#define SCH5027D 0x89
+#define SCH4304 0x90 /* SCH4304, SCH4307 */
/* Register defines */
#define DEVICE_ID_REG 0x20 /* Device ID register */
#define DEVICE_REV_REG 0x21 /* Device revision register */
+#define DEVICE_TEST7_REG 0x29 /* Device test 7 register */
/* Static variables for the Super I/O device ID and revision. */
static int first_time = 1;
uint8_t superio_id;
int devs[MAX_LOGICAL_DEVICES];
} logical_device_table[] = {
- // Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB
+ /* Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB */
+ {LPC47M172,{0, 3, 4, 2, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
{FDC37B80X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}},
{FDC37B78X,{0, 3, 4, 5, 6, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}},
{FDC37B72X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}},
{LPC47M15X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}},
{LPC47S45X,{0, 3, 4, 5, 6, 7, -1, 8, -1, -1, -1, -1, 10, -1, 11}},
{LPC47B397,{0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}},
+ {LPC47U33X,{0, 3, 4, -1, -1, 7, -1, -1, -1, 9, 0, 5, 10, 0, 11}},
{A8000, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
{DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
{SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
{SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}},
+ {SCH5027D, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, 11}},
+ {SCH4304, {0, 3, 4, 5, -1, 7, -1, 11, -1, -1, -1, -1, 10, -1, -1}},
};
/**
static void smsc_init(device_t dev)
{
struct superio_smsc_smscsuperio_config *conf = dev->chip_info;
- struct resource *res0, *res1;
+ struct resource *res0;
int i, ld;
/* Do not initialize disabled devices. */
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
} else if (ld == logical_device_table[i].devs[LD_KBC]) {
- res0 = find_resource(dev, PNP_IDX_IO0);
- res1 = find_resource(dev, PNP_IDX_IO1);
- init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+ pc_keyboard_init(&conf->keyboard);
}
}
{
int i, j, fn;
int tmp[MAX_LOGICAL_DEVICES];
+ uint8_t test7;
if (first_time) {
/* Read the device ID and revision of the Super I/O chip. */
/* TODO: Error handling? */
- printk_info("Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
+ printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
superio_id, superio_rev);
first_time = 0;
+
+ if(superio_id == LPC47M172) {
+ /* Do not use the default logical device number
+ * but instead the standard smsc registers set
+ */
+
+ /* TEST7 configuration register (0x29)
+ * bit 0 : LD_NUM (0 = new, 1 = std smsc)
+ */
+ test7 = pnp_read_config(dev, DEVICE_TEST7_REG);
+ test7 |= 1;
+ pnp_write_config(dev, DEVICE_TEST7_REG, test7);
+ }
}
/* Find the correct Super I/O. */
/* Enable the specified devices (if present on the chip). */
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
- &pnp_dev_info);
+ &pnp_dev_info[0]);
/* Restore LD_FOO values. */
for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)