-/*\r
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/superio.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $\r
- *\r
- * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip\r
- *\r
- * Based on LinuxBIOS code for SMSC 47B397:\r
- * Copyright 2000 AG Electronics Ltd.\r
- * Copyright 2003-2004 Linux Networx\r
- * Copyright 2004 Tyan \r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log: superio.c,v $\r
- * Revision 1.1.1.1 2005/07/11 15:28:51 smagnani\r
- * Initial revision.\r
- *\r
- *\r
- */\r
-\r
-#include <arch/io.h>\r
-#include <device/device.h>\r
-#include <device/pnp.h>\r
-#include <console/console.h>\r
-#include <device/smbus.h>\r
-#include <string.h>\r
-#include <bitops.h>\r
-#include <uart8250.h>\r
-#include <assert.h>\r
-#include "chip.h"\r
-#include "lpc47n217.h"\r
-\r
-// Forward declarations\r
-static void enable_dev(device_t dev);\r
-void lpc47n217_pnp_set_resources(device_t dev);\r
-void lpc47n217_pnp_enable_resources(device_t dev);\r
-void lpc47n217_pnp_enable(device_t dev);\r
-static void lpc47n217_init(device_t dev);\r
-\r
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);\r
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);\r
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);\r
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);\r
-void lpc47n217_pnp_set_enable(device_t dev, int enable);\r
-\r
-static void pnp_enter_conf_state(device_t dev);\r
-static void pnp_exit_conf_state(device_t dev);\r
-\r
-\r
-struct chip_operations superio_smsc_lpc47n217_ops = {\r
- CHIP_NAME("smsc lpc47n217")\r
- .enable_dev = enable_dev,\r
-};\r
-\r
-static struct device_operations ops = {\r
- .read_resources = pnp_read_resources,\r
- .set_resources = lpc47n217_pnp_set_resources,\r
- .enable_resources = lpc47n217_pnp_enable_resources,\r
- .enable = lpc47n217_pnp_enable,\r
- .init = lpc47n217_init,\r
-};\r
-\r
-static struct pnp_info pnp_dev_info[] = {\r
- { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },\r
- { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },\r
- { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }\r
-};\r
-\r
-/**********************************************************************************/\r
-/* PUBLIC INTERFACE */\r
-/**********************************************************************************/\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: enable_dev\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Create device structures and allocate resources to devices \r
-// specified in the pnp_dev_info array (above).\r
-//\r
-static void enable_dev(device_t dev)\r
-{\r
- pnp_enable_devices(dev, &pnp_ops, \r
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), \r
- pnp_dev_info);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_pnp_set_resources\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Configure the specified Super I/O device with the resources\r
-// (I/O space, etc.) that have been allocate for it.\r
-//\r
-void lpc47n217_pnp_set_resources(device_t dev)\r
-{\r
- int i;\r
- \r
- pnp_enter_conf_state(dev); \r
-\r
- // NOTE: Cannot use pnp_set_resources() here because it assumes chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
- for(i = 0; i < dev->resources; i++)\r
- lpc47n217_pnp_set_resource(dev, &dev->resource[i]);\r
-\r
-// dump_pnp_device(dev);\r
- \r
- pnp_exit_conf_state(dev); \r
-} \r
-\r
-void lpc47n217_pnp_enable_resources(device_t dev)\r
-{ \r
- pnp_enter_conf_state(dev);\r
-\r
- // NOTE: Cannot use pnp_enable_resources() here because it assumes chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
- lpc47n217_pnp_set_enable(dev, 1);\r
-\r
- pnp_exit_conf_state(dev);\r
-}\r
-\r
-void lpc47n217_pnp_enable(device_t dev)\r
-{\r
- pnp_enter_conf_state(dev); \r
-\r
- // NOTE: Cannot use pnp_set_enable() here because it assumes chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
-\r
- if(dev->enabled) {\r
- lpc47n217_pnp_set_enable(dev, 1);\r
- }\r
- else {\r
- lpc47n217_pnp_set_enable(dev, 0);\r
- }\r
-\r
- pnp_exit_conf_state(dev); \r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_init\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Initialize the specified Super I/O device.\r
-// Devices other than COM ports are ignored.\r
-// For COM ports, we configure the baud rate. \r
-//\r
-static void lpc47n217_init(device_t dev)\r
-{\r
- struct superio_smsc_lpc47n217_config* conf = dev->chip_info;\r
- struct resource *res0;\r
-\r
- if (!dev->enabled)\r
- return;\r
-\r
- switch(dev->path.u.pnp.device) {\r
- case LPC47N217_SP1: \r
- res0 = find_resource(dev, PNP_IDX_IO0);\r
- init_uart8250(res0->base, &conf->com1);\r
- break;\r
-\r
- case LPC47N217_SP2:\r
- res0 = find_resource(dev, PNP_IDX_IO0);\r
- init_uart8250(res0->base, &conf->com2);\r
- break;\r
- }\r
-}\r
-\r
-\r
-/**********************************************************************************/\r
-/* PRIVATE FUNCTIONS */\r
-/**********************************************************************************/\r
-\r
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)\r
-{\r
- if (!(resource->flags & IORESOURCE_ASSIGNED)) {\r
- printk_err("ERROR: %s %02x not allocated\n",\r
- dev_path(dev), resource->index);\r
- return;\r
- }\r
-\r
- /* Now store the resource */\r
- // NOTE: Cannot use pnp_set_XXX() here because they assume chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
-\r
- if (resource->flags & IORESOURCE_IO) {\r
- lpc47n217_pnp_set_iobase(dev, resource->base);\r
- }\r
- else if (resource->flags & IORESOURCE_DRQ) {\r
- lpc47n217_pnp_set_drq(dev, resource->base);\r
- }\r
- else if (resource->flags & IORESOURCE_IRQ) {\r
- lpc47n217_pnp_set_irq(dev, resource->base);\r
- }\r
- else {\r
- printk_err("ERROR: %s %02x unknown resource type\n",\r
- dev_path(dev), resource->index);\r
- return;\r
- }\r
- resource->flags |= IORESOURCE_STORED;\r
-\r
- report_resource_stored(dev, resource, "");\r
-}\r
-\r
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)\r
-{\r
- ASSERT(!(iobase & 0x3));\r
- \r
- switch(dev->path.u.pnp.device) {\r
- case LPC47N217_PP: \r
- pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- default:\r
- BUG();\r
- break;\r
- }\r
-}\r
-\r
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)\r
-{\r
- if (dev->path.u.pnp.device == LPC47N217_PP) {\r
- const uint8_t PP_DMA_MASK = 0x0F;\r
- const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;\r
- uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);\r
- uint8_t new_config;\r
-\r
- ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range?? \r
- new_config = (current_config & ~PP_DMA_MASK) | drq;\r
- pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);\r
- } else {\r
- BUG();\r
- }\r
-}\r
-\r
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)\r
-{\r
- uint8_t irq_config_register = 0;\r
- uint8_t irq_config_mask = 0;\r
- uint8_t current_config;\r
- uint8_t new_config;\r
- \r
- switch(dev->path.u.pnp.device) {\r
- case LPC47N217_PP: \r
- irq_config_register = 0x27;\r
- irq_config_mask = 0x0F;\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- irq_config_register = 0x28;\r
- irq_config_mask = 0xF0;\r
- irq <<= 4;\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- irq_config_register = 0x28;\r
- irq_config_mask = 0x0F;\r
- break;\r
- \r
- default:\r
- BUG();\r
- return;\r
- }\r
-\r
- ASSERT(!(irq & ~irq_config_mask)); // IRQ out of range??\r
- \r
- current_config = pnp_read_config(dev, irq_config_register);\r
- new_config = (current_config & ~irq_config_mask) | irq;\r
- pnp_write_config(dev, irq_config_register, new_config);\r
-}\r
-\r
-void lpc47n217_pnp_set_enable(device_t dev, int enable)\r
-{\r
- uint8_t power_register = 0;\r
- uint8_t power_mask = 0;\r
- uint8_t current_power;\r
- uint8_t new_power;\r
- \r
- switch(dev->path.u.pnp.device) {\r
- case LPC47N217_PP: \r
- power_register = 0x01;\r
- power_mask = 0x04;\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- power_register = 0x02;\r
- power_mask = 0x08;\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- power_register = 0x02;\r
- power_mask = 0x80;\r
- break;\r
- \r
- default:\r
- BUG();\r
- return;\r
- }\r
-\r
- current_power = pnp_read_config(dev, power_register);\r
- new_power = current_power & ~power_mask; // disable by default\r
-\r
- if (enable) {\r
- struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);\r
- lpc47n217_pnp_set_iobase(dev, ioport_resource->base);\r
- \r
- new_power |= power_mask; // Enable\r
- \r
- } else {\r
- lpc47n217_pnp_set_iobase(dev, 0);\r
- }\r
- pnp_write_config(dev, power_register, new_power);\r
-}\r
-\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: pnp_enter_conf_state\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Enable access to the LPC47N217's configuration registers.\r
-//\r
-static void pnp_enter_conf_state(device_t dev) \r
-{\r
- outb(0x55, dev->path.u.pnp.port);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: pnp_exit_conf_state\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Disable access to the LPC47N217's configuration registers.\r
-//\r
-static void pnp_exit_conf_state(device_t dev) \r
-{\r
- outb(0xaa, dev->path.u.pnp.port);\r
-}\r
-\r
-#if 0\r
-//----------------------------------------------------------------------------------\r
-// Function: dump_pnp_device\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Print the values of all of the LPC47N217's configuration registers.\r
-// NOTE: The LPC47N217 must be in configuration mode when this\r
-// function is called.\r
-//\r
-static void dump_pnp_device(device_t dev)\r
-{\r
- int register_index;\r
- print_debug("\r\n");\r
-\r
- for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {\r
- uint8_t register_value;\r
-\r
- if ((register_index & 0x0f) == 0) {\r
- print_debug_hex8(register_index);\r
- print_debug_char(':');\r
- }\r
-\r
- // Skip over 'register' that would cause exit from configuration mode\r
- if (register_index == 0xaa)\r
- register_value = 0xaa;\r
- else\r
- register_value = pnp_read_config(dev, register_index);\r
-\r
- print_debug_char(' ');\r
- print_debug_hex8(register_value);\r
- if ((register_index & 0x0f) == 0x0f) {\r
- print_debug("\r\n");\r
- }\r
- }\r
-\r
- print_debug("\r\n");\r
-}\r
-#endif\r
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* RAM-based driver for SMSC LPC47N217 Super I/O chip. */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <assert.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "lpc47n217.h"
+
+/* Forward declarations */
+static void enable_dev(device_t dev);
+static void lpc47n217_pnp_set_resources(device_t dev);
+static void lpc47n217_pnp_enable_resources(device_t dev);
+static void lpc47n217_pnp_enable(device_t dev);
+static void lpc47n217_init(device_t dev);
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
+static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase);
+static void lpc47n217_pnp_set_drq(device_t dev, u8 drq);
+static void lpc47n217_pnp_set_irq(device_t dev, u8 irq);
+static void lpc47n217_pnp_set_enable(device_t dev, int enable);
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+struct chip_operations superio_smsc_lpc47n217_ops = {
+ CHIP_NAME("SMSC LPC47N217 Super I/O")
+ .enable_dev = enable_dev,
+};
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = lpc47n217_pnp_set_resources,
+ .enable_resources = lpc47n217_pnp_enable_resources,
+ .enable = lpc47n217_pnp_enable,
+ .init = lpc47n217_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }
+};
+
+/**
+ * Create device structures and allocate resources to devices specified in the
+ * pnp_dev_info array (above).
+ *
+ * @param dev Pointer to structure describing a Super I/O device.
+ */
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
+ pnp_dev_info);
+}
+
+/**
+ * Configure the specified Super I/O device with the resources (I/O space,
+ * etc.) that have been allocate for it.
+ *
+ * NOTE: Cannot use pnp_set_resources() here because it assumes chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ *
+ * @param dev Pointer to structure describing a Super I/O device.
+ */
+static void lpc47n217_pnp_set_resources(device_t dev)
+{
+ struct resource *res;
+
+ pnp_enter_conf_state(dev);
+ for (res = dev->resource_list; res; res = res->next)
+ lpc47n217_pnp_set_resource(dev, res);
+ /* dump_pnp_device(dev); */
+ pnp_exit_conf_state(dev);
+}
+
+/*
+ * NOTE: Cannot use pnp_enable_resources() here because it assumes chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ */
+static void lpc47n217_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ lpc47n217_pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+
+/*
+ * NOTE: Cannot use pnp_set_enable() here because it assumes chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ */
+static void lpc47n217_pnp_enable(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ lpc47n217_pnp_set_enable(dev, !!dev->enabled);
+ pnp_exit_conf_state(dev);
+}
+
+/**
+ * Initialize the specified Super I/O device.
+ *
+ * Devices other than COM ports are ignored. For COM ports, we configure the
+ * baud rate.
+ *
+ * @param dev Pointer to structure describing a Super I/O device.
+ */
+static void lpc47n217_init(device_t dev)
+{
+ struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
+ struct resource *res0;
+
+ if (!dev->enabled)
+ return;
+
+ switch(dev->path.pnp.device) {
+ case LPC47N217_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
+ break;
+ case LPC47N217_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
+ break;
+ }
+}
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
+{
+ if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+ printk(BIOS_ERR, "ERROR: %s %02x not allocated\n",
+ dev_path(dev), resource->index);
+ return;
+ }
+
+ /* Now store the resource. */
+
+ /*
+ * NOTE: Cannot use pnp_set_XXX() here because they assume chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ */
+ if (resource->flags & IORESOURCE_IO) {
+ lpc47n217_pnp_set_iobase(dev, resource->base);
+ } else if (resource->flags & IORESOURCE_DRQ) {
+ lpc47n217_pnp_set_drq(dev, resource->base);
+ } else if (resource->flags & IORESOURCE_IRQ) {
+ lpc47n217_pnp_set_irq(dev, resource->base);
+ } else {
+ printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n",
+ dev_path(dev), resource->index);
+ return;
+ }
+ resource->flags |= IORESOURCE_STORED;
+
+ report_resource_stored(dev, resource, "");
+}
+
+static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
+{
+ ASSERT(!(iobase & 0x3));
+
+ switch(dev->path.pnp.device) {
+ case LPC47N217_PP:
+ pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+ break;
+ case LPC47N217_SP1:
+ pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+ break;
+ case LPC47N217_SP2:
+ pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+ break;
+ default:
+ BUG();
+ break;
+ }
+}
+
+static void lpc47n217_pnp_set_drq(device_t dev, u8 drq)
+{
+ const u8 PP_DMA_MASK = 0x0F;
+ const u8 PP_DMA_SELECTION_REGISTER = 0x26;
+ u8 current_config, new_config;
+
+ if (dev->path.pnp.device == LPC47N217_PP) {
+ current_config = pnp_read_config(dev,
+ PP_DMA_SELECTION_REGISTER);
+ ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range? */
+ new_config = (current_config & ~PP_DMA_MASK) | drq;
+ pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
+ } else {
+ BUG();
+ }
+}
+
+static void lpc47n217_pnp_set_irq(device_t dev, u8 irq)
+{
+ u8 irq_config_register = 0, irq_config_mask = 0;
+ u8 current_config, new_config;
+
+ switch(dev->path.pnp.device) {
+ case LPC47N217_PP:
+ irq_config_register = 0x27;
+ irq_config_mask = 0x0F;
+ break;
+ case LPC47N217_SP1:
+ irq_config_register = 0x28;
+ irq_config_mask = 0xF0;
+ irq <<= 4;
+ break;
+ case LPC47N217_SP2:
+ irq_config_register = 0x28;
+ irq_config_mask = 0x0F;
+ break;
+ default:
+ BUG();
+ return;
+ }
+
+ ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range? */
+
+ current_config = pnp_read_config(dev, irq_config_register);
+ new_config = (current_config & ~irq_config_mask) | irq;
+ pnp_write_config(dev, irq_config_register, new_config);
+}
+
+static void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+ u8 power_register = 0, power_mask = 0, current_power, new_power;
+
+ switch(dev->path.pnp.device) {
+ case LPC47N217_PP:
+ power_register = 0x01;
+ power_mask = 0x04;
+ break;
+ case LPC47N217_SP1:
+ power_register = 0x02;
+ power_mask = 0x08;
+ break;
+ case LPC47N217_SP2:
+ power_register = 0x02;
+ power_mask = 0x80;
+ break;
+ default:
+ BUG();
+ return;
+ }
+
+ current_power = pnp_read_config(dev, power_register);
+ new_power = current_power & ~power_mask; /* Disable by default. */
+ if (enable) {
+ struct resource* ioport_resource;
+ ioport_resource = find_resource(dev, PNP_IDX_IO0);
+ lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
+ new_power |= power_mask; /* Enable. */
+ } else {
+ lpc47n217_pnp_set_iobase(dev, 0);
+ }
+ pnp_write_config(dev, power_register, new_power);
+}
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ outb(0xaa, dev->path.pnp.port);
+}
+
+#if 0
+/**
+ * Print the values of all of the LPC47N217's configuration registers.
+ *
+ * NOTE: The LPC47N217 must be in config mode when this function is called.
+ *
+ * @param dev Pointer to structure describing a Super I/O device.
+ */
+static void dump_pnp_device(device_t dev)
+{
+ int i;
+ print_debug("\n");
+
+ for (i = 0; i <= LPC47N217_MAX_CONFIG_REGISTER; i++) {
+ u8 register_value;
+
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+
+ /*
+ * Skip over 'register' that would cause exit from
+ * configuration mode.
+ */
+ if (i == 0xaa)
+ register_value = 0xaa;
+ else
+ register_value = pnp_read_config(dev, i);
+
+ print_debug_char(' ');
+ print_debug_hex8(register_value);
+ if ((i & 0x0f) == 0x0f)
+ print_debug("\n");
+ }
+
+ print_debug("\n");
+}
+#endif
projects / coreboot.git / blobdiff