-/*\r
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $\r
- *\r
- * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip\r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
- *\r
- * $Log: lpc47n217_early_serial.c,v $\r
- * Revision 1.1.1.1 2005/07/11 15:28:51 smagnani\r
- * Initial revision.\r
- *\r
- *\r
- */\r
-\r
-#include <arch/romcc_io.h>\r
-#include <assert.h>\r
-#include "lpc47n217.h"\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: pnp_enter_conf_state\r
-// Parameters: dev - high 8 bits = Super I/O port\r
-// Return Value: None\r
-// Description: Enable access to the LPC47N217's configuration registers.\r
-//\r
-static inline void pnp_enter_conf_state(device_t dev) {\r
- unsigned port = dev>>8;\r
- outb(0x55, port);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: pnp_exit_conf_state\r
-// Parameters: dev - high 8 bits = Super I/O port\r
-// Return Value: None\r
-// Description: Disable access to the LPC47N217's configuration registers.\r
-//\r
-static void pnp_exit_conf_state(device_t dev) {\r
- unsigned port = dev>>8;\r
- outb(0xaa, port);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_pnp_set_iobase\r
-// Parameters: dev - high 8 bits = Super I/O port, \r
-// low 8 bits = logical device number (per lpc47n217.h)\r
-// iobase - base I/O port for the logical device\r
-// Return Value: None\r
-// Description: Program the base I/O port for the specified logical device.\r
-//\r
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)\r
-{\r
- // LPC47N217 requires base ports to be a multiple of 4\r
- ASSERT(!(iobase & 0x3));\r
-\r
- switch(dev & 0xFF) {\r
- case LPC47N217_PP: \r
- pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- default:\r
- break;\r
- }\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_pnp_set_enable\r
-// Parameters: dev - high 8 bits = Super I/O port, \r
-// low 8 bits = logical device number (per lpc47n217.h)\r
-// enable - 0 to disable, anythig else to enable\r
-// Return Value: None\r
-// Description: Enable or disable the specified logical device.\r
-// Technically, a full disable requires setting the device's base\r
-// I/O port below 0x100. We don't do that here, because we don't\r
-// have access to a data structure that specifies what the 'real'\r
-// base port is (when asked to enable the device). Also the function\r
-// is used only to disable the device while its true base port is\r
-// programmed (see lpc47n217_enable_serial() below).\r
-//\r
-void lpc47n217_pnp_set_enable(device_t dev, int enable)\r
-{\r
- uint8_t power_register = 0;\r
- uint8_t power_mask = 0;\r
- uint8_t current_power;\r
- uint8_t new_power;\r
- \r
- switch(dev & 0xFF) {\r
- case LPC47N217_PP: \r
- power_register = 0x01;\r
- power_mask = 0x04;\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- power_register = 0x02;\r
- power_mask = 0x08;\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- power_register = 0x02;\r
- power_mask = 0x80;\r
- break;\r
- \r
- default:\r
- return;\r
- }\r
-\r
- current_power = pnp_read_config(dev, power_register);\r
- new_power = current_power & ~power_mask; // disable by default\r
-\r
- if (enable)\r
- new_power |= power_mask; // Enable\r
-\r
- pnp_write_config(dev, power_register, new_power);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_enable_serial\r
-// Parameters: dev - high 8 bits = Super I/O port, \r
-// low 8 bits = logical device number (per lpc47n217.h)\r
-// iobase - processor I/O port address to assign to this serial device\r
-// Return Value: bool\r
-// Description: Configure the base I/O port of the specified serial device\r
-// and enable the serial device.\r
-//\r
-static void lpc47n217_enable_serial(device_t dev, unsigned iobase)\r
-{\r
- // NOTE: Cannot use pnp_set_XXX() here because they assume chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
- \r
- pnp_enter_conf_state(dev);\r
- lpc47n217_pnp_set_enable(dev, 0);\r
- lpc47n217_pnp_set_iobase(dev, iobase);\r
- lpc47n217_pnp_set_enable(dev, 1);\r
- pnp_exit_conf_state(dev);\r
-}\r
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include <assert.h>
+#include "lpc47n217.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+/**
+ * Program the base I/O port for the specified logical device.
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param iobase Base I/O port for the logical device.
+ */
+void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
+{
+ /* LPC47N217 requires base ports to be a multiple of 4. */
+ ASSERT(!(iobase & 0x3));
+
+ switch(dev & 0xFF) {
+ case LPC47N217_PP:
+ pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+ break;
+ case LPC47N217_SP1:
+ pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+ break;
+ case LPC47N217_SP2:
+ pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * Enable or disable the specified logical device.
+ *
+ * Technically, a full disable requires setting the device's base I/O port
+ * below 0x100. We don't do that here, because we don't have access to a data
+ * structure that specifies what the 'real' base port is (when asked to enable
+ * the device). Also the function is used only to disable the device while its
+ * true base port is programmed (see lpc47n217_enable_serial() below).
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param enable 0 to disable, anythig else to enable.
+ */
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+ u8 power_register = 0, power_mask = 0, current_power, new_power;
+
+ switch(dev & 0xFF) {
+ case LPC47N217_PP:
+ power_register = 0x01;
+ power_mask = 0x04;
+ break;
+ case LPC47N217_SP1:
+ power_register = 0x02;
+ power_mask = 0x08;
+ break;
+ case LPC47N217_SP2:
+ power_register = 0x02;
+ power_mask = 0x80;
+ break;
+ default:
+ return;
+ }
+
+ current_power = pnp_read_config(dev, power_register);
+ new_power = current_power & ~power_mask; /* Disable by default. */
+ if (enable)
+ new_power |= power_mask; /* Enable. */
+ pnp_write_config(dev, power_register, new_power);
+}
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param iobase Processor I/O port address to assign to this serial device.
+ */
+static void lpc47n217_enable_serial(device_t dev, u16 iobase)
+{
+ /*
+ * NOTE: Cannot use pnp_set_XXX() here because they assume chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ */
+ pnp_enter_conf_state(dev);
+ lpc47n217_pnp_set_enable(dev, 0);
+ lpc47n217_pnp_set_iobase(dev, iobase);
+ lpc47n217_pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
projects / coreboot.git / blobdiff