fix superio warnings. interesting side node: most superio .h files have no

[coreboot.git] / src / superio / ite / it8718f / it8718f_early_serial.c

diff --git a/src/superio/ite/it8718f/it8718f_early_serial.c b/src/superio/ite/it8718f/it8718f_early_serial.c
index f4fa04ef23efb95b2fefbecb1be1b766d9ec9af1..fabbde5e8fc5f9d2eaf56af7d364328bf858ecdd 100644 (file)
--- a/src/superio/ite/it8718f/it8718f_early_serial.c
+++ b/src/superio/ite/it8718f/it8718f_early_serial.c
@@ -64,7 +64,7 @@ static void it8718f_exit_conf(void)
        it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
 }
 
-static void it8718f_24mhz_clkin(void)
+void it8718f_24mhz_clkin(void)
 {
        it8718f_enter_conf();
 
@@ -75,7 +75,7 @@ static void it8718f_24mhz_clkin(void)
 }
 
 /* Enable the peripheral devices on the IT8718F Super I/O chip. */
-static void it8718f_enable_serial(device_t dev, unsigned iobase)
+void it8718f_enable_serial(device_t dev, unsigned iobase)
 {
        /* (1) Enter the configuration state (MB PnP mode). */
        it8718f_enter_conf();
@@ -83,8 +83,8 @@ static void it8718f_enable_serial(device_t dev, unsigned iobase)
        /* (2) Modify the data of configuration registers. */
 
        /* Select the chip to configure (if there's more than one).
-           Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-           If this register is not written, both chips are configured. */
+          Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+          If this register is not written, both chips are configured. */
        /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
 
        /* Enable serial port(s). */
@@ -97,4 +97,3 @@ static void it8718f_enable_serial(device_t dev, unsigned iobase)
        /* (3) Exit the configuration state (MB PnP mode). */
        it8718f_exit_conf();
 }
-