C and other Super I/O cosmetic fixes.

[coreboot.git] / src / superio / intel / i3100 / superio.c

diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c
index 340fb00c50567fc9b652db7498aa2ecd79cfe8a3..120790a194160b69041ed2e160ce283d6edfc5a5 100644 (file)
--- a/src/superio/intel/i3100/superio.c
+++ b/src/superio/intel/i3100/superio.c
@@ -28,14 +28,14 @@
 
 static void pnp_enter_ext_func_mode(device_t dev)
 {
-       outb(0x80, dev->path.u.pnp.port);
-       outb(0x86, dev->path.u.pnp.port);
+       outb(0x80, dev->path.pnp.port);
+       outb(0x86, dev->path.pnp.port);
 }
 
 static void pnp_exit_ext_func_mode(device_t dev)
 {
-       outb(0x68, dev->path.u.pnp.port);
-       outb(0x08, dev->path.u.pnp.port);
+       outb(0x68, dev->path.pnp.port);
+       outb(0x08, dev->path.pnp.port);
 }
 
 static void i3100_init(device_t dev)
@@ -43,13 +43,12 @@ static void i3100_init(device_t dev)
        struct superio_intel_i3100_config *conf;
        struct resource *res0;
 
-       if (!dev->enabled) {
+       if (!dev->enabled)
                return;
-       }
 
        conf = dev->chip_info;
 
-       switch (dev->path.u.pnp.device) {
+       switch (dev->path.pnp.device) {
        case I3100_SP1:
                res0 = find_resource(dev, PNP_IDX_IO0);
                init_uart8250(res0->base, &conf->com1);
@@ -92,8 +91,8 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-       { &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+       { &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 };
 
 static void enable_dev(struct device *dev)
@@ -105,4 +104,3 @@ struct chip_operations superio_intel_i3100_ops = {
        CHIP_NAME("Intel 3100 Super I/O")
        .enable_dev = enable_dev,
 };
-