C and other Super I/O cosmetic fixes.

[coreboot.git] / src / superio / fintek / f71863fg / superio.c

diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c
index e41c0500477841f32d63f511ec4adff2abf9c1e6..f54d3ad22bdecca5b90077005a877e1cf1920562 100644 (file)
--- a/src/superio/fintek/f71863fg/superio.c
+++ b/src/superio/fintek/f71863fg/superio.c
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pnp.h>
@@ -31,6 +30,7 @@
 static void pnp_enter_conf_state(device_t dev)
 {
        outb(0x87, dev->path.pnp.port);
+       outb(0x87, dev->path.pnp.port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
@@ -56,6 +56,10 @@ static void f71863fg_init(device_t dev)
                res0 = find_resource(dev, PNP_IDX_IO0);
                init_uart8250(res0->base, &conf->com2);
                break;
+       case F71863FG_KBC:
+               res0 = find_resource(dev, PNP_IDX_IO0);
+               pc_keyboard_init(&conf->keyboard);
+               break;
        }
 }
 
@@ -90,13 +94,16 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-       /* TODO: Some of the 0x7f8 etc. values may not be correct. */
-       { &ops, F71863FG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-       { &ops, F71863FG_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, F71863FG_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, F71863FG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-       { &ops, F71863FG_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
-       { &ops, F71863FG_GPIO, PNP_IRQ0, },
+       /* TODO: Some of the 0x07f8 etc. values may not be correct. */
+       { &ops, F71863FG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, F71863FG_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, F71863FG_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, F71863FG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, F71863FG_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+       { &ops, F71863FG_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
+       { &ops, F71863FG_GPIO, }
+       { &ops, F71863FG_VID,  PNP_IO0, {0x07f8, 0}, },
+       { &ops, F71863FG_SPI, },
        { &ops, F71863FG_PME, },
 };