C and other Super I/O cosmetic fixes.

[coreboot.git] / src / superio / fintek / f71805f / superio.c

diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c
index 50801dda221af59761ea57bf53e5ceb8a0a7a6a1..e1012bae51ca6c3a41c21ffb6373065c89fc420f 100644 (file)
--- a/src/superio/fintek/f71805f/superio.c
+++ b/src/superio/fintek/f71805f/superio.c
@@ -30,6 +30,7 @@
 static void pnp_enter_conf_state(device_t dev)
 {
        outb(0x87, dev->path.pnp.port);
+       outb(0x87, dev->path.pnp.port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
@@ -89,12 +90,12 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-       /* TODO: Some of the 0x7f8 etc. values may not be correct. */
-       { &ops, F71805F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-       { &ops, F71805F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, F71805F_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-       { &ops, F71805F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-       { &ops, F71805F_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
+       /* TODO: Some of the 0x07f8 etc. values may not be correct. */
+       { &ops, F71805F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, F71805F_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, F71805F_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+       { &ops, F71805F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+       { &ops, F71805F_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
        { &ops, F71805F_GPIO, PNP_IRQ0, },
        { &ops, F71805F_PME, },
 };