);
port (
sys_clk : in std_logic;
- sys_res_n : in std_logic;
address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data_out : out hbyte;
wr : in std_logic;
architecture beh of sp_ram is
subtype RAM_ENTRY_TYPE is hbyte;
- type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH) - 1) of RAM_ENTRY_TYPE;
- signal ram : RAM_TYPE := (others => x"00");
+ type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE;
+ signal ram : RAM_TYPE := (1 => x"41", 2 => x"42", 3 => x"43", 4 => x"44",
+ 5 => x"45", 6 => x"46", 7 => x"47", 8 => x"48", 9 => x"49", 10 => x"50", others => x"00");
begin
- process(sys_clk, sys_res_n)
+ process(sys_clk)
begin
- if sys_res_n = '0' then
- ram <= (others => x"00");
- elsif rising_edge(sys_clk) then
+ if rising_edge(sys_clk) then
data_out <= ram(to_integer(unsigned(address)));
if wr = '1' then
ram(to_integer(unsigned(address))) <= data_in;