/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ops.h>
#include <device/pci_ids.h>
#define SATA_MISC_CTRL 0x45
-static void sata_init(struct device *dev)
+static void sata_i_init(struct device *dev)
{
u8 reg;
- printk_debug("Configuring VIA SATA controller\n");
+ printk(BIOS_DEBUG, "Configuring VIA SATA controller\n");
/* Class IDE Disk */
reg = pci_read_config8(dev, SATA_MISC_CTRL);
pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1);
reg |= 0x80; /* Sub Class Write Protect on */
pci_write_config8(dev, SATA_MISC_CTRL, reg);
+
+ return;
+}
+
+static void sata_ii_init(struct device *dev)
+{
+ u8 reg;
+
+ sata_i_init(dev);
+
+ /*
+ * Analog black magic, you may or may not need to adjust 0x60-0x6f,
+ * depends on PCB.
+ */
+
+ /*
+ * Analog PHY - gen1
+ * CDR bandwidth [6:5] = 3
+ * Squelch Window Select [4:3] = 1
+ * CDR Charge Pump [2:0] = 1
+ */
+
+ pci_write_config8(dev, 0x64, 0x49);
+
+ /* Adjust driver current source value to 9. */
+ reg = pci_read_config8(dev, 0x65);
+ reg &= 0xf0;
+ reg |= 0x9;
+ pci_write_config8(dev, 0x65, reg);
+
+ /* Set all manual termination 50ohm bits [2:0] and enable [4]. */
+ reg = pci_read_config8(dev, 0x6a);
+ reg |= 0xf;
+ pci_write_config8(dev, 0x6a, reg);
+
+ /*
+ * Analog PHY - gen2
+ * CDR bandwidth [5:4] = 2
+ * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e
+ * CDR Charge Pump [2:0] = 1
+ */
+
+ reg = pci_read_config8(dev, 0x6f);
+ reg &= 0x08;
+ reg |= 0x61;
+ pci_write_config8(dev, 0x6f, reg);
+
+ /* Check if staggered spinup is supported. */
+ reg = pci_read_config8(dev, 0x83);
+ if ((reg & 0x8) == 0) {
+ /* Start OOB sequence on both drives. */
+ reg |= 0x30;
+ pci_write_config8(dev, 0x83, reg);
+ }
}
-static const struct device_operations sata_ops = {
+static const struct device_operations sata_i_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sata_i_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static const struct device_operations sata_ii_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = sata_init,
+ .init = sata_ii_init,
.enable = 0,
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &sata_ops,
+static const struct pci_driver northbridge_driver_ii __pci_driver = {
+ .ops = &sata_ii_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VT8237_SATA,
+};
+
+static const struct pci_driver northbridge_driver_i __pci_driver = {
+ .ops = &sata_i_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_VT6420_SATA,
};