/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License v2 as published by
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
+#include <pc80/keyboard.h>
+#include <pc80/i8259.h>
#include <stdlib.h>
#include "vt8237r.h"
#include "chip.h"
} ioapic_table[] = {
/* IO-APIC virtual wire mode configuration. */
/* mask, trigger, polarity, destination, delivery, vector */
- {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST |
- ExtINT, NONE},
+ {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST |
+ ExtINT, NONE},
{1, DISABLED, NONE},
{2, DISABLED, NONE},
{3, DISABLED, NONE},
}
}
+static void southbridge_init_common(struct device *dev);
+
/** Set up PCI IRQ routing, route everything through APIC. */
static void pci_routing_fixup(struct device *dev)
{
* Set up the power management capabilities directly into ACPI mode.
* This avoids having to handle any System Management Interrupts (SMIs).
*/
+
+extern u8 acpi_slp_type;
+
+
static void setup_pm(device_t dev)
{
+ u16 tmp;
/* Debounce LID and PWRBTN# Inputs for 16ms. */
pci_write_config8(dev, 0x80, 0x20);
/* GP Timer Control 1s */
pci_write_config8(dev, 0x93, 0x88);
- /* 7 = SMBus clock from RTC 32.768KHz
- * 5 = Internal PLL reset from susp
- * 2 = GPO2 is GPIO
+ /*
+ * 7 = SMBus clock from RTC 32.768KHz
+ * 5 = Internal PLL reset from susp disabled
+ * 2 = GPO2 is SUSA#
*/
- pci_write_config8(dev, 0x94, 0xa4);
+ pci_write_config8(dev, 0x94, 0xa0);
- /* 7 = stp to sust delay 1msec
+ /*
+ * 7 = stp to sust delay 1msec
* 6 = SUSST# Deasserted Before PWRGD for STD
+ * 4 = PWRGOOD reset on VT8237A/S
* 3 = GPO26/GPO27 is GPO
* 2 = Disable Alert on Lan
*/
/* Disable GP3 timer. */
pci_write_config8(dev, 0x98, 0);
- /* Enable SATA LED, disable special CPU Frequency Change -
- * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
- */
- pci_write_config8(dev, 0xe5, 0x9);
-
- /* REQ5 as PCI request input - should be together with INTE-INTH. */
- pci_write_config8(dev, 0xe4, 0x4);
-
/* Enable ACPI accessm RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
outb(0x0, VT8237R_ACPI_IO_BASE + 0x42);
/* SCI is generated for RTC/pwrBtn/slpBtn. */
- outw(0x001, VT8237R_ACPI_IO_BASE + 0x04);
+ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
+#if HAVE_ACPI_RESUME == 1
+ acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
+ printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
+#endif
+ /* clear sleep */
+ tmp &= ~(7 << 10);
+ tmp |= 1;
+ outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
+
+
+
+
+}
+
+static void vt8237r_init(struct device *dev)
+{
+ u8 enables;
+
+ /*
+ * Enable SATA LED, disable special CPU Frequency Change -
+ * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+ */
+ pci_write_config8(dev, 0xe5, 0x9);
+
+ /* REQ5 as PCI request input - should be together with INTE-INTH. */
+ pci_write_config8(dev, 0xe4, 0x4);
+
+ /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
+ enables = pci_read_config8(dev, 0x4f);
+ enables |= 0x08;
+ pci_write_config8(dev, 0x4f, enables);
+
+ /*
+ * Set Read Pass Write Control Enable
+ * (force A2 from APIC FSB to low).
+ */
+ pci_write_config8(dev, 0x48, 0x8c);
+
+ southbridge_init_common(dev);
/* FIXME: Intel needs more bit set for C2/C3. */
- /* Allow SLP# signal to assert LDTSTOP_L.
+ /*
+ * Allow SLP# signal to assert LDTSTOP_L.
* Will work for C3 and for FID/VID change.
*/
outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
}
-static void vt8237r_init(struct device *dev)
+static void vt8237s_init(struct device *dev)
+{
+ u32 tmp;
+
+ /* Put SPI base VT8237S_SPI_MEM_BASE. */
+ tmp = pci_read_config32(dev, 0xbc);
+ pci_write_config32(dev, 0xbc,
+ (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
+
+ /*
+ * REQ5 as PCI request input - should be together with INTE-INTH.
+ */
+ pci_write_config8(dev, 0xe4, 0x04);
+
+ /* Reduce further the STPCLK/LDTSTP signal to 5us. */
+ pci_write_config8(dev, 0xec, 0x4);
+
+ /* Host Bus Power Management Control, maybe not needed */
+ pci_write_config8(dev, 0x8c, 0x5);
+
+ /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */
+ pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+
+ southbridge_init_common(dev);
+
+ /* FIXME: Intel needs more bit set for C2/C3. */
+
+ /*
+ * Allow SLP# signal to assert LDTSTOP_L.
+ * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.
+ */
+ outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
+
+ dump_south(dev);
+}
+
+static void vt8237_common_init(struct device *dev)
{
u8 enables, byte;
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
- /* FIXME: Map 4MB of flash into the address space,
- * this should be in CAR call.
+ /*
+ * ROM decode
+ * bit range
+ * 7 000E0000h-000EFFFFh
+ * 6 FFF00000h-FFF7FFFFh
+ * 5 FFE80000h-FFEFFFFFh
+ * 4 FFE00000h-FFE7FFFFh
+ * 3 FFD80000h-FFDFFFFFh
+ * 2 FFD00000h-FFD7FFFFh
+ * 1 FFC80000h-FFCFFFFFh
+ * 0 FFC00000h-FFC7FFFFh
+ * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
*/
- /* pci_write_config8(dev, 0x41, 0x7f); */
+ pci_write_config8(dev, 0x41, 0x7f);
- /* Set bit 6 of 0x40 (I/O recovery time).
+ /*
+ * Set bit 6 of 0x40 (I/O recovery time).
* IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
* that PCI interrupts can be properly marked as level triggered.
*/
/* Delay transaction control */
pci_write_config8(dev, 0x43, 0xb);
- /* I/O recovery time */
+ /* I/O recovery time, default IDE routing */
pci_write_config8(dev, 0x4c, 0x44);
/* ROM memory cycles go to LPC. */
pci_write_config8(dev, 0x59, 0x80);
- /* Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI. */
- pci_write_config8(dev, 0x5B, 0xb);
-
- /* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */
- pci_write_config8(dev, 0x48, 0x8c);
+ /*
+ * Bit | Meaning
+ * -------------
+ * 3 | Bypass APIC De-Assert Message (1=Enable)
+ * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
+ * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
+ * 0 | Dynamic Clock Gating Main Switch (1=Enable)
+ */
+ pci_write_config8(dev, 0x5b, 0xb);
/* Set 0x58 to 0x43 APIC and RTC. */
pci_write_config8(dev, 0x58, 0x43);
- /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
-
/* Enable serial IRQ, 6PCI clocks. */
pci_write_config8(dev, 0x52, 0x9);
- /* Enable HPET at VT8237R_HPET_ADDR. */
- pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
-
/* Power management setup */
setup_pm(dev);
init_pc_keyboard(0x60, 0x64, 0);
}
-static void southbridge_init(struct device *dev)
+static void southbridge_init_common(struct device *dev)
{
- vt8237r_init(dev);
+ vt8237_common_init(dev);
pci_routing_fixup(dev);
setup_ioapic(VT8237R_APIC_BASE);
setup_i8259();
init_keyboard(dev);
}
-static const struct device_operations vt8237r_lpc_ops = {
+static const struct device_operations vt8237r_lpc_ops_s = {
.read_resources = vt8237r_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = vt8237r_enable_resources,
- .init = &southbridge_init,
+ .init = &vt8237s_init,
.scan_bus = scan_static_bus,
};
-static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &vt8237r_lpc_ops,
+static const struct device_operations vt8237r_lpc_ops_r = {
+ .read_resources = vt8237r_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = vt8237r_enable_resources,
+ .init = &vt8237r_init,
+ .scan_bus = scan_static_bus,
+};
+
+static const struct pci_driver lpc_driver_r __pci_driver = {
+ .ops = &vt8237r_lpc_ops_r,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_VT8237R_LPC,
};
+
+static const struct pci_driver lpc_driver_s __pci_driver = {
+ .ops = &vt8237r_lpc_ops_s,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VT8237S_LPC,
+};
projects / coreboot.git / blobdiff