* This file is part of the coreboot project.
*
* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk>
+ * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk>
*
* This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
#include <device/pci.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <pc80/keyboard.h>
#include <pc80/i8259.h>
#include "vt8237r.h"
#include "chip.h"
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
extern void dump_south(device_t dev);
static void southbridge_init_common(struct device *dev);
-#ifdef CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
/* Interrupts for INT# A B C D */
static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};
}
#endif
-static struct ioapicreg {
- u32 reg;
- u32 value_low;
- u32 value_high;
-} ioapic_table[] = {
- /* IO-APIC virtual wire mode configuration. */
- /* mask, trigger, polarity, destination, delivery, vector */
- {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST |
- ExtINT, NONE},
- {1, DISABLED, NONE},
- {2, DISABLED, NONE},
- {3, DISABLED, NONE},
- {4, DISABLED, NONE},
- {5, DISABLED, NONE},
- {6, DISABLED, NONE},
- {7, DISABLED, NONE},
- {8, DISABLED, NONE},
- {9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
-};
-
-static void setup_ioapic(u32 ioapic_base)
-{
- u32 value_low, value_high, val;
- volatile u32 *l;
- int i;
-
- /* All delivered to CPU0. */
- ioapic_table[0].value_high = (lapicid()) << (56 - 32);
- l = (u32 *)ioapic_base;
-
-#ifdef CONFIG_EPIA_VT8237R_INIT
- /* Set APIC to APIC Serial bus. */
- l[0] = 0x3;
- l[4] = 0;
-#else
- /* Set APIC to FSB message bus. */
- l[0] = 0x3;
- val = l[4];
- l[4] = (val & 0xFFFFFE) | 1;
-#endif
-
- /* Set APIC ADDR - this will be VT8237R_APIC_ID. */
- l[0] = 0;
- val = l[4];
- l[4] = (val & 0xF0FFFF) | (VT8237R_APIC_ID << 24);
-
- for (i = 0; i < ARRAY_SIZE(ioapic_table); i++) {
- l[0] = (ioapic_table[i].reg * 2) + 0x10;
- l[4] = ioapic_table[i].value_low;
- value_low = l[4];
- l[0] = (ioapic_table[i].reg * 2) + 0x11;
- l[4] = ioapic_table[i].value_high;
- if (i == 0) {
- l[0] = (ioapic_table[i].reg * 2) + 0x10;
- value_low = l[4];
- if (value_low == 0xffffffff)
- {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
- }
-}
-
-
/** Set up PCI IRQ routing, route everything through APIC. */
static void pci_routing_fixup(struct device *dev)
{
-#ifdef CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
device_t pdev;
u8 reg;
#endif
/* Gate Interrupts until RAM Writes are flushed */
pci_write_config8(dev, 0x49, 0x20);
-#ifdef CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
/* Share INTE-INTH with INTA-INTD as per stock BIOS. */
pci_write_config8(dev, 0x46, 0x00);
/* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
-#ifdef CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
pci_write_config16(dev, 0x84, 0x3052);
#else
* 0 = USB Wakeup
*/
-#ifdef CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
pci_write_config8(dev, 0x95, 0xc2);
#else
pci_write_config8(dev, 0x95, 0xcc);
{
u8 enables, reg8;
-#ifdef CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
printk_spew("Entering vt8237r_init, for EPIA.\n");
/*
* TODO: Looks like stock BIOS can do this but causes a hang
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
-#ifdef CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
/*
* Set Read Pass Write Control Enable
*/
southbridge_init_common(dev);
-#ifndef CONFIG_EPIA_VT8237R_INIT
+#if !CONFIG_EPIA_VT8237R_INIT
/* FIXME: Intel needs more bit set for C2/C3. */
/*
pci_write_config8(dev, PCI_COMMAND, byte);
/* EPIA-N(L) Uses CN400 for BIOS Access */
-#ifndef CONFIG_EPIA_VT8237R_INIT
+#if !CONFIG_EPIA_VT8237R_INIT
/* Enable the internal I/O decode. */
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
/* Delay transaction control */
pci_write_config8(dev, 0x43, 0xb);
-#ifdef CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
/* I/O recovery time, default IDE routing */
pci_write_config8(dev, 0x4c, 0x04);
{
vt8237_common_init(dev);
pci_routing_fixup(dev);
- setup_ioapic(VT8237R_APIC_BASE);
+ setup_ioapic(VT8237R_APIC_BASE, VT8237R_APIC_ID);
setup_i8259();
init_keyboard(dev);
}
projects / coreboot.git / blobdiff