VIA southbridge K8T890: Apply un-written naming rules

[coreboot.git] / src / southbridge / via / vt8237r / lpc.c

diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 3e2f215751024c49ba910b34956b69f9a4621c17..7fc5b524fde2112972e885da0fd0f779d84f19f1 100644 (file)
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -151,6 +151,10 @@ static void pci_routing_fixup(struct device *dev)
 static void setup_pm(device_t dev)
 {
        u16 tmp;
+       struct southbridge_via_vt8237r_config *cfg;
+
+       cfg = dev->chip_info;
+
        /* Debounce LID and PWRBTN# Inputs for 16ms. */
        pci_write_config8(dev, 0x80, 0x20);
 
@@ -179,7 +183,10 @@ static void setup_pm(device_t dev)
         * 5 = Internal PLL reset from susp disabled
         * 2 = GPO2 is SUSA#
         */
-       pci_write_config8(dev, 0x94, 0xa0);
+       tmp = 0xa0;
+       if (cfg && cfg->enable_gpo3)
+               tmp |= 0x10;
+       pci_write_config8(dev, 0x94, tmp);
 
        /*
         * 7 = stp to sust delay 1msec
@@ -195,7 +202,14 @@ static void setup_pm(device_t dev)
 #if CONFIG_EPIA_VT8237R_INIT
        pci_write_config8(dev, 0x95, 0xc2);
 #else
-       pci_write_config8(dev, 0x95, 0xcc);
+       tmp = 0xcc;
+       if (cfg) {
+               if (cfg->disable_gpo26_gpo27)
+                       tmp &= ~0x08;
+               if (cfg->enable_aol_2_smb_slave)
+                       tmp &= ~0x04;
+       }
+       pci_write_config8(dev, 0x95, tmp);
 #endif
 
        /* Disable GP3 timer. */
@@ -247,6 +261,9 @@ static void setup_pm(device_t dev)
 static void vt8237r_init(struct device *dev)
 {
        u8 enables;
+       struct southbridge_via_vt8237r_config *cfg;
+
+       cfg = dev->chip_info;
 
 #if CONFIG_EPIA_VT8237R_INIT
        printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
@@ -282,8 +299,15 @@ static void vt8237r_init(struct device *dev)
         */
        pci_write_config8(dev, 0xe5, 0x09);
 
+       enables = 0x4;
+       if (cfg) {
+               if (cfg->enable_gpo5)
+                       enables |= 0x01;
+               if (cfg->gpio15_12_dir_output)
+                       enables |= 0x10;
+       }
        /* REQ5 as PCI request input - should be together with INTE-INTH. */
-       pci_write_config8(dev, 0xe4, 0x4);
+       pci_write_config8(dev, 0xe4, enables);
 #endif
 
        /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
@@ -297,8 +321,8 @@ static void vt8237r_init(struct device *dev)
         */
        pci_write_config8(dev, 0x48, 0x0c);
 #else
-       
-  #if CONFIG_SOUTHBRIDGE_VIA_K8T800
+
+  #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
        /* It seems that when we pair with the K8T800, we need to disable
         * the A2 mask
         */
@@ -310,7 +334,7 @@ static void vt8237r_init(struct device *dev)
         */
        pci_write_config8(dev, 0x48, 0x8c);
   #endif
-       
+
 #endif
 
        southbridge_init_common(dev);
@@ -327,7 +351,7 @@ static void vt8237r_init(struct device *dev)
 
        printk(BIOS_SPEW, "Leaving %s.\n", __func__);
        printk(BIOS_SPEW, "And taking a dump:\n");
-       dump_south(dev);        
+       dump_south(dev);
 }
 
 static void vt8237a_init(struct device *dev)
@@ -421,6 +445,12 @@ static void vt8237s_init(struct device *dev)
 static void vt8237_common_init(struct device *dev)
 {
        u8 enables, byte;
+       struct southbridge_via_vt8237r_config *cfg;
+#if !CONFIG_EPIA_VT8237R_INIT
+       unsigned char pwr_on;
+#endif
+
+       cfg = dev->chip_info;
 
        /* Enable addr/data stepping. */
        byte = pci_read_config8(dev, PCI_COMMAND);
@@ -506,7 +536,20 @@ static void vt8237_common_init(struct device *dev)
         *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
         *   0 | Dynamic Clock Gating Main Switch (1=Enable)
         */
-       pci_write_config8(dev, 0x5b, 0xb);
+       if (cfg && cfg->int_efgh_as_gpio) {
+               pci_write_config8(dev, 0x5b, 0x9);
+       } else {
+               pci_write_config8(dev, 0x5b, 0xb);
+       }
+
+       /* configure power state of the board after loss of power */
+       if (get_option(&pwr_on, "power_on_after_fail") < 0)
+               pwr_on = 1;
+       enables = pci_read_config8(dev, 0x58);
+       pci_write_config8(dev, 0x58, enables & ~0x02);
+       outb(0x0d, 0x70);
+       outb(pwr_on ? 0x00 : 0x80, 0x71);
+       pci_write_config8(dev, 0x58, enables);
 
        /* Set 0x58 to 0x43 APIC and RTC. */
        pci_write_config8(dev, 0x58, 0x43);
@@ -596,12 +639,24 @@ static void southbridge_init_common(struct device *dev)
        init_keyboard(dev);
 }
 
+
+static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+       pci_write_config16(dev, 0x70, vendor);
+       pci_write_config16(dev, 0x72, device);
+}
+
+static struct pci_operations lops_pci = {
+       .set_subsystem = vt8237_set_subsystem,
+};
+
 static const struct device_operations vt8237r_lpc_ops_s = {
        .read_resources         = vt8237r_read_resources,
        .set_resources          = pci_dev_set_resources,
        .enable_resources       = pci_dev_enable_resources,
        .init                   = vt8237s_init,
        .scan_bus               = scan_static_bus,
+       .ops_pci                = &lops_pci,
 };
 
 static const struct device_operations vt8237r_lpc_ops_r = {
@@ -610,6 +665,7 @@ static const struct device_operations vt8237r_lpc_ops_r = {
        .enable_resources       = pci_dev_enable_resources,
        .init                   = vt8237r_init,
        .scan_bus               = scan_static_bus,
+       .ops_pci                = &lops_pci,
 };
 
 static const struct device_operations vt8237r_lpc_ops_a = {
@@ -618,6 +674,7 @@ static const struct device_operations vt8237r_lpc_ops_a = {
        .enable_resources       = pci_dev_enable_resources,
        .init                   = vt8237a_init,
        .scan_bus               = scan_static_bus,
+       .ops_pci                = &lops_pci,
 };
 
 static const struct pci_driver lpc_driver_r __pci_driver = {