Various license header consistency fixes (trivial).

[coreboot.git] / src / southbridge / via / k8t890 / k8t890_host_ctrl.c

diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
index faa498e8b0952a4d406b8175e3ad49f533f6a146..38f69680fe23775c0ae39db618fc597d5a1addd6 100644 (file)
--- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
@@ -4,8 +4,8 @@
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -22,6 +22,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
+#include "k8t890.h"
 
 /* this may be later merged */
 
@@ -36,14 +37,14 @@ static void host_ctrl_enable_k8t890(struct device *dev)
         */
        pci_write_config8(dev, 0xa0, 0x13);
 
-       /* Disable NVRAM and enable non-posted PCI writes. */
-       pci_write_config8(dev, 0xa1, 0x8e);
-
        /*
-        * NVRAM I/O base 0xe00-0xeff, but it is disabled.
+        * NVRAM I/O base at K8T890_NVRAM_IO_BASE
         * Some bits are set and reserved.
         */
-       pci_write_config8(dev, 0xa2, 0x0e);
+       pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+       /* enable NB NVRAM and enable non-posted PCI writes. */
+       pci_write_config8(dev, 0xa1, 0x8f);
        /* Arbitration control, some bits are reserved. */
        pci_write_config8(dev, 0xa5, 0x3c);
 
@@ -94,14 +95,15 @@ static void host_ctrl_enable_k8m890(struct device *dev) {
         */
        pci_write_config8(dev, 0xa0, 0x13);
 
-       /* Disable NVRAM and enable non-posted PCI writes. */
-       pci_write_config8(dev, 0xa1, 0x8e);
-
        /*
-        * NVRAM I/O base 0xe00-0xeff, but it is disabled.
+        * NVRAM I/O base at K8T890_NVRAM_IO_BASE
         */
 
-       pci_write_config8(dev, 0xa2, 0x0e);
+       pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+       /* Enable NVRAM and enable non-posted PCI writes. */
+       pci_write_config8(dev, 0xa1, 0x8f);
+
        /* Arbitration control  */
        pci_write_config8(dev, 0xa5, 0x3c);