Various license header consistency fixes (trivial).

[coreboot.git] / src / southbridge / via / k8t890 / k8t890_host_ctrl.c

diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
index e3e358b7ca5e7d1e90c21d84bf0437e1cece00f3..38f69680fe23775c0ae39db618fc597d5a1addd6 100644 (file)
--- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
@@ -1,11 +1,11 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -22,9 +22,12 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
+#include "k8t890.h"
+
+/* this may be later merged */
 
 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable(struct device *dev)
+static void host_ctrl_enable_k8t890(struct device *dev)
 {
        dump_south(dev);
 
@@ -34,20 +37,25 @@ static void host_ctrl_enable(struct device *dev)
         */
        pci_write_config8(dev, 0xa0, 0x13);
 
-       /* Disable NVRAM and enable non-posted PCI writes. */
-       pci_write_config8(dev, 0xa1, 0x8e);
-
        /*
-        * NVRAM I/O base 0xe00-0xeff, but it is disabled.
+        * NVRAM I/O base at K8T890_NVRAM_IO_BASE
         * Some bits are set and reserved.
         */
-       pci_write_config8(dev, 0xa2, 0x0e);
+       pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+       /* enable NB NVRAM and enable non-posted PCI writes. */
+       pci_write_config8(dev, 0xa1, 0x8f);
        /* Arbitration control, some bits are reserved. */
        pci_write_config8(dev, 0xa5, 0x3c);
 
        /* Arbitration control 2 */
        pci_write_config8(dev, 0xa6, 0x80);
 
+       /* this will be possibly removed, when I figure out
+        * if the ROM SIP is good, second reason is that the 
+        * unknown bits are AGP related, which are dummy on K8T890
+        */
+
        writeback(dev, 0xa0, 0x13);     /* Bit4 is reserved! */
        writeback(dev, 0xa1, 0x8e);     /* Some bits are reserved. */
        writeback(dev, 0xa2, 0x0e);     /* I/O NVRAM base 0xe00-0xeff disabled. */
@@ -78,16 +86,56 @@ static void host_ctrl_enable(struct device *dev)
        dump_south(dev);
 }
 
-static struct device_operations host_ctrl_ops = {
-       .read_resources = pci_dev_read_resources,
-       .set_resources = pci_dev_set_resources,
-       .enable_resources = pci_dev_enable_resources,
-       .enable = host_ctrl_enable,
-       .ops_pci = 0,
+/* This fine tunes the HT link settings, which were loaded by ROM strap. */
+static void host_ctrl_enable_k8m890(struct device *dev) {
+
+       /*
+        * Set PCI to HT outstanding requests to 03.
+        * Bit 4 32 AGP ADS Read Outstanding Request Number
+        */
+       pci_write_config8(dev, 0xa0, 0x13);
+
+       /*
+        * NVRAM I/O base at K8T890_NVRAM_IO_BASE
+        */
+
+       pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+       /* Enable NVRAM and enable non-posted PCI writes. */
+       pci_write_config8(dev, 0xa1, 0x8f);
+
+       /* Arbitration control  */
+       pci_write_config8(dev, 0xa5, 0x3c);
+
+       /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
+       pci_write_config8(dev, 0xa6, 0x83);
+
+}
+
+static const struct device_operations host_ctrl_ops_t = {
+       .read_resources         = pci_dev_read_resources,
+       .set_resources          = pci_dev_set_resources,
+       .enable_resources       = pci_dev_enable_resources,
+       .enable                 = host_ctrl_enable_k8t890,
+       .ops_pci                = 0,
+};
+
+static const struct device_operations host_ctrl_ops_m = {
+       .read_resources         = pci_dev_read_resources,
+       .set_resources          = pci_dev_set_resources,
+       .enable_resources       = pci_dev_enable_resources,
+       .enable                 = host_ctrl_enable_k8m890,
+       .ops_pci                = 0,
+};
+
+static const struct pci_driver northbridge_driver_t __pci_driver = {
+       .ops    = &host_ctrl_ops_t,
+       .vendor = PCI_VENDOR_ID_VIA,
+       .device = PCI_DEVICE_ID_VIA_K8T890CE_2,
 };
 
-static const struct pci_driver northbridge_driver __pci_driver = {
-       .ops = &host_ctrl_ops,
-       .vendor = PCI_VENDOR_ID_VIA,
-       .device = PCI_DEVICE_ID_VIA_K8T890CE_2,
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+       .ops    = &host_ctrl_ops_m,
+       .vendor = PCI_VENDOR_ID_VIA,
+       .device = PCI_DEVICE_ID_VIA_K8M890CE_2,
 };