*/
#include <stdlib.h>
-//include "k8t890.h"
-#warning hack the right header here
+#include "k8t890.h"
/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
#define K8T890_NVRAM_IO_BASE 0xf00
#define K8T890_MULTIPLE_FN_EN 0x4f
+
/* we provide S3 NVRAM to system */
#define S3_NVRAM_EARLY 1
/* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
-static ldtreg[3] = {0x86, 0xa6, 0xc6};
+static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
/* This functions sets KT890 link frequency and width to same values as
* it has been setup on K8 side, by AMD NB init.
- */
+ */
u8 k8t890_early_setup_ht(void)
{
pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
/* check if connected non coherent, initcomplete (find the SB on K8 side) */
+ ldtnr = 0;
if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
ldtnr = 0;
} else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) {
return 1;
}
-int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
-
+static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
+{
+
printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
switch (size) {
case 1:
return nvram_pos;
}
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+{
switch (size) {
case 1:
*old_dword &= ~0xff;