The interrupt controller lives at I/O 0x4d0/0x4d1.

[coreboot.git] / src / southbridge / via / k8t890 / k8t890_early_car.c

diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c
index a7bb9102c4383a8a1948982579afa14e189ec776..037f5a75eb6eae07cfd78571a0798e3c4fbbdb16 100644 (file)
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/k8t890_early_car.c
@@ -23,22 +23,22 @@
  */
 
 #include <stdlib.h>
-//include "k8t890.h"
-#warning hack the right header here
+#include "k8t890.h"
 
 /* The 256 bytes of NVRAM for S3 storage, 256B aligned */
 #define K8T890_NVRAM_IO_BASE   0xf00
 #define K8T890_MULTIPLE_FN_EN  0x4f
+
 /* we provide S3 NVRAM to system */
 #define S3_NVRAM_EARLY 1
 
 
 /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
-static ldtreg[3] = {0x86, 0xa6, 0xc6};
+static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
 
 /* This functions sets KT890 link frequency and width to same values as
  * it has been setup on K8 side, by AMD NB init.
- */ 
+ */
 
 u8 k8t890_early_setup_ht(void)
 {
@@ -113,8 +113,9 @@ u8 k8t890_early_setup_ht(void)
        return 1;
 }
 
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
-       
+static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+{
+
        printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
        switch (size) {
        case 1:
@@ -133,7 +134,8 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
        return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+{
        switch (size) {
        case 1:
                *old_dword &= ~0xff;