/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
* Written by Morgan Tsai <my_tsai@sis.com> for SiS.
#define SMBUS0_IO_BASE 0x8D0
+static inline void smbus_delay(void)
+{
+ outb(0x80, 0x80);
+}
+
+int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+ unsigned long loops;
+ loops = SMBUS_TIMEOUT;
+ do {
+ unsigned char val;
+ smbus_delay();
+ val = inb(smbus_io_base + SMBHSTSTAT);
+ val &= 0x1f;
+ if (val == 0) {
+ return 0;
+ }
+ outb(val,smbus_io_base + SMBHSTSTAT);
+ } while(--loops);
+ return -2;
+}
+
+int smbus_wait_until_done(unsigned smbus_io_base)
+{
+ unsigned long loops;
+ loops = SMBUS_TIMEOUT;
+ do {
+ unsigned char val;
+ smbus_delay();
+
+ val = inb(smbus_io_base + 0x00);
+ if ( (val & 0xff) != 0x02) {
+ return 0;
+ }
+ } while(--loops);
+ return -3;
+}
+
+int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
+{
+ unsigned char global_status_register;
+ unsigned char byte;
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
+ smbus_delay();
+
+ /* byte data recv */
+ outb(0x05, smbus_io_base + SMBHSTPRTCL);
+ smbus_delay();
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3;
+ }
+
+ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
+
+ /* read results of transaction */
+ byte = inb(smbus_io_base + SMBHSTCMD);
+
+ if (global_status_register != 0x80) { // lose check, otherwise it should be 0
+ return -1;
+ }
+ return byte;
+}
+
+int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
+{
+ unsigned global_status_register;
+
+ outb(val, smbus_io_base + SMBHSTDAT0);
+ smbus_delay();
+
+ /* set the command... */
+ outb(val, smbus_io_base + SMBHSTCMD);
+ smbus_delay();
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
+ smbus_delay();
+
+ /* set up for a byte data write */
+ outb(0x04, smbus_io_base + SMBHSTPRTCL);
+ smbus_delay();
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3;
+ }
+ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
+
+ if (global_status_register != 0x80) {
+ return -1;
+ }
+ return 0;
+}
+
+static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+ unsigned char global_status_register;
+ unsigned char byte;
+
+ outb(0xff, smbus_io_base + 0x00);
+ smbus_delay();
+ outb(0x20, smbus_io_base + 0x03);
+ smbus_delay();
+
+ outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04);
+ smbus_delay();
+ outb(address & 0xff, smbus_io_base + 0x05);
+ smbus_delay();
+ outb(0x12, smbus_io_base + 0x03);
+ smbus_delay();
+
+int i,j;
+for(i=0;i<0x1000;i++)
+{
+ if (inb(smbus_io_base + 0x00) != 0x08)
+ { smbus_delay();
+ for(j=0;j<0xFFFF;j++);
+ }
+};
+
+ global_status_register = inb(smbus_io_base + 0x00);
+ byte = inb(smbus_io_base + 0x08);
+
+ if (global_status_register != 0x08) { // lose check, otherwise it should be 0
+ print_debug("Fail");print_debug("\r\t");
+ return -1;
+ }
+ print_debug("Success");print_debug("\r\t");
+ return byte;
+}
+
+
+static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
+{
+ unsigned global_status_register;
+
+ outb(val, smbus_io_base + SMBHSTDAT0);
+ smbus_delay();
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
+ smbus_delay();
+
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+ smbus_delay();
+
+ /* set up for a byte data write */
+ outb(0x06, smbus_io_base + SMBHSTPRTCL);
+ smbus_delay();
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3;
+ }
+ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
+
+ if (global_status_register != 0x80) {
+ return -1;
+ }
+ return 0;
+}
+
+
+
static const uint8_t SiS_LPC_init[34][3]={
{0x04, 0xF8, 0x07}, //Reg 0x04
{0x45, 0x00, 0x00}, //Reg 0x45 //Enable Rom Flash
{0xDF, 0x00, 0xAA}, //Reg 0xDF
{0x00, 0x00, 0x00} //End of table
};
+
static const uint8_t SiS_NBPCIE_init[43][3]={
{0x3D, 0x00, 0x00}, //Reg 0x3D
{0x1C, 0xFE, 0x01}, //Reg 0x1C
{0x5E, 0x00, 0x10}, //Reg 0x5E
{0x34, 0x00, 0xD0}, //Reg 0x34
{0xD0, 0x00, 0x01}, //Reg 0xD0
-
{0x4F, 0x00, 0x80}, //Reg 0x4F
{0xA1, 0x00, 0xF4}, //Reg 0xA1
{0xA2, 0x7F, 0x00}, //Reg 0xA2
{0x4F, 0x00, 0x00}, //Reg 0x4F
{0x00, 0x00, 0x00} //End of table
};
+
static const uint8_t SiS_ACPI_init[10][3]={
{0x1B, 0xBF, 0x40}, //Reg 0x1B
{0x84, 0x00, 0x0E}, //Reg 0x84
{0x6F, 0xFF, 0x14}, //Reg 0x6F
{0x00, 0x00, 0x00} //End of table
};
+
static const uint8_t SiS_SBPCIE_init[13][3]={
{0x48, 0x00 ,0x07}, //Reg 0x48
{0x49, 0x00 ,0x06}, //Reg 0x49
{0x00, 0x00, 0x00} //End of table
};
-
-
static const uint8_t SiS_NB_init[56][3]={
{0x04, 0x00 ,0x07}, //Reg 0x04
{0x05, 0x00 ,0x00}, //Reg 0x05 // alex
{0x45, 0x00 ,0xFF}, //Reg 0x45
{0x46, 0x00 ,0x90}, //Reg 0x46
{0x47, 0x00 ,0xA0}, //Reg 0x47
-//{0x4C, 0xFF ,0x09}, //Reg 0x4C // SiS307 enable
+//{0x4C, 0xFF ,0x09}, //Reg 0x4C // SiS307 enable
{0x4E, 0x00 ,0x00}, //Reg 0x4E
{0x4F, 0x00 ,0x02}, //Reg 0x4F
{0x5B, 0x00 ,0x44}, //Reg 0x5B
{0x97, 0x00 ,0x00}, //Reg 0x97
{0x98, 0x00 ,0x00}, //Reg 0x98
{0x99, 0x00 ,0x00}, //Reg 0x99
-
{0x00, 0x00, 0x00} //End of table
};
-
static const uint8_t SiS_NBAGP_init[34][3]={
-{0xCF, 0xDF, 0x00}, //HT issue
+{0xCF, 0xDF, 0x00}, //HT issue
{0x06, 0xDF, 0x20},
{0x1E, 0xDF, 0x20},
{0x50, 0x00, 0x02},
{0xBF, 0xF9, 0x06},
{0xBA, 0x00, 0x61},
{0xBD, 0x7F, 0x80},
-
-
-{0x00, 0x00, 0x00} //End of table
+{0x00, 0x00, 0x00} //End of table
};
static const uint8_t SiS_ACPI_2_init[56][3]={
{0x85, 0x00, 0xB3},
{0x86, 0x00, 0x72},
{0x87, 0x00, 0x40},
-{0x88, 0x00, 0xDE}, // after set mode
+{0x88, 0x00, 0xDE}, // after set mode
{0x89, 0x00, 0xB3},
{0x8A, 0x00, 0x72},
{0x8B, 0x00, 0x40},
{0xA1, 0x00, 0x15},
{0xA2, 0x00, 0x15},
{0xA3, 0x00, 0x15},
-{0x00, 0x00, 0x00} //End of table
+{0x00, 0x00, 0x00} //End of table
};
-
/* In => Share Memory size
=> 00h : 0MBytes
=> 02h : 32MBytes
=> 04h : 128MBytes
=> Others: Reserved
*/
-void Init_Share_Memory(uint8_t ShareSize)
+static void Init_Share_Memory(uint8_t ShareSize)
{
device_t dev;
=> 04h : 512MBytes
=> Others: Reserved
*/
-void Init_Aper_Size(uint8_t AperSize)
+static void Init_Aper_Size(uint8_t AperSize)
{
device_t dev;
uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
}
-void sis_init_stage1(void)
+static void sis_init_stage1(void)
{
device_t dev;
uint8_t temp8;
i++;
};
// ========================== NBPCIE =============================
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit
temp8 = pci_read_config8(dev, 0x4C);
GUI_En = temp8 & 0x10;
pci_write_config8(dev, 0x4C, temp8 & (!0x10));
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, 0x0004), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0);
i=0;
while(SiS_NBPCIE_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
i++;
};
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit
temp8 = pci_read_config8(dev, 0x4C);
pci_write_config8(dev, 0x4C, temp8 | GUI_En);
- return;
+ return;
}
-void sis_init_stage2(void)
+static void sis_init_stage2(void)
{
- device_t dev;
- msr_t msr;
+ device_t dev;
+ msr_t msr;
int i;
uint8_t temp8;
uint16_t temp16;
// ========================== NB =============================
- printk_debug("Init NorthBridge sis761 -------->\n");
+ printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n");
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
msr = rdmsr(0xC001001A);
- printk_debug("Memory Top Bound %lx\n",msr.lo );
+ printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo );
temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
temp16=0x0001<<(temp16-1);
temp16<<=8;
- printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
+ printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
pci_write_config8(dev, 0x7F, 0x08); // ACPI Base
outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function
// ========================== ACPI =============================
i=0;
- printk_debug("Init ACPI -------->\n");
+ printk(BIOS_DEBUG, "Init ACPI -------->\n");
do
{ temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
temp8 &= SiS_ACPI_2_init[i][1];
}while(SiS_ACPI_2_init[i][0] != 0);
// ========================== Misc =============================
- printk_debug("Init Misc -------->\n");
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_ISA), 0);
- // PCI Device Enable
- pci_write_config8(dev, 0x7C, 0x03); // bit0=0 : enable audio controller(), bit1=1 : disable modem
- pci_write_config8(dev, 0x76, pci_read_config8(dev, 0x76)|0x30); // SM bus enable, PCIEXP Controller 1 and 2 disable
- pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable
+ printk(BIOS_DEBUG, "Init Misc -------->\n");
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
+ /* R77h Internal PCI Device Enable 1 (Power On Value = 0h)
+ * bit5 : USB Emulation (1=enable)
+ * bit3 : Internal Keyboard Controller Port Access Control enable (1=enable)
+ * bit2 : Reserved
+ * bit1 : Mask USB A20M# Event (1:K8, 0:P4/K7)
+ */
+ pci_write_config8(dev, 0x77, 0x2E);
+
+ /* R7Ch Internal PCI Device Enable 2 (Power On Value = 0h)
+ * bit4 : SATA Controller Enable (0=enable)
+ * bit3 : IDE Controller Enable (0=enable)
+ * bit2 : MAC Controller Enable (0=enable)
+ * bit1 : MODEM Controller Enable (1=disable)
+ * bit0 : AC97 Controller Enable (1=disable)
+ */
+ pci_write_config8(dev, 0x7C, 0x03);
+
+ /* R7Eh Enable Azalia (Power On Value = 08h)
+ * bit3 : Azalia Controller Enable (0=enable)
+ */
+ pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable
temp8=inb(0x878)|0x4; //bit2=1 enable Azalia =0 enable AC97
outb(temp8, 0x878); // ACPI select AC97 or HDA controller
- printk_debug("Audio select %x\n",inb(0x878));
+ printk(BIOS_DEBUG, "Audio select %x\n",inb(0x878));
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA0), 0);
- if(!dev){
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0);
+
+ if (!dev)
print_debug("SiS 1183 does not exist !!");
- }
// SATA Set Mode
pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40);
{
device_t dev;
uint8_t temp8;
- printk_debug("enable_smbus -------->\n");
+ printk(BIOS_DEBUG, "enable_smbus -------->\n");
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
temp8=pci_read_config8(dev, 0x76); // Enable SMBUS
pci_write_config8(dev, 0x76, temp8 | 0x03);
- printk_debug("enable_smbus <--------\n");
+ printk(BIOS_DEBUG, "enable_smbus <--------\n");
}
-static int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
}
-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
}
projects / coreboot.git / blobdiff