Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / southbridge / ricoh / rl5c476 / rl5c476.c

diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index 799619775e27d5fbeb282e48771bead9f7e59305..70d74f5fabb8d77f445cf8630d21f19d54c8f3ec 100644 (file)
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -1,10 +1,12 @@
 /*
- * (C) Copyright 2004-2005 Nick Barker <nick.barker@btinternet.com>
+ * This file is part of the coreboot project.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * Copyright (C) 2004-2005 Nick Barker <nick.barker@btinternet.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -13,8 +15,7 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 #include <arch/io.h>
@@ -37,9 +38,9 @@ static void rl5c476_init(device_t dev)
        unsigned char *base;
 
        /* cardbus controller function 1 for CF Socket */
-       printk_debug("Ricoh RL5c476: Initializing.\n");
+       printk(BIOS_DEBUG, "Ricoh RL5c476: Initializing.\n");
 
-       printk_debug("CF Base = %0x\n",cf_base);
+       printk(BIOS_DEBUG, "CF Base = %0x\n",cf_base);
 
        /* misc control register */
        pci_write_config16(dev,0x82,0x00a0);
@@ -47,10 +48,10 @@ static void rl5c476_init(device_t dev)
        /* set up second slot as compact flash port if asked to do so */
 
        if (!enable_cf_boot) {
-               printk_debug("CF boot not enabled.\n");
+               printk(BIOS_DEBUG, "CF boot not enabled.\n");
                return;
        }
-       
+
        if (PCI_FUNC(dev->path.pci.devfn) != 1) {
                // Only configure if second CF slot.
                return;
@@ -151,28 +152,28 @@ static void rl5c476_init(device_t dev)
         */
        unsigned char *cptr;
        cptr = (unsigned char *)(cf_base + 0x200);
-       printk_debug("CF Config = %x\n",*cptr);
+       printk(BIOS_DEBUG, "CF Config = %x\n",*cptr);
 
-       /* Set CF to decode 16 IO bytes on any 16 byte boundary - 
-        * rely on the io windows of the bridge set up above to 
+       /* Set CF to decode 16 IO bytes on any 16 byte boundary -
+        * rely on the io windows of the bridge set up above to
         * map those bytes into the addresses for IDE controller 3
         * (0x1e8 - 0x1ef and 0x3ed - 0x3ee)
         */
        *cptr = 0x41;
 }
 
-void rl5c476_read_resources(device_t dev)
+static void rl5c476_read_resources(device_t dev)
 {
 
        struct resource *resource;
 
-        /* For CF socket we need an extra memory window for 
+        /* For CF socket we need an extra memory window for
          * the control structure of the CF itself
          */
-       if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ 
+       if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
                /* fake index as it isn't in PCI config space */
                resource = new_resource(dev, 1);
-               resource->flags |= IORESOURCE_MEM ;
+               resource->flags |= IORESOURCE_MEM;
                resource->size = 0x1000;
                resource->align = resource->gran = 12;
                resource->limit= 0xffff0000;
@@ -180,15 +181,15 @@ void rl5c476_read_resources(device_t dev)
        cardbus_read_resources(dev);
 }
 
-void rl5c476_set_resources(device_t dev)
+static void rl5c476_set_resources(device_t dev)
 {
        struct resource *resource;
-       printk_debug("%s In set resources \n",dev_path(dev));
+       printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
        if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
                resource = find_resource(dev,1);
                if( !(resource->flags & IORESOURCE_STORED) ){
                        resource->flags |= IORESOURCE_STORED ;
-                       printk_debug("%s 1 ==> %x\n",dev_path(dev),resource->base); 
+                       printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);
                        cf_base = resource->base;
                }
        }
@@ -211,12 +212,10 @@ static const struct pci_driver ricoh_rl5c476_driver __pci_driver = {
        .device = PCI_DEVICE_ID_RICOH_RL5C476,
 };
 
-void southbridge_init(device_t dev)
+static void southbridge_init(device_t dev)
 {
-
        struct southbridge_ricoh_rl5c476_config *conf = dev->chip_info;
        enable_cf_boot = conf->enable_cf;
-
 }
 
 struct chip_operations southbridge_ricoh_rl5c476_ops = {