Please find appended. This patch gets rid of the %gs magic altogether,

[coreboot.git] / src / southbridge / nvidia / mcp55 / mcp55_early_setup_car.c

diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index fb84f5a36dc9f288092b600fad09233abc7e433b..e01630dc050a3b0b24edc7d27617be32100e332c 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -267,8 +267,13 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
        RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
        RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
        RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
-
-       RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
+       /* The following operation hangs when performed via MMCFG:
+            pci_read_config32(romcc): 00010000:0078: 20040000
+            setup_resource_map_x_offset: 10000, 78: 20040000
+            pci_write_config32(romcc): 00010000:0078: 19040000
+            (hang)
+          Response missing? */
+       /* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */
 
 #if MCP55_USE_AZA == 1
        RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,