Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / southbridge / intel / pxhd / pxhd_bridge.c

diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c
index 5913063606890a1c10e864c048cdd5aff785f21b..683ff20013b8148dce27033ad86fdae526b0d71f 100644 (file)
--- a/src/southbridge/intel/pxhd/pxhd_bridge.c
+++ b/src/southbridge/intel/pxhd/pxhd_bridge.c
@@ -8,6 +8,7 @@
 #include <device/pci_ops.h>
 #include <device/pcix.h>
 #include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
 #include <delay.h>
 #include "pxhd.h"
 
@@ -21,7 +22,7 @@ static void pxhd_enable(device_t dev)
        }
        bridge = dev_find_slot(dev->bus->secondary, dev->path.pci.devfn & ~1);
        if (!bridge) {
-               printk_err("Cannot find bridge for ioapic: %s\n",
+               printk(BIOS_ERR, "Cannot find bridge for ioapic: %s\n",
                           dev_path(dev));
                return;
        }
@@ -47,7 +48,7 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
        if(bus_100Mhz) {
                uint16_t word;
 
-               printk_debug("setting pxhd bus to 100 Mhz\n");
+               printk(BIOS_DEBUG, "setting pxhd bus to 100 Mhz\n");
                /* set to pcix 100 mhz */
                word = pci_read_config16(dev, 0x40);
                word &= ~(3 << 14);
@@ -55,29 +56,29 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
                word &= ~(3 << 9);
                word |= (2 << 9);
                pci_write_config16(dev, 0x40, word);
-               
+
                /* reset the bus to make the new frequencies effective */
                pci_bus_reset(&dev->link[0]);
-       }       
+       }
        return pcix_scan_bridge(dev, max);
 }
 static void pcix_init(device_t dev)
 {
-       uint32_t dword;
-       uint16_t word;
-       uint8_t byte;
-       int nmi_option;
-
        /* Bridge control ISA enable */
        pci_write_config8(dev, 0x3e, 0x07);
 
+#warning "Please review lots of dead code here."
 #if 0
+       int nmi_option;
+       uint32_t dword;
+       uint16_t word;
+       uint8_t byte;
 
        /* Enable memory write and invalidate ??? */
        byte = pci_read_config8(dev, 0x04);
         byte |= 0x10;
         pci_write_config8(dev, 0x04, byte);
-       
+
        /* Set drive strength */
        word = pci_read_config16(dev, 0xe0);
         word = 0x0404;
@@ -85,7 +86,7 @@ static void pcix_init(device_t dev)
        word = pci_read_config16(dev, 0xe4);
         word = 0x0404;
         pci_write_config16(dev, 0xe4, word);
-       
+
        /* Set impedance */
        word = pci_read_config16(dev, 0xe8);
         word = 0x0404;
@@ -95,7 +96,7 @@ static void pcix_init(device_t dev)
        word = pci_read_config16(dev, 0x4c);
         word |= 1;
         pci_write_config16(dev, 0x4c, word);
-       
+
        /* Set split transaction limits */
        word = pci_read_config16(dev, 0xa8);
         pci_write_config16(dev, 0xaa, word);
@@ -107,12 +108,12 @@ static void pcix_init(device_t dev)
        dword = pci_read_config32(dev, 0x04);
         dword |= (1<<8);
         pci_write_config32(dev, 0x04, dword);
-       
+
        /* system and error parity enable */
        dword = pci_read_config32(dev, 0x3c);
         dword |= (3<<16);
         pci_write_config32(dev, 0x3c, dword);
-       
+
        /* NMI enable */
        nmi_option = NMI_OFF;
        get_option(&nmi_option, "nmi");
@@ -121,7 +122,7 @@ static void pcix_init(device_t dev)
                dword |= (1<<0);
                pci_write_config32(dev, 0x44, dword);
        }
-       
+
        /* Set up CRC flood enable */
        dword = pci_read_config32(dev, 0xc0);
        if(dword) {  /* do device A only */
@@ -132,7 +133,7 @@ static void pcix_init(device_t dev)
                dword |= (1<<1);
                pci_write_config32(dev, 0xc8, dword);
        }
-       
+
        return;
 #endif
 }
@@ -159,68 +160,22 @@ static const struct pci_driver pcix_driver2 __pci_driver = {
         .device = 0x032a,
 };
 
-#define ALL            (0xff << 24)
-#define NONE           (0)
-#define DISABLED       (1 << 16)
-#define ENABLED                (0 << 16)
-#define TRIGGER_EDGE   (0 << 15)
-#define TRIGGER_LEVEL  (1 << 15)
-#define POLARITY_HIGH  (0 << 13)
-#define POLARITY_LOW   (1 << 13)
-#define PHYSICAL_DEST  (0 << 11)
-#define LOGICAL_DEST   (1 << 11)
-#define ExtINT         (7 << 8)
-#define NMI            (4 << 8)
-#define SMI            (2 << 8)
-#define INT            (1 << 8)
-       /* IO-APIC virtual wire mode configuration */
-       /* mask, trigger, polarity, destination, delivery, vector */
-
-static void setup_ioapic(device_t dev)
-{
-       int i;
-       unsigned long value_low, value_high;
-       unsigned long ioapic_base;
-       volatile unsigned long *l;
-       unsigned interrupts;
-
-       ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-       l = (unsigned long *) ioapic_base;
-
-       /* Enable front side bus delivery */
-       l[0] = 0x03;
-       l[4] = 1;
-
-       l[0] = 0x01;
-       interrupts = (l[04] >> 16) & 0xff;
-       for (i = 0; i < interrupts; i++) {
-               l[0] = (i * 2) + 0x10;
-               l[4] = DISABLED;
-               value_low = l[4];
-               l[0] = (i * 2) + 0x11;
-               l[4] = NONE; /* Should this be an address? */
-               value_high = l[4];
-               if (value_low == 0xffffffff) {
-                       printk_warning("IO APIC not responding.\n");
-                       return;
-               }
-       }
-}
-
 static void ioapic_init(device_t dev)
 {
-       uint32_t value;
+       uint32_t value, ioapic_base;
        /* Enable bus mastering so IOAPICs work */
        value = pci_read_config16(dev, PCI_COMMAND);
        value |= PCI_COMMAND_MASTER;
        pci_write_config16(dev, PCI_COMMAND, value);
 
-       setup_ioapic(dev);
+       ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+       setup_ioapic(ioapic_base, 0); // Don't rename IOAPIC ID
 }
 
 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-       pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, 
+       pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
                ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
@@ -242,14 +197,14 @@ static const struct pci_driver ioapic_driver __pci_driver = {
        .ops    = &ioapic_ops,
        .vendor = PCI_VENDOR_ID_INTEL,
        .device = 0x0326,
-       
+
 };
 
 static const struct pci_driver ioapic2_driver __pci_driver = {
        .ops    = &ioapic_ops,
        .vendor = PCI_VENDOR_ID_INTEL,
        .device = 0x0327,
-       
+
 };
 
 struct chip_operations southbridge_intel_pxhd_ops = {