Convert some comments to proper Doxygen syntax.

[coreboot.git] / src / southbridge / intel / i82870 / p64h2_ioapic.c

diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c
index d1c5f4955266641b7bc2546ae59bada600b8e40c..8af57beed7298b4d641beaef05f080b8982de151 100644 (file)
--- a/src/southbridge/intel/i82870/p64h2_ioapic.c
+++ b/src/southbridge/intel/i82870/p64h2_ioapic.c
@@ -18,15 +18,15 @@ static void p64h2_ioapic_enable(device_t dev)
     pci_write_config16(dev, PCI_COMMAND, command);
 }
 
-//----------------------------------------------------------------------------------
-// Function:        p64h2_ioapic_init
-// Parameters:      dev - PCI bus/device/function of P64H2 IOAPIC
-//                  NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0
-// Return Value:    None
-// Description:     Configure one of the IOAPICs in a P64H2.
-//                  Note that a PCI bus scan will detect both IOAPICs, so this function
-//                  will be called twice for each P64H2 in the system.
-//
+/**
+ * Configure one of the IOAPICs in a P64H2.
+ *
+ * Note that a PCI bus scan will detect both IOAPICs, so this function
+ * will be called twice for each P64H2 in the system.
+ *
+ * @param dev PCI bus/device/function of P64H2 IOAPIC.
+ *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
+ */
 static void p64h2_ioapic_init(device_t dev)
 {
     uint32_t memoryBase;
@@ -39,9 +39,9 @@ static void p64h2_ioapic_init(device_t dev)
     num_p64h2_ioapics++;
 
     // A note on IOAPIC addresses:
-    //  0 and 1 are used for the local APICs of the dual virtual 
+    //  0 and 1 are used for the local APICs of the dual virtual
        //      (hyper-threaded) CPUs of physical CPU 0 (mainboard/Config.lb).
-    //  6 and 7 are used for the local APICs of the dual virtual 
+    //  6 and 7 are used for the local APICs of the dual virtual
        //      (hyper-threaded) CPUs of physical CPU 1 (mainboard/Config.lb).
     //  2 is used for the IOAPIC in the 82801 Southbridge (hard-coded in i82801xx_lpc.c)
 
@@ -62,9 +62,9 @@ static void p64h2_ioapic_init(device_t dev)
     pIndexRegister  = (volatile uint32_t*) memoryBase;
     pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
 
-    printk_debug("IOAPIC %d at %02x:%02x.%01x  MBAR = %x DataAddr = %x\n",
-                 apic_id, dev->bus->secondary, PCI_SLOT(dev->path.u.pci.devfn), 
-                 PCI_FUNC(dev->path.u.pci.devfn), pIndexRegister, pWindowRegister);
+    printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
+                 apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
+                 PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
 
     apic_id <<= 24;             // Convert ID to bitmask
 
@@ -72,13 +72,13 @@ static void p64h2_ioapic_init(device_t dev)
     *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id;   // Set the ID
 
     if ((*pWindowRegister & (0xF<<24)) != apic_id)
-        die("p64h2_ioapic_init failed"); 
+        die("p64h2_ioapic_init failed");
 
     *pIndexRegister  = 3;   // Select Boot Configuration register
     *pWindowRegister |= 1;  // Use Processor System Bus to deliver interrupts
 
     if (!(*pWindowRegister & 1))
-        die("p64h2_ioapic_init failed"); 
+        die("p64h2_ioapic_init failed");
 }
 
 static struct device_operations ioapic_ops = {
@@ -90,7 +90,7 @@ static struct device_operations ioapic_ops = {
         .enable   = p64h2_ioapic_enable,
 };
 
-static struct pci_driver ioapic_driver __pci_driver = {
+static const struct pci_driver ioapic_driver __pci_driver = {
         .ops    = &ioapic_ops,
         .vendor = PCI_VENDOR_ID_INTEL,
         .device = PCI_DEVICE_ID_INTEL_82870_1E0,