This patch halts the tco timer early in the boot process on all ICH series southbridges.

[coreboot.git] / src / southbridge / intel / i82801xx / i82801xx.h

diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801xx/i82801xx.h
index e5b2d33ba4cde93cde360b3147c4d332dd4adb38..27ce21c207de6486a3cffbd070c89440b7f55e22 100644 (file)
--- a/src/southbridge/intel/i82801xx/i82801xx.h
+++ b/src/southbridge/intel/i82801xx/i82801xx.h
@@ -34,6 +34,7 @@ extern void i82801xx_enable(device_t dev);
 #define GEN_PMCON_3            0xa4
 
 #define PMBASE                 0x40
+#define PMBASE_ADDR            0x0400 /* ACPI Base Address Register */
 #define ACPI_CNTL              0x44
 #define BIOS_CNTL              0x4E
 #define GPIO_BASE_ICH0_5       0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
@@ -68,6 +69,9 @@ extern void i82801xx_enable(device_t dev);
 #define MTT                    0x70
 #define PCI_MAST_STS           0x82
 
+#define TCOBASE                        0x60 /* TCO Base Address Register */
+#define TCO1_CNT               0x08 /* TCO1 Control Register */
+
 /* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD       (1 << 2)
 #define RTC_POWER_FAILED       (1 << 1)