printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / southbridge / intel / i82801gx / i82801gx_usb.c

diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb.c b/src/southbridge/intel/i82801gx/i82801gx_usb.c
index d8024777f703efb9a38000430500cc9e9d78f0f6..00fddf7c65d6d7ee55f7d987b04539aa70def43f 100644 (file)
--- a/src/southbridge/intel/i82801gx/i82801gx_usb.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb.c
@@ -1,12 +1,12 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 coresystems GmbH
+ * Copyright (C) 2008-2009 coresystems GmbH
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -30,18 +30,37 @@ static void usb_init(struct device *dev)
        u8 reg8;
 
        /* USB Specification says the device must be Bus Master */
-       printk_debug("UHCI: Setting up controller.. ");
+       printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
 
        reg32 = pci_read_config32(dev, PCI_COMMAND);
        pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
 
+       // Erratum
+       pci_write_config8(dev, 0xca, 0x00);
+
+       // Yes. Another Erratum
        reg8 = pci_read_config8(dev, 0xca);
        reg8 |= (1 << 0);
        pci_write_config8(dev, 0xca, reg8);
 
-       printk_debug("done.\n");
+       printk(BIOS_DEBUG, "done.\n");
+}
+
+static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+       if (!vendor || !device) {
+               pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+                               pci_read_config32(dev, PCI_VENDOR_ID));
+       } else {
+               pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+                               ((device & 0xffff) << 16) | (vendor & 0xffff));
+       }
 }
 
+static struct pci_operations usb_pci_ops = {
+       .set_subsystem    = usb_set_subsystem,
+};
+
 static struct device_operations usb_ops = {
        .read_resources         = pci_dev_read_resources,
        .set_resources          = pci_dev_set_resources,
@@ -49,31 +68,33 @@ static struct device_operations usb_ops = {
        .init                   = usb_init,
        .scan_bus               = 0,
        .enable                 = i82801gx_enable,
+       .ops_pci                = &usb_pci_ops,
 };
 
 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
 static const struct pci_driver i82801gb_usb1 __pci_driver = {
        .ops    = &usb_ops,
        .vendor = PCI_VENDOR_ID_INTEL,
-       .device = PCI_DEVICE_ID_INTEL_82801GB_USB1,
+       .device = 0x27c8,
 };
 
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
 static const struct pci_driver i82801gb_usb2 __pci_driver = {
        .ops    = &usb_ops,
        .vendor = PCI_VENDOR_ID_INTEL,
-       .device = PCI_DEVICE_ID_INTEL_82801GB_USB2,
+       .device = 0x27c9,
 };
 
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
 static const struct pci_driver i82801gb_usb3 __pci_driver = {
        .ops    = &usb_ops,
        .vendor = PCI_VENDOR_ID_INTEL,
-       .device = PCI_DEVICE_ID_INTEL_82801GB_USB3,
+       .device = 0x27ca,
 };
 
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
 static const struct pci_driver i82801gb_usb4 __pci_driver = {
        .ops    = &usb_ops,
        .vendor = PCI_VENDOR_ID_INTEL,
-       .device = PCI_DEVICE_ID_INTEL_82801GB_USB4,
+       .device = 0x27cb,
 };
-
-