printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / southbridge / intel / i82801gx / i82801gx_pcie.c

diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
index d7655c5ea592546c5cf20872062e3cd51d15ec60..d69bc6d07d10a67f16198a874ad34d299aed1cfd 100644 (file)
--- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
@@ -28,8 +28,8 @@ static void pci_init(struct device *dev)
        u16 reg16;
        u32 reg32;
 
-       printk_debug("Initializing ICH7 PCIe bridge.\n");
-       
+       printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
+
        /* Enable Bus Master */
        reg32 = pci_read_config32(dev, PCI_COMMAND);
        reg32 |= PCI_COMMAND_MASTER;
@@ -75,15 +75,15 @@ static void pci_init(struct device *dev)
        reg16 |= (1 << 6);
        pci_write_config16(dev, 0x50, reg16);
 
-#if EVEN_MORE_DEBUG
+#ifdef EVEN_MORE_DEBUG
        reg32 = pci_read_config32(dev, 0x20);
-       printk_spew("    MBL    = 0x%08x\n", reg32);
+       printk(BIOS_SPEW, "    MBL    = 0x%08x\n", reg32);
        reg32 = pci_read_config32(dev, 0x24);
-       printk_spew("    PMBL   = 0x%08x\n", reg32);
+       printk(BIOS_SPEW, "    PMBL   = 0x%08x\n", reg32);
        reg32 = pci_read_config32(dev, 0x28);
-       printk_spew("    PMBU32 = 0x%08x\n", reg32);
+       printk(BIOS_SPEW, "    PMBU32 = 0x%08x\n", reg32);
        reg32 = pci_read_config32(dev, 0x2c);
-       printk_spew("    PMLU32 = 0x%08x\n", reg32);
+       printk(BIOS_SPEW, "    PMLU32 = 0x%08x\n", reg32);
 #endif
 
        /* Clear errors in status registers */