/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2008 coresystems GmbH
+ * Copyright (C) 2008-2009 coresystems GmbH
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include "i82801gx.h"
static void pci_init(struct device *dev)
{
u16 reg16;
+ u8 reg8;
-#if 0
- /* Commented out for now because it will break on some machines. */
- /* Set latency timer to 32. */
- pci_write_config16(dev, 0x1b, 0x20);
-#endif
+ /* Enable Bus Master */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MASTER;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /* This device has no interrupt */
+ pci_write_config8(dev, INTR, 0xff);
- /* disable parity error response */
- reg16 = pci_read_config16(dev, 0x3e);
+ /* disable parity error response and SERR */
+ reg16 = pci_read_config16(dev, BCTRL);
reg16 &= ~(1 << 0);
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 &= ~(1 << 1);
+ pci_write_config16(dev, BCTRL, reg16);
+
+ /* Master Latency Count must be set to 0x04! */
+ reg8 = pci_read_config8(dev, SMLT);
+ reg8 &= 0x07;
+ reg8 |= (0x04 << 3);
+ pci_write_config8(dev, SMLT, reg8);
+
+ /* Will this improve throughput of bus masters? */
+ pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
- reg16 = pci_read_config16(dev, 0x06);
- reg16 |= 0xf900;
- pci_write_config16(dev, 0x06, reg16);
+ reg16 = pci_read_config16(dev, PSTS);
+ //reg16 |= 0xf900;
+ pci_write_config16(dev, PSTS, reg16);
- reg16 = pci_read_config16(dev, 0x1e);
- reg16 |= 0xf900;
- pci_write_config16(dev, 0x1e, reg16);
+ reg16 = pci_read_config16(dev, SECSTS);
+ // reg16 |= 0xf900;
+ pci_write_config16(dev, SECSTS, reg16);
}
+#undef PCI_BRIDGE_UPDATE_COMMAND
static void ich_pci_dev_enable_resources(struct device *dev)
{
const struct pci_operations *ops;
/* Set the subsystem vendor and device id for mainboard devices */
ops = ops_pci(dev);
if (dev->on_mainboard && ops && ops->set_subsystem) {
- printk_debug("%s subsystem <- %02x/%02x\n",
- dev_path(dev),
- MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
- MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
- ops->set_subsystem(dev,
- MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
- MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+ printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
+ dev_path(dev),
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+ ops->set_subsystem(dev,
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
}
-#if 0
- /* If we write to PCI_COMMAND, on some systems
+ command = pci_read_config16(dev, PCI_COMMAND);
+ command |= dev->command;
+#ifdef PCI_BRIDGE_UPDATE_COMMAND
+ /* If we write to PCI_COMMAND, on some systems
* this will cause the ROM and APICs not being visible
* anymore.
*/
- command = pci_read_config16(dev, PCI_COMMAND);
- command |= dev->command;
- printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
+ printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
+#else
+ printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
#endif
}
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link[0].bridge_ctrl;
ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
- printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
/* This is the reason we need our own pci_bus_enable_resources */
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
-#if 0
- /* Currently disabled because it causes a "BAR 9" memory resource
- * conflict:
- */
- u32 pci_id;
-
- printk_debug("Setting PCI bridge subsystem ID\n");
- pci_id = pci_read_config32(dev, 0);
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_id );
-#endif
+ /* NOTE: This is not the default position! */
+ if (!vendor || !device) {
+ pci_write_config32(dev, 0x54,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, 0x54,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
}
static struct pci_operations pci_ops = {
.ops_pci = &pci_ops,
};
-
/* Desktop */
+/* 82801BA/CA/DB/EB/ER/FB/FR/FW/FRW/GB/GR/GDH/HB/IB/6300ESB/i3100 */
static const struct pci_driver i82801g_pci __pci_driver = {
.ops = &device_ops,
- .vendor = 0x8086,
+ .vendor = PCI_VENDOR_ID_INTEL,
.device = 0x244e,
};
/* Mobile / Ultra Mobile */
+/* 82801BAM/CAM/DBL/DBM/FBM/GBM/GHM/GU/HBM/HEM */
static const struct pci_driver i82801gmu_pci __pci_driver = {
.ops = &device_ops,
- .vendor = 0x8086,
+ .vendor = PCI_VENDOR_ID_INTEL,
.device = 0x2448,
};
-
projects / coreboot.git / blobdiff