#include <pc80/i8259.h>
#include <arch/io.h>
#include "i82801gx.h"
-#include "i82801gx_power.h"
#define NMI_OFF 0
{
int i;
u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
- volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
+ volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+ volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*ioapic_index = 0;
reg32 = *ioapic_data;
- printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+ printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
if (reg32 != (1 << 25))
die("APIC Error\n");
- printk_spew("Dumping IOAPIC registers\n");
+ printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
for (i=0; i<3; i++) {
*ioapic_index = i;
- printk_spew(" reg 0x%04x:", i);
+ printk(BIOS_SPEW, " reg 0x%04x:", i);
reg32 = *ioapic_data;
- printk_spew(" 0x%08x\n", reg32);
+ printk(BIOS_SPEW, " 0x%08x\n", reg32);
}
*ioapic_index = 3; /* Select Boot Configuration register. */
u8 reg8;
u16 reg16, pmbase;
u32 reg32;
- char *state;
+ const char *state;
/* Get the chip configuration */
config_t *config = dev->chip_info;
reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
pci_write_config8(dev, GEN_PMCON_3, reg8);
- printk_info("Set power %s after power failure.\n", state);
+ printk(BIOS_INFO, "Set power %s after power failure.\n", state);
/* Set up NMI on errors. */
reg8 = inb(0x61);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
- printk_info ("NMI sources enabled.\n");
+ printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */
} else {
- printk_info ("NMI sources disabled.\n");
+ printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
}
outb(reg8, 0x70);
/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
reg16 = pci_read_config16(dev, GEN_PMCON_1);
- reg16 &= ~((3 << 0) | (1 << 10));
- reg16 |= (1 << 3) | (1 << 5);
- reg16 |= (1 << 2); // CLKRUN_EN
+ reg16 &= ~(3 << 0); // SMI# rate 1 minute
+ reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
+ reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
+ reg16 |= (1 << 5); // CPUSLP_EN Desktop only
+ // another laptop wants this?
+ // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
+ reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
#if DEBUG_PERIODIC_SMIS
/* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
* periodic SMIs.
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); // PM1_CNT
-#if 0
-#if CONFIG_HAVE_ACPI_RESUME
- acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0;
- printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n",
- reg32, acpi_slp_type);
-#endif
-#endif
- reg32 |= (1 << 1); // enable C3->C0 transition on bus master
- reg32 |= 1; // SCI_EN
+
+ reg32 &= ~(7 << 10); // SLP_TYP
+ reg32 |= (1 << 1); // enable C3->C0 transition on bus master
+ reg32 |= (1 << 0); // SCI_EN
outl(reg32, pmbase + 0x04);
}
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
}
- printk_debug("rtc_failed = 0x%x\n", rtc_failed);
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
rtc_init(rtc_failed);
}
u32 reg32;
/* Move HPET to default address 0xfed00000 and enable it */
- reg32 = RCBA32(0x3404);
+ reg32 = RCBA32(HPTC);
reg32 |= (1 << 7); // HPET Address Enable
reg32 &= ~(3 << 0);
- RCBA32(0x3404) = reg32;
+ RCBA32(HPTC) = reg32;
}
static void enable_clock_gating(void)
u32 reg32;
/* Enable Clock Gating for most devices */
- reg32 = RCBA32(0x341c);
+ reg32 = RCBA32(CG);
reg32 |= (1 << 31); // LPC clock gating
reg32 |= (1 << 30); // PATA clock gating
// SATA clock gating
reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
reg32 |= (1 << 23); // AC97 clock gating
- reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating
+ reg32 |= (1 << 19); // USB EHCI clock gating
reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
reg32 |= (1 << 2); // PCIe clock gating;
- RCBA32(0x341c) = reg32;
+ reg32 &= ~(1 << 20); // No static clock gating for USB
+ reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating
+ RCBA32(CG) = reg32;
}
#if CONFIG_HAVE_SMI_HANDLER
#endif
#if ENABLE_ACPI_MODE_IN_COREBOOT
- printk_debug("Enabling ACPI via APMC:\n");
+ printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
- printk_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#else
- printk_debug("Disabling ACPI via APMC:\n");
+ printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(0x1e, 0xb2); // Disable ACPI mode
- printk_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
/* Don't allow evil boot loaders, kernels, or
* userspace applications to deceive us:
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
- printk_debug("Locking BIOS to RO... ");
+ printk(BIOS_DEBUG, "Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
- printk_debug("ok.\n");
+ printk(BIOS_DEBUG, "ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
- printk_debug("Writing:\n");
+ printk(BIOS_DEBUG, "Writing:\n");
*(volatile u8 *)0xfff00000 = 0x00;
- printk_debug("Testing:\n");
+ printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
- printk_debug("Done.\n");
+ printk(BIOS_DEBUG, "Done.\n");
#endif
}
#endif
RCBA16(SPIBASE + 2) = spicontrol;
}
-static void i82801gx_fixups(void)
+static void i82801gx_fixups(struct device *dev)
{
/* This needs to happen after PCI enumeration */
RCBA32(0x1d40) |= 1;
+
+ /* USB Transient Disconnect Detect:
+ * Prevent a SE0 condition on the USB ports from being
+ * interpreted by the UHCI controller as a disconnect
+ */
+ pci_write_config8(dev, 0xad, 0x3);
}
static void lpc_init(struct device *dev)
{
- printk_debug("i82801gx: lpc_init\n");
+ printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
setup_i8259();
/* The OS should do this? */
- // i8259_configure_irq_trigger(9, 1);
+ /* Interrupt 9 should be level triggered (SCI) */
+ i8259_configure_irq_trigger(9, 1);
#if CONFIG_HAVE_SMI_HANDLER
i82801gx_lock_smm(dev);
i82801gx_spi_init();
- i82801gx_fixups();
+ i82801gx_fixups(dev);
}
static void i82801gx_lpc_read_resources(device_t dev)
projects / coreboot.git / blobdiff