/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2008 coresystems GmbH
+ * Copyright (C) 2008-2009 coresystems GmbH
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
+#include <pc80/i8259.h>
#include <arch/io.h>
#include "i82801gx.h"
#define NMI_OFF 0
+typedef struct southbridge_intel_i82801gx_config config_t;
+
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
static void i82801gx_pirq_init(device_t dev)
{
- pci_write_config8(dev, PIRQA_ROUT, 0x85);
- pci_write_config8(dev, PIRQB_ROUT, 0x87);
- pci_write_config8(dev, PIRQC_ROUT, 0x86);
- pci_write_config8(dev, PIRQD_ROUT, 0x87);
-
- pci_write_config8(dev, PIRQE_ROUT, 0x80);
- pci_write_config8(dev, PIRQF_ROUT, 0x80);
- pci_write_config8(dev, PIRQG_ROUT, 0x80);
- pci_write_config8(dev, PIRQH_ROUT, 0x85);
+ device_t irq_dev;
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
+ pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+ pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+ pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+ pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+
+ pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+ pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+ pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+ pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+
+ /* Eric Biederman once said we should let the OS do this.
+ * I am not so sure anymore he was right.
+ */
+
+ for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin=0, int_line=0;
+
+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+ continue;
+
+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+
+ switch (int_pin) {
+ case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+ case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+ case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+ case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ }
+
+ if (!int_line)
+ continue;
+
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ }
+}
+
+static void i82801gx_gpi_routing(device_t dev)
+{
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+ u32 reg32 = 0;
+
+ /* An array would be much nicer here, or some
+ * other method of doing this.
+ */
+ reg32 |= (config->gpi0_routing & 0x03) << 0;
+ reg32 |= (config->gpi1_routing & 0x03) << 2;
+ reg32 |= (config->gpi2_routing & 0x03) << 4;
+ reg32 |= (config->gpi3_routing & 0x03) << 6;
+ reg32 |= (config->gpi4_routing & 0x03) << 8;
+ reg32 |= (config->gpi5_routing & 0x03) << 10;
+ reg32 |= (config->gpi6_routing & 0x03) << 12;
+ reg32 |= (config->gpi7_routing & 0x03) << 14;
+ reg32 |= (config->gpi8_routing & 0x03) << 16;
+ reg32 |= (config->gpi9_routing & 0x03) << 18;
+ reg32 |= (config->gpi10_routing & 0x03) << 20;
+ reg32 |= (config->gpi11_routing & 0x03) << 22;
+ reg32 |= (config->gpi12_routing & 0x03) << 24;
+ reg32 |= (config->gpi13_routing & 0x03) << 26;
+ reg32 |= (config->gpi14_routing & 0x03) << 28;
+ reg32 |= (config->gpi15_routing & 0x03) << 30;
+
+ pci_write_config32(dev, 0xb8, reg32);
}
static void i82801gx_power_options(device_t dev)
reg8 |= 1;
}
reg8 |= (3 << 4); /* avoid #S4 assertions */
+ reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
pci_write_config8(dev, GEN_PMCON_3, reg8);
printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off");
// Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
reg16 = pci_read_config16(dev, GEN_PMCON_1);
- reg16 &= ~3;
- reg16 |= (1 << 3) | (1 << 5) | (1 << 10);
+ reg16 &= ~((3 << 0) | (1 << 10));
+ reg16 |= (1 << 3) | (1 << 5);
+ reg16 |= (1 << 2); // CLKRUN_EN
pci_write_config16(dev, GEN_PMCON_1, reg16);
- // Set GPIO13 to SCI (?)
- // This might be board specific
- pci_write_config32(dev, 0xb8, 0x08000000);
+ // Set the board's GPI routing.
+ i82801gx_gpi_routing(dev);
}
-void i82801gx_rtc_init(struct device *dev)
+static void i82801gx_configure_cstates(device_t dev)
+{
+ u8 reg8;
+
+ reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
+ reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
+ pci_write_config8(dev, 0xa9, reg8);
+
+ // Set Deeper Sleep configuration to recommended values
+ reg8 = pci_read_config8(dev, 0xaa);
+ reg8 &= 0xf0;
+ reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us
+ reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us
+ pci_write_config8(dev, 0xaa, reg8);
+}
+
+static void i82801gx_rtc_init(struct device *dev)
{
u8 reg8;
- u32 reg32;
int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
rtc_init(rtc_failed);
}
-static void enable_hpet(struct device *dev)
+static void enable_hpet(void)
{
u32 reg32;
- u32 code = (0 & 0x3);
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 << 17); /* Enable HPET. */
- /*
- * Bits [16:15] Memory Address Range
- * 00 FED0_0000h - FED0_03FFh
- * 01 FED0_1000h - FED0_13FFh
- * 10 FED0_2000h - FED0_23FFh
- * 11 FED0_3000h - FED0_33FFh
- */
- reg32 &= ~(3 << 15); /* Clear it */
- reg32 |= (code << 15);
- /* TODO: reg32 is never written to anywhere? */
- printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
+
+ /* Leave HPET at default address, but enable it */
+ reg32 = RCBA32(0x3404);
+ reg32 |= (1 << 7); // HPET Address Enable
+ RCBA32(0x3404) = reg32;
+}
+
+static void enable_clock_gating(void)
+{
+ u32 reg32;
+
+ /* Enable Clock Gating for most devices */
+ reg32 = RCBA32(0x341c);
+ reg32 |= (1 << 31); // LPC clock gating
+ reg32 |= (1 << 30); // PATA clock gating
+ // SATA clock gating
+ reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
+ reg32 |= (1 << 23); // AC97 clock gating
+ reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating
+ reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
+ reg32 |= (1 << 2); // PCIe clock gating;
+ RCBA32(0x341c) = reg32;
}
+#if HAVE_SMI_HANDLER
static void i82801gx_lock_smm(struct device *dev)
{
void smm_lock(void);
+#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
+#endif
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk_debug("Enabling ACPI via APMC:\n");
printk_debug("Done.\n");
#endif
}
+#endif
+
+#define SPIBASE 0x3020
+static void i82801gx_spi_init(void)
+{
+ u16 spicontrol;
+
+ spicontrol = RCBA16(SPIBASE + 2);
+ spicontrol &= ~(1 << 0); // SPI Access Request
+ RCBA16(SPIBASE + 2) = spicontrol;
+}
+
+static void i82801gx_fixups(void)
+{
+ /* This needs to happen after PCI enumeration */
+ RCBA32(0x1d40) |= 1;
+}
static void lpc_init(struct device *dev)
{
/* Setup power options. */
i82801gx_power_options(dev);
+ /* Configure Cx state registers */
+ i82801gx_configure_cstates(dev);
+
/* Set the state of the GPIO lines. */
//gpio_init(dev);
isa_dma_init();
/* Initialize the High Precision Event Timers, if present. */
- enable_hpet(dev);
+ enable_hpet();
+
+ /* Initialize Clock Gating */
+ enable_clock_gating();
setup_i8259();
+#if HAVE_SMI_HANDLER
i82801gx_lock_smm(dev);
+#endif
+
+ i82801gx_spi_init();
+
+ i82801gx_fixups();
}
static void i82801gx_lpc_read_resources(device_t dev)
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- printk_debug("Setting LPC bridge subsystem ID\n");
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- pci_read_config32(dev, 0));
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
}
static struct pci_operations pci_ops = {
.ops_pci = &pci_ops,
};
-/* ICH7 / ICH7R */
+/* 82801GB/GR (ICH7/ICH7R) */
static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27b8,
};
-/* ICH7M / ICH7U */
+/* 82801GBM/GU (ICH7-M/ICH7-U) */
static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27b9,
};
-/* ICH7M DH */
+/* 82801GHM (ICH7-M DH) */
static const struct pci_driver ich7m_dh_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27bd,
};
-
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