printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / southbridge / intel / i82801ex / i82801ex_lpc.c

diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
index 39e5343fd959da6104f0f6134f7aabe34964915f..b97af3860a5e02fa1fd96b338514b1b9407538ee 100644 (file)
--- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
@@ -214,7 +214,7 @@ static void i82801ex_gpio_init(device_t dev)
 
 static void enable_hpet(struct device *dev)
 {
-const unsigned long hpet_address = 0xfed0000;
+       const unsigned long hpet_address = 0xfed00000;
 
        uint32_t dword;
        uint32_t code = (0 & 0x3);
@@ -231,8 +231,9 @@ const unsigned long hpet_address = 0xfed0000;
 
        dword &= ~(3 << 15); /* clear it */
        dword |= (code<<15);
+       pci_write_config32(dev, GEN_CNTL, dword);
 
-       printk_debug("enabling HPET @0x%lx\n", hpet_address | (code <<12) );
+       printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
 }
 
 static void lpc_init(struct device *dev)
@@ -266,7 +267,7 @@ static void lpc_init(struct device *dev)
                byte |= 1;
        }
        pci_write_config8(dev, 0xa4, byte);
-       printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+       printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
 
        /* Set up the PIRQ */
        i82801ex_pirq_init(dev);