printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / southbridge / intel / i82801dx / i82801dx_lpc.c

diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
index 8f698ee53d0b2b564f79170be939232c95831003..ae522c310b9a2fd5f6fef6e5d1278b5a73918c75 100644 (file)
--- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
@@ -53,14 +53,14 @@ static void i82801dx_enable_ioapic(struct device *dev)
        reg32 |= (1 << 1);      /* Delayed transaction enable */
        reg32 |= (1 << 2);      /* DMA collection buffer enable */
        pci_write_config32(dev, GEN_CNTL, reg32);
-       printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
+       printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
        *ioapic_index = 0;
        *ioapic_data = (1 << 25);
 
        *ioapic_index = 0;
        reg32 = *ioapic_data;
-       printk_debug("Southbridge APIC ID = %x\n", reg32);
+       printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
        if (reg32 != (1 << 25))
                die("APIC Error\n");
 
@@ -107,7 +107,7 @@ static void i82801dx_power_options(device_t dev)
         * 1 == S5 Soft Off
         */
        pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
-       printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
+       printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
 
        /* Set up NMI on errors. */
        byte = inb(0x61);
@@ -177,6 +177,30 @@ static void i82801dx_lpc_decode_en(device_t dev)
        pci_write_config16(dev, LPC_EN, 0x300F);
 }
 
+/* ICH4 does not mention HPET in the docs, but
+ * all ICH3 and ICH4 do have HPETs built in.
+ */
+static void enable_hpet(struct device *dev)
+{
+       u32 reg32;
+       u32 code = (0 & 0x3);
+
+       reg32 = pci_read_config32(dev, GEN_CNTL);
+       reg32 |= (1 << 17);     /* Enable HPET. */
+       /*
+        * Bits [16:15] Memory Address Range
+        * 00           FED0_0000h - FED0_03FFh
+        * 01           FED0_1000h - FED0_13FFh
+        * 10           FED0_2000h - FED0_23FFh
+        * 11           FED0_3000h - FED0_33FFh
+        */
+       reg32 &= ~(3 << 15);    /* Clear it */
+       reg32 |= (code << 15);
+       pci_write_config32(dev, GEN_CNTL, reg32);
+
+       printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
+}
+
 static void lpc_init(struct device *dev)
 {
        /* Set the value for PCI command register. */
@@ -207,6 +231,9 @@ static void lpc_init(struct device *dev)
 
        /* Setup decode ports and LPC I/F enables. */
        i82801dx_lpc_decode_en(dev);
+
+       /* Initialize the High Precision Event Timers */
+       enable_hpet(dev);
 }
 
 static void i82801dx_lpc_read_resources(device_t dev)