#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801cx.h"
#define NMI_OFF 0
#define MAINBOARD_POWER_ON 1
-void i82801cx_enable_ioapic( struct device *dev)
+static void i82801cx_enable_ioapic( struct device *dev)
{
uint32_t dword;
- volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000;
- volatile uint32_t* ioapic_data = (volatile uint32_t*)0xfec00010;
+ volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR;
+ volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10);
dword = pci_read_config32(dev, GEN_CNTL);
dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */
dword |= (1 << 1); /* delay transaction enable */
dword |= (1 << 2); /* DMA collection buf enable */
pci_write_config32(dev, GEN_CNTL, dword);
- printk_debug("ioapic southbridge enabled %x\n",dword);
-
+ printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword);
+
// Must program the APIC's ID before using it
*ioapic_index = 0; // Select APIC ID register
*ioapic_data = (2<<24);
-
+
// Hang if the ID didn't take (chip not present?)
*ioapic_index = 0;
dword = *ioapic_data;
- printk_debug("Southbridge apic id = %x\n", (dword>>24) & 0xF);
+ printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF);
if(dword != (2<<24))
die("");
}
// This is how interrupts are received from the Super I/O chip
-void i82801cx_enable_serial_irqs( struct device *dev)
+static void i82801cx_enable_serial_irqs( struct device *dev)
{
// Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
}
-//----------------------------------------------------------------------------------
-// Function: i82801cx_lpc_route_dma
-// Parameters: dev
-// mask - identifies whether each channel should be used for PCI DMA
-// (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-// Channel 4 is not used (reserved).
-// Return Value: None
-// Description: Route all DMA channels to either PCI or LPC.
-//
-void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
+/**
+ * Route all DMA channels to either PCI or LPC.
+ *
+ * @param dev TODO
+ * @param mask Identifies whether each channel should be used for PCI DMA
+ * (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
+ * Channel 4 is not used (reserved).
+ */
+static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
{
uint16_t dmaConfig;
int channelIndex;
pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
}
-void i82801cx_rtc_init(struct device *dev)
+static void i82801cx_rtc_init(struct device *dev)
{
uint32_t dword;
int rtc_failed;
pmcon3 |= SLEEP_AFTER_POWER_FAIL;
}
pci_write_config8(dev, GEN_PMCON_3, pmcon3);
- printk_info("set power %s after power fail\n",
+ printk(BIOS_INFO, "set power %s after power fail\n",
pwr_on ? "on" : "off");
// See if the Safe Mode jumper is set
dword = pci_read_config32(dev, GEN_STS);
rtc_failed |= dword & (1 << 2);
-
+
rtc_init(rtc_failed);
}
-void i82801cx_1f0_misc(struct device *dev)
+static void i82801cx_1f0_misc(struct device *dev)
{
// Prevent LPC disabling, enable parity errors, and SERR# (System Error)
pci_write_config16(dev, PCI_COMMAND, 0x014f);
-
+
// Set ACPI base address to 0x1100 (I/O space)
pci_write_config32(dev, PMBASE, 0x00001101);
-
+
// Enable ACPI I/O and power management
pci_write_config8(dev, ACPI_CNTL, 0x10);
-
+
// Set GPIO base address to 0x1180 (I/O space)
pci_write_config32(dev, GPIO_BASE, 0x00001181);
-
+
// Enable GPIO
pci_write_config8(dev, GPIO_CNTL, 0x10);
-
+
// Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10
pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
-
+
// Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted.
pci_write_config8(dev, PIRQE_ROUT, 0x07);
-
+
// Enable access to the upper 128 byte bank of CMOS RAM
pci_write_config8(dev, RTC_CONF, 0x04);
-
+
// Decode 0x3F8-0x3FF (COM1) for COMA port,
// 0x2F8-0x2FF (COM2) for COMB
pci_write_config8(dev, COM_DEC, 0x10);
// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
- // Enable COMA, COMB, LPT, floppy;
+ // Enable COMA, COMB, LPT, floppy;
// disable microcontroller, Super I/O, sound, gameport
pci_write_config16(dev, LPC_EN, 0x000F);
}
i82801cx_enable_ioapic(dev);
i82801cx_enable_serial_irqs(dev);
-
+
/* power after power fail */
/* FIXME this doesn't work! */
/* Which state do we want to goto after g3 (power restored)?
else
byte |= 1; // Return to S5
pci_write_config8(dev, GEN_PMCON_3, byte);
- printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+ printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
/* Set up NMI on errors */
byte = inb(0x61);
byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
- if (nmi_option) {
+ if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70);
}
-
+
/* Initialize the real time clock */
i82801cx_rtc_init(dev);
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void i82801cx_lpc_enable_resources(device_t dev)
-{
- pci_dev_enable_resources(dev);
- enable_childrens_resources(dev);
-}
-
static struct device_operations lpc_ops = {
.read_resources = i82801cx_lpc_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = i82801cx_lpc_enable_resources,
+ .enable_resources = pci_dev_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
.enable = 0,
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