Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / southbridge / intel / i82801cx / i82801cx_early_smbus.c

diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
index 9c3480283c19c6e122174542dd3d5394cf32d0f4..b62db80f9c8f91a2c702d4dacb8f179e8a480e46 100644 (file)
--- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
@@ -5,14 +5,14 @@ static void enable_smbus(void)
 {
        device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
-       print_debug("SMBus controller enabled\r\n");
+       print_debug("SMBus controller enabled\n");
        /* set smbus iobase */
        pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
        /* Set smbus enable */
        pci_write_config8(dev, HOSTC, HST_EN);
-       /* Set smbus iospace enable */ 
+       /* Set smbus iospace enable */
        pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
-       /* Disable interrupt generation */ 
+       /* Disable interrupt generation */
        outb(0, SMBUS_IO_BASE + SMBHSTCTL);
        /* clear any lingering errors, so the transaction will run */
        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
@@ -55,7 +55,7 @@ static int smbus_wait_until_ready(void)
                }
                if(loops == (SMBUS_TIMEOUT / 2)) {
                        // Clear status flags
-                       outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), 
+                       outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
                                SMBUS_IO_BASE + SMBHSTSTAT);
                }
        } while(--loops);
@@ -69,7 +69,7 @@ static int smbus_wait_until_done(void)
        do {
                unsigned char val;
                smbus_delay();
-               
+
                val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
                // !HOST_BUSY?
                if ( (val & 1) == 0) {
@@ -92,7 +92,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
        if (smbus_wait_until_ready() < 0) {
                return -2;
        }
-       
+
        /* setup transaction */
        /* disable interrupts */
        outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);