Convert some comments to proper Doxygen syntax.
[coreboot.git] / src / southbridge / intel / i82801cx / i82801cx.h
index 4cb215efbb1ff3d611d26bf561c1b238e88206d6..da518a3660ad5ee6b4eeb13ca55b732fba5ab5c4 100644 (file)
@@ -2,8 +2,10 @@
 #define I82801CX_H
 
 #if !defined(__PRE_RAM__)
+#include <device/device.h>
 #include "chip.h"
-extern void i82801cx_enable(device_t dev);
+void i82801cx_enable(device_t dev);
+void i82801cx_hard_reset(void);
 #endif
 
 
@@ -30,9 +32,7 @@ extern void i82801cx_enable(device_t dev);
 #define RTC_POWER_FAILED               (1<<1)
 #define SLEEP_AFTER_POWER_FAIL (1<<0)
 
-/********************************************************************/
-/*                                                     IDE Controller                          */
-/********************************************************************/
+/* IDE controller: */
 
 // PCI Configuration Space (D31:F1)
 #define IDE_TIM_PRI            0x40            // IDE timings, primary
@@ -42,9 +42,7 @@ extern void i82801cx_enable(device_t dev);
 // IDE_TIM bits
 #define IDE_DECODE_ENABLE      (1<<15)
 
-/********************************************************************/
-/*                                                             SMBus                               */
-/********************************************************************/
+/* SMBus: */
 
 // PCI Configuration Space (D31:F3)
 #define SMB_BASE       0x20
@@ -68,9 +66,9 @@ extern void i82801cx_enable(device_t dev);
 #define SMBTRNSADD             9
 #define SMBSLVDATA             10
 #define SMLINK_PIN_CTL 14
-#define SMBUS_PIN_CTL  15 
+#define SMBUS_PIN_CTL  15
 
-/* Between 1-10 seconds, We should never timeout normally 
+/* Between 1-10 seconds, We should never timeout normally
  * Longer than this is just painful when a timeout condition occurs.
  */
 #define SMBUS_TIMEOUT (100*1000)