Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / southbridge / intel / i82801ax / i82801ax_lpc.c

diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
index e42bac3449d79500b1fedeafcf02b955e70e8372..50be866be32c7f06a04725cd0627077e15de6f9c 100644 (file)
--- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
@@ -68,13 +68,13 @@ typedef struct southbridge_intel_i82801ax_config config_t;
 #define PIRQG 0x0A
 #define PIRQH 0x0B
 
-/* 
- * Use 0x0ef8 for a bitmap to cover all these IRQ's. 
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
  * Use the defined IRQ values above or set mainboard
  * specific IRQ values in your mainboards Config.lb.
 */
 
-void i82801ax_enable_apic(struct device *dev)
+static void i82801ax_enable_apic(struct device *dev)
 {
        uint32_t reg32;
        volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
@@ -92,14 +92,14 @@ void i82801ax_enable_apic(struct device *dev)
        reg32 |= (1 << 1);      /* Delayed transaction enable */
        reg32 |= (1 << 2);      /* DMA collection buffer enable */
        pci_write_config32(dev, GEN_CNTL, reg32);
-       printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
+       printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
        *ioapic_index = 0;
        *ioapic_data = (1 << 25);
 
        *ioapic_index = 0;
        reg32 = *ioapic_data;
-       printk_debug("Southbridge APIC ID = %x\n", reg32);
+       printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
        if (reg32 != (1 << 25))
                die("APIC Error\n");
 
@@ -108,7 +108,7 @@ void i82801ax_enable_apic(struct device *dev)
        *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
 }
 
-void i82801ax_enable_serial_irqs(struct device *dev)
+static void i82801ax_enable_serial_irqs(struct device *dev)
 {
        /* Set packet length and toggle silent mode bit. */
        pci_write_config8(dev, SERIRQ_CNTL,
@@ -189,7 +189,7 @@ static void i82801ax_power_options(device_t dev)
         * 1 == S5 Soft Off
         */
        pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
-       printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
+       printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
 
        /* Set up NMI on errors. */
        byte = inb(0x61);
@@ -220,7 +220,7 @@ static void gpio_init(device_t dev, uint16_t ich_model)
        }
 }
 
-void i82801ax_rtc_init(struct device *dev)
+static void i82801ax_rtc_init(struct device *dev)
 {
        uint8_t reg8;
        uint32_t reg32;
@@ -240,7 +240,7 @@ void i82801ax_rtc_init(struct device *dev)
        pci_write_config8(dev, RTC_CONF, 0x04);
 }
 
-void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
+static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
 {
        uint16_t reg16;
        int i;