#include <device/pci_ids.h>
#include <pc80/isa-dma.h>
#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
#include "i82371eb.h"
+static void enable_intel_82093aa_ioapic(void)
+{
+ u16 reg16;
+ u32 reg32;
+ u8 ioapic_id = 2;
+ volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+ volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+ device_t dev;
+
+ dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
+
+ /* Enable IOAPIC. */
+ reg16 = pci_read_config16(dev, XBCS);
+ reg16 |= (1 << 8); /* APIC Chip Select */
+ pci_write_config16(dev, XBCS, reg16);
+
+ /* Set the IOAPIC ID. */
+ *ioapic_index = 0;
+ *ioapic_data = ioapic_id << 24;
+
+ /* Read back and verify the IOAPIC ID. */
+ *ioapic_index = 0;
+ reg32 = (*ioapic_data >> 24) & 0x0f;
+ printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
+ if (reg32 != ioapic_id)
+ die("IOAPIC error!\n");
+}
+
static void isa_init(struct device *dev)
{
u32 reg32;
/* Initialize ISA DMA. */
isa_dma_init();
+
+#if CONFIG_IOAPIC
+ /*
+ * Unlike most other southbridges the 82371EB doesn't have a built-in
+ * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
+ * have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
+ *
+ * Thus, we can/must only enable the IOAPIC if it actually exists,
+ * i.e. the respective mainboard does "select IOAPIC".
+ */
+ enable_intel_82093aa_ioapic();
+#endif
}
static void sb_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-const struct device_operations isa_ops = {
+static const struct device_operations isa_ops = {
.read_resources = sb_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,