Please bear with me - another rename checkin. This qualifies as trivial, no

[coreboot.git] / src / southbridge / intel / i82371eb / chip.h

diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 58efa3b66ff08525d96bcbe05ea3072baa27cc23..2be0f4ffdfcafb10cab009a5e43918029053ee2a 100644 (file)
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -1,13 +1,39 @@
-#ifndef I82371EB_CHIP_H
-#define I82371EB_CHIP_H
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
-struct southbridge_intel_i82371eb_config 
-{
-       unsigned int ide0_enable : 1;
-       unsigned int ide1_enable : 1;
-};
+#ifndef SOUTHBRIDGE_INTEL_I82371EB_CHIP_H
+#define SOUTHBRIDGE_INTEL_I82371EB_CHIP_H
+
+#include <device/device.h>
 
-struct chip_operations;
-extern struct chip_operations southbridge_intel_i82371eb_ops;
+extern const struct chip_operations southbridge_intel_i82371eb_ops;
+
+struct southbridge_intel_i82371eb_config {
+       int ide0_enable:1;
+       int ide0_drive0_udma33_enable:1;
+       int ide0_drive1_udma33_enable:1;
+       int ide1_enable:1;
+       int ide1_drive0_udma33_enable:1;
+       int ide1_drive1_udma33_enable:1;
+       int ide_legacy_enable:1;
+       int usb_enable:1;
+};
 
-#endif /* I82371EB_CHIP_H */
+#endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */