Here is a proposed way how to handle the SATA PHY settings on SB700. It

[coreboot.git] / src / southbridge / amd / sb700 / sb700_sata.c

diff --git a/src/southbridge/amd/sb700/sb700_sata.c b/src/southbridge/amd/sb700/sb700_sata.c
index 48c192c95da8b5abdd0e52bc6a346d8e131b8660..5c72a98a76938ef7a15c1a351e757680e9077b54 100644 (file)
--- a/src/southbridge/amd/sb700/sb700_sata.c
+++ b/src/southbridge/amd/sb700/sb700_sata.c
@@ -26,7 +26,7 @@
 #include <arch/io.h>
 #include "sb700.h"
 
-int sata_drive_detect(int portnum, u16 iobar)
+static int sata_drive_detect(int portnum, u16 iobar)
 {
        u8 byte, byte2;
        int i = 0;
@@ -53,13 +53,36 @@ int sata_drive_detect(int portnum, u16 iobar)
        return 0;
 }
 
+       /* This function can be overloaded in mainboard.c */
+
+void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) {
+       /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
+       pci_write_config16(dev, 0x86, 0x2c00);
+
+       /* RPR7.6.2 SATA GENI PHY ports setting */
+       pci_write_config32(dev, 0x88, 0x01B48017);
+       pci_write_config32(dev, 0x8c, 0x01B48019);
+       pci_write_config32(dev, 0x90, 0x01B48016);
+       pci_write_config32(dev, 0x94, 0x01B48016);
+       pci_write_config32(dev, 0x98, 0x01B48016);
+       pci_write_config32(dev, 0x9C, 0x01B48016);
+
+       /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
+       pci_write_config16(dev, 0xA0, 0xA09A);
+       pci_write_config16(dev, 0xA2, 0xA09F);
+       pci_write_config16(dev, 0xA4, 0xA07A);
+       pci_write_config16(dev, 0xA6, 0xA07A);
+       pci_write_config16(dev, 0xA8, 0xA07A);
+       pci_write_config16(dev, 0xAA, 0xA07A);
+}
+
 static void sata_init(struct device *dev)
 {
        u8 byte;
        u16 word;
        u32 dword;
        u8 rev_id;
-       u8 *sata_bar5;
+       u32 sata_bar5;
        u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
        int i, j;
 
@@ -89,7 +112,7 @@ static void sata_init(struct device *dev)
        rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
 
        /* get base addresss */
-       sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF);
+       sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
        sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
        sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
        sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -101,7 +124,7 @@ static void sata_init(struct device *dev)
        printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
        printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
        printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
-       printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
+       printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
 
        /* disable combined mode */
        byte = pci_read_config8(sm_dev, 0xAD);
@@ -161,27 +184,7 @@ static void sata_init(struct device *dev)
        /* Program the watchdog counter to 0x10 */
        byte = 0x10;
        pci_write_config8(dev, 0x46, byte);
-
-       /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
-       word = 0x2c00;
-       pci_write_config16(dev, 0x86, word);
-
-       /* RPR7.6.2 SATA GENI PHY ports setting */
-       pci_write_config32(dev, 0x88, 0x01B48017);
-       pci_write_config32(dev, 0x8c, 0x01B48019);
-       pci_write_config32(dev, 0x90, 0x01B48016);
-       pci_write_config32(dev, 0x94, 0x01B48016);
-       pci_write_config32(dev, 0x98, 0x01B48016);
-       pci_write_config32(dev, 0x9C, 0x01B48016);
-
-       /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
-       pci_write_config16(dev, 0xA0, 0xA09A);
-       pci_write_config16(dev, 0xA2, 0xA09F);
-       pci_write_config16(dev, 0xA4, 0xA07A);
-       pci_write_config16(dev, 0xA6, 0xA07A);
-       pci_write_config16(dev, 0xA8, 0xA07A);
-       pci_write_config16(dev, 0xAA, 0xA07A);
-
+       sb700_setup_sata_phys(dev);
        /* Enable the I/O, MM, BusMaster access for SATA */
        byte = pci_read_config8(dev, 0x4);
        byte |= 7 << 0;