* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <reset.h>
#include <arch/cpu.h>
#include "sb600.h"
#include "sb600_smbus.c"
#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
/*SIZE 0x40 */
-
static void pmio_write(u8 reg, u8 value)
{
outb(reg, PM_INDEX);
return inb(PM_INDEX + 1);
}
-/* Get SB ASIC Revision.*/
+/* RPR 2.1: Get SB ASIC Revision. */
static u8 get_sb600_revision(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
/* NOT REACHED */
}
return pci_read_config8(dev, 0x08);
* Serial port 0
* KBC Port
* ACPI Micro-controller port
-* LPC ROM size
* This function does not change port 0x80 decoding.
* Console output through any port besides 0x3f8 is unsupported.
* If you use FWH ROMs, you have to setup IDSEL.
-* NOTE: Call me ASAP, because I will reset LPC ROM size!
* Reviewed-by: Carl-Daniel Hailfinger
* Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1
* (LPC ISA Bridge)
u32 reg32;
device_t dev;
- /* Enable lpc controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
+ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
+ * This bit has no meaning if debug strap is not enabled. So if the
+ * board keeps rebooting and the code fails to reach here, we could
+ * disable the debug strap first. */
+ reg32 = pci_read_config32(dev, 0x4C);
+ reg32 |= 1 << 31;
+ pci_write_config32(dev, 0x4C, reg32);
+
+ /* Enable lpc controller */
reg32 = pci_read_config32(dev, 0x64);
reg32 |= 1 << 20;
pci_write_config32(dev, 0x64, reg32);
dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */
/* Decode port 0x3f8-0x3ff (Serial 0) */
-#warning Serial port decode on LPC is hardcoded to 0x3f8
+ // XXX Serial port decode on LPC is hardcoded to 0x3f8
reg8 = pci_read_config8(dev, 0x44);
reg8 |= 1 << 6;
pci_write_config8(dev, 0x44, reg8);
reg8 |= (1 << 5) | (1 << 6);
pci_write_config8(dev, 0x47, reg8);
- /* SuperIO, LPC ROM */
+ /* Super I/O, RTC */
reg8 = pci_read_config8(dev, 0x48);
/* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
reg8 |= (1 << 1) | (1 << 0);
- /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */
- reg8 |= (1 << 3) | (1 << 4);
/* Decode port 0x70-0x73 (RTC) */
- reg8 |= 1 << 6;
+ reg8 |= (1 << 6);
pci_write_config8(dev, 0x48, reg8);
-
- /* hardware should enable LPC ROM by pin straps */
- /* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
- /* See detail in BDG-215SB600-03.pdf page 15. */
- /* enable LPC ROM range mirroring start 0x000e(0000) */
- pci_write_config16(dev, 0x68, 0x000e);
- /* enable LPC ROM range mirroring end 0x000f(ffff) */
- pci_write_config16(dev, 0x6a, 0x000f);
- /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB */
- pci_write_config16(dev, 0x6c, 0xfff0);
- /* enable LPC ROM range end at 0xffff(ffff) */
- pci_write_config16(dev, 0x6e, 0xffff);
}
/* what is its usage? */
return (dev >> 15) & 0x1f;
}
-
static u8 dual_core(void)
{
return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0;
}
/*
-SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
-RPR 2.3.3 C-state and VID/FID change for the K8 platform.
+ * SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
+ * RPR 2.3.3 C-state and VID/FID change for the K8 platform.
*/
static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
{
u8 byte;
byte = pmio_read(0x9a);
byte &= ~0x34;
- if(dual_core())
+ if (dual_core())
byte |= 0x34;
else
byte |= 0x04;
byte |= 0x01;
pmio_write(0x7c, byte);
- /*Must be 0 for K8 platform.*/
+ /* Must be 0 for K8 platform. */
byte = pmio_read(0x68);
byte &= ~0x01;
pmio_write(0x68, byte);
- /*Must be 0 for K8 platform.*/
+ /* Must be 0 for K8 platform. */
byte = pmio_read(0x8d);
byte &= ~(1<<6);
pmio_write(0x8d, byte);
byte &= ~0x04;
pmio_write(0x42, byte);
- if(get_sb600_revision() == 0x14) {
+ if (get_sb600_revision() == 0x14) {
pmio_write(0x89, 0x10);
byte = pmio_read(0x52);
}
}
-
-static void hard_reset(void)
+void hard_reset(void)
{
set_bios_reset();
outb(0x0e, 0x0cf9);
}
-static void soft_reset(void)
+void soft_reset(void)
{
set_bios_reset();
/* link reset */
outb(0x06, 0x0cf9);
}
-
-static void sb600_pci_port80(void)
+void sb600_pci_port80(void)
{
u8 byte;
device_t dev;
pci_write_config8(dev, 0x4A, byte);
}
-static void sb600_lpc_port80(void)
+void sb600_lpc_port80(void)
{
u8 byte;
device_t dev;
pci_write_config8(dev, 0x4a, byte);
}
-
/* sbDevicesPorInitTable */
static void sb600_devices_por_init(void)
{
device_t dev;
u8 byte;
- printk_info("sb600_devices_por_init()\n");
+ printk(BIOS_INFO, "sb600_devices_por_init()\n");
/* SMBus Device, BDF:0-20-0 */
- printk_info("sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
+ printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
/* NOT REACHED */
}
- printk_info("SMBus controller enabled, sb revision is 0x%x\r\n",
+ printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
get_sb600_revision());
/* sbPorAtStartOfTblCfg */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* IDE Device, BDF:0-20-1 */
- printk_info("sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
+ printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
/* Disable prefetch */
byte = pci_read_config8(dev, 0x63);
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
- printk_info("sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
+ printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
pci_write_config8(dev, 0x46, 0xC3);
pci_write_config8(dev, 0x47, 0xFF);
+ // TODO: This has already been done(?)
/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
* Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
- * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
- * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
+ * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). */
byte = pci_read_config8(dev, 0x48);
byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
- byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
byte |= 1 << 6; /* enable for RTC I/O range */
pci_write_config8(dev, 0x48, byte);
pci_write_config8(dev, 0x49, 0xFF);
byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
pci_write_config8(dev, 0x4A, byte);
- /* Set LPC ROM size, it has been done in sb600_lpc_init().
- * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
- * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
- * pci_write_config16(dev, 0x68, 0x000e)
- * pci_write_config16(dev, 0x6c, 0xfff0);*/
-
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
- printk_info("sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
+ printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* I don't know why CIM tried to write into a read-only reg! */
/*pci_write_config8(dev, 0x0c, 0x20) */ ;
pci_write_config8(dev, 0x50, 0x01);
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
- printk_info("sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
+ printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
/*PHY Global Control, we are using A14.
{
u8 byte;
- printk_info("sb600_pmio_por_init()\n");
+ printk(BIOS_INFO, "sb600_pmio_por_init()\n");
/* K8KbRstEn, KB_RST# control for K8 system. */
byte = pmio_read(0x66);
byte |= 0x20;
*/
static void sb600_early_setup(void)
{
- printk_info("sb600_early_setup()\n");
+ printk(BIOS_INFO, "sb600_early_setup()\n");
sb600_por_init();
}
projects / coreboot.git / blobdiff