ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic

[coreboot.git] / src / southbridge / amd / sb600 / sb600.c

diff --git a/src/southbridge/amd/sb600/sb600.c b/src/southbridge/amd/sb600/sb600.c
index 9a65f3830a68ff52f2a6b69e99f1ff77051e7bce..61a0c6559c7f3f6e754173ac7aa54a34c8078db9 100644 (file)
--- a/src/southbridge/amd/sb600/sb600.c
+++ b/src/southbridge/amd/sb600/sb600.c
@@ -17,20 +17,19 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <types.h>
-#include <lib.h>
-#include <console.h>
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
 #include <device/pci.h>
-#include <msr.h>
-#include <legacy.h>
 #include <device/pci_ids.h>
-#include <statictree.h>
-#include <config.h>
+#include <device/pci_ops.h>
 #include "sb600.h"
 
-static struct device * find_sm_dev(struct device * dev, u32 devfn)
+static device_t find_sm_dev(device_t dev, u32 devfn)
 {
-       struct device * sm_dev;
+       device_t sm_dev;
 
        sm_dev = dev_find_slot(dev->bus->secondary, devfn);
        if (!sm_dev)
@@ -50,7 +49,7 @@ static struct device * find_sm_dev(struct device * dev, u32 devfn)
        return sm_dev;
 }
 
-void set_sm_enable_bits(struct device * sm_dev, u32 reg_pos, u32 mask, u32 val)
+void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)
 {
        u32 reg_old, reg;
        reg = reg_old = pci_read_config32(sm_dev, reg_pos);
@@ -61,13 +60,13 @@ void set_sm_enable_bits(struct device * sm_dev, u32 reg_pos, u32 mask, u32 val)
        }
 }
 
-static void pmio_write_index(unsigned long port_base, u8 reg, u8 value)
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
 {
        outb(reg, port_base);
        outb(value, port_base + 1);
 }
 
-static u8 pmio_read_index(unsigned long port_base, u8 reg)
+static u8 pmio_read_index(u16 port_base, u8 reg)
 {
        outb(reg, port_base);
        return inb(port_base + 1);
@@ -75,29 +74,25 @@ static u8 pmio_read_index(unsigned long port_base, u8 reg)
 
 void pm_iowrite(u8 reg, u8 value)
 {
-       unsigned long port_base = 0xcd6;
-       pmio_write_index(port_base, reg, value);
+       pmio_write_index(PM_INDEX, reg, value);
 }
 
 u8 pm_ioread(u8 reg)
 {
-       unsigned long port_base = 0xcd6;
-       return pmio_read_index(port_base, reg);
+       return pmio_read_index(PM_INDEX, reg);
 }
 
 void pm2_iowrite(u8 reg, u8 value)
 {
-       unsigned long port_base = 0xcd0;
-       pmio_write_index(port_base, reg, value);
+       pmio_write_index(PM2_INDEX, reg, value);
 }
 
 u8 pm2_ioread(u8 reg)
 {
-       unsigned long port_base = 0xcd0;
-       return pmio_read_index(port_base, reg);
+       return pmio_read_index(PM2_INDEX, reg);
 }
 
-static void set_pmio_enable_bits(struct device * sm_dev, u32 reg_pos,
+static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,
                                 u32 mask, u32 val)
 {
        u8 reg_old, reg;
@@ -109,10 +104,10 @@ static void set_pmio_enable_bits(struct device * sm_dev, u32 reg_pos,
        }
 }
 
-void sb600_enable(struct device * dev)
+void sb600_enable(device_t dev)
 {
-       struct device * sm_dev = 0;
-       struct device * bus_dev = 0;
+       device_t sm_dev = 0;
+       device_t bus_dev = 0;
        int index = -1;
        u32 deviceid;
        u32 vendorid;
@@ -125,21 +120,21 @@ void sb600_enable(struct device * dev)
 
        printk(BIOS_DEBUG, "sb600_enable()\n");
 
-/*
-*      0:12.0  SATA    bit 8 of sm_dev 0xac : 1 - enable, default         + 32 * 3
-*      0:13.1  USB-1   bit 2 of sm_dev 0x68
-*      0:13.2  USB-2   bit 3 of sm_dev 0x68
-*      0:13.3  USB-3   bit 4 of sm_dev 0x68
-*      0:13.4  USB-4   bit 5 of sm_dev 0x68
-*      0:13.5  USB2    bit 0 of sm_dev 0x68 : 1 - enable, default
-*      0:14.0  SMBUS                                                   0
-*      0:14.1  IDE                                                     1
-*      0:14.2  HDA     bit 3 of pm_io 0x59 : 1 - enable, default           + 32 * 4
-*      0:14.3  LPC     bit 20 of sm_dev 0x64 : 0 - disable, default  + 32 * 1
-*      0:14.4  PCI                                                     4
-*      0:14.5  ACI     bit 0 of pm_io 0x59 : 0 - enable, default
-*      0:14.6  MCI     bit 1 of pm_io 0x59 : 0 - enable, default
-*/
+       /*
+        * 0:12.0  SATA bit 8 of sm_dev 0xac : 1 - enable, default         + 32 * 3
+        * 0:13.1  USB-1        bit 2 of sm_dev 0x68
+        * 0:13.2  USB-2        bit 3 of sm_dev 0x68
+        * 0:13.3  USB-3        bit 4 of sm_dev 0x68
+        * 0:13.4  USB-4        bit 5 of sm_dev 0x68
+        * 0:13.5  USB2 bit 0 of sm_dev 0x68 : 1 - enable, default
+        * 0:14.0  SMBUS                                                        0
+        * 0:14.1  IDE                                                  1
+        * 0:14.2  HDA  bit 3 of pm_io 0x59 : 1 - enable, default           + 32 * 4
+        * 0:14.3  LPC  bit 20 of sm_dev 0x64 : 0 - disable, default  + 32 * 1
+        * 0:14.4  PCI                                                  4
+        * 0:14.5  ACI  bit 0 of pm_io 0x59 : 0 - enable, default
+        * 0:14.6  MCI  bit 1 of pm_io 0x59 : 0 - enable, default
+        */
        if (dev->device == 0x0000) {
                vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
                deviceid = (vendorid >> 16) & 0xffff;
@@ -230,15 +225,7 @@ void sb600_enable(struct device * dev)
        }
 }
 
-struct device_operations sb600 = {
-       .id = {.type = DEVICE_ID_PCI,
-               {.pci = {.vendor = PCI_VENDOR_ID_AMD,
-                             .device = xz}}},
-       .constructor             = default_device_constructor,
-       .phase3_scan             = 0,
-       .phase4_enable_disable           = sb600_enable,
-       .phase4_read_resources   = pci_dev_read_resources,
-       .phase4_set_resources    = pci_dev_set_resources,
-       .phase6_init             = NULL,
-       .ops_pci                 = &pci_dev_ops_pci,
+struct chip_operations southbridge_amd_sb600_ops = {
+       CHIP_NAME("ATI SB600")
+       .enable_dev = sb600_enable,
 };